JP2005011862A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which hardly reduces an effective area at a circuit pattern corner, while decreasing ceramic material stress at the pattern corner and solder distortion stress under an insulating board. <P>SOLUTION: The semiconductor device comprises a heat sink and an insulating board. The insulating board is composed of a ceramic material, a circuit pattern, and a rear pattern. The ceramic material is bonded to the circuit pattern and the rear pattern with active metal or bonded direct to them, a semiconductor element is bonded to the circuit pattern through solder under the semiconductor element, and the rear pattern is bonded to the heat sink with solder under the insulating board so that all the insulating board is fixed to the heat sink. In the semiconductor device, the corner of the circuit pattern and the corner of the rear pattern are turned to a set pattern, the curvature of the corner of the rear pattern is set larger than that of the corner of the circuit pattern. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a circuit pattern is formed on the surface of an insulating substrate, a back surface pattern is formed on the back surface, and a semiconductor element is mounted on the front circuit pattern.
[0002]
[Prior art]
In the conventional semiconductor device as described above, when the semiconductor device is subjected to a thermal cycle, the insulating substrate is caused by an unmatched linear expansion coefficient between the insulating substrate made of a ceramic base material and the heat sink made of Cu or the like. The lower solder may crack. When such a crack progresses, the semiconductor element may eventually be thermally destroyed as the heat dissipating property deteriorates. Similarly, cracks may also occur in the ceramic substrate at the circuit pattern corner portion due to the mismatch of the linear expansion coefficient between the ceramic substrate and the circuit pattern made of Cu or the like. In some cases, dielectric breakdown can occur.
[0003]
In particular, it is said that cracks are likely to occur in an “offset pattern” in which the dimensional difference between the Cu pattern edge and the end face of the ceramic substrate is not the same between the circuit pattern side and the back surface pattern side.
[0004]
Therefore, as a measure for suppressing solder cracks under the insulating substrate or cracks in the ceramic substrate at the corners of the circuit pattern, the dimensional difference between the Cu pattern edge and the ceramic substrate end face is the same on the circuit pattern side and the back pattern side. The “set patterning” strategy is adopted.
[0005]
For example, in the one disclosed in Patent Document 1, a “set pattern” is formed with an Al ₂ O ₃ plate of 0.26 to 0.29 mm, or a pattern that is exactly the same as the shape of the circuit pattern. An invention has been shown in which the stress on the ceramic base material is reduced during the thermal cycle and the cracks in the ceramic base material are suppressed by forming the surface on the back surface.
[0006]
In addition, Patent Document 2 reduces the stress generated in the ceramic base material and the distortion generated in the solder under the insulating substrate by setting the double-sided pattern as a “set pattern” and limiting the thickness of the pattern on both sides. The present invention is intended to suppress cracks in ceramic substrates and solder.
[0007]
Moreover, in patent document 3, it describes that the starting point position of the copper plate of the front and back of a ceramic substrate is made to correspond. Furthermore, in patent document 4, it describes about the micro space | interval between a metal plate and an insulated substrate.
[0008]
In recent years, in addition to the use of “set patterns”, measures have been studied to increase both the curvature R of each corner portion of the circuit pattern and the back surface pattern. That is, in this way, the stress generated in the ceramic substrate of the circuit pattern / back surface pattern is further reduced, and the solder strain under the insulating substrate is reduced, thereby suppressing the solder crack.
[0009]
For example, Patent Document 5 describes the relationship between the corner curvature R and the distance d between the end of the circuit and the end of the ceramic substrate.
[0010]
However, when a large curvature R is taken at the circuit pattern corner, the effective area in the vicinity of the circuit pattern corner where the semiconductor element and the electrode terminal can be mounted decreases. Therefore, the problem that the area of the insulating substrate has to be expanded as a result still remains.
[0011]
[Patent Document 1]
JP 2000-156440 A [Patent Document 2]
JP 2002-246502 A [Patent Document 3]
Japanese Patent Laid-Open No. 06-152078 [Patent Document 4]
JP 2001-068623 A [Patent Document 5]
Japanese Patent Laid-Open No. 10-214915
[Problems to be solved by the invention]
The present invention has been made to solve the above-described problems, and does not reduce the effective area of the circuit pattern corner portion while reducing the ceramic base material stress of the pattern corner portion and the solder strain stress under the insulating substrate. An object is to present a highly efficient semiconductor device.
[0013]
[Means for Solving the Problems]
The present invention has been made to achieve the above object. A semiconductor device according to the present invention includes:
Including a heat sink and an insulating substrate;
The insulating substrate is composed of a ceramic base material, a circuit pattern and a back surface pattern, and the ceramic base material is bonded to the circuit pattern and the back surface pattern with active metal bonding or directly,
The semiconductor element is bonded to the circuit pattern via the solder under the semiconductor element,
The back surface pattern is a semiconductor device in which the entire insulating substrate is fixed to the heat sink by bonding the back surface pattern to the heat sink with solder under the substrate. In the semiconductor device,
The corner portion of the circuit pattern and the corner portion of the back pattern are formed into a set pattern, and the curvature of the corner portion of the back pattern is made larger than the curvature of the corner portion of the circuit pattern.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.
[0015]
First, as a premise for explaining a preferred embodiment according to the present invention, some embodiments of a semiconductor device according to the prior art are shown together with the drawings.
[0016]
The semiconductor device shown in FIG. 5 includes a heat sink 2 made of material Cu, Cu / Mo, Al / Sic, Al or the like and having a thickness of 3 to 5 mm, and an insulating substrate 4. The insulating substrate 4 is composed of, for example, a ceramic base 6 having a thickness of 0.635 mm, a circuit pattern 8 and a back surface pattern 10. The ceramic substrate 6 is made of, for example, AlN (aluminum nitride), Al ₂ O ₃ (alumina), Si ₃ N ₄ (silicon nitride), and the circuit pattern 8 or the back surface pattern 10 made of Cu and active metal bonding or Directly joined.
[0017]
Further, the semiconductor element 12 is bonded to the circuit pattern 8 via the semiconductor element lower solder 16. Further, the entire back surface pattern 10 is bonded to the heat sink 2 by the under-substrate solder 14, whereby the entire insulating substrate 4 is fixed to the heat sink 2. The semiconductor element 12 and the electrode terminal 22 embedded in the package case 20 are electrically joined by an aluminum wire 18. The package case 20 is bonded to the heat sink 2 with an adhesive 24. The semiconductor element 12 and the like are covered with a silcon gel 26 and the outermost surface of the package case 20 is filled with a mold resin 28.
[0018]
In the conventional semiconductor device as described above, when subjected to a thermal cycle, due to the difference in coefficient of linear expansion between the insulating substrate 4 made of the ceramic base 6 and the heat sink 2 made of Cu or the like, Cracks may occur in the solder. When such a crack progresses, the semiconductor element 12 may eventually break down due to the deterioration of heat dissipation. Similarly, cracks may also occur in the ceramic substrate 6 at the circuit pattern corner portion due to the difference in linear expansion coefficient between the ceramic substrate 6 and the circuit pattern 8 made of Cu or the like. If the crack situation worsens, dielectric breakdown may occur.
[0019]
In particular, it is said that cracks are likely to occur in an “offset pattern” in which the dimensional difference between the Cu pattern edge and the end face of the ceramic substrate 6 is not the same on the circuit pattern 8 side and the back pattern 10 side. For example, as shown in the left part of the graph of FIG. 12, when designed under the condition of Lu> Lp, the stress of the ceramic substrate 6 at the corner part on the circuit pattern 8 side becomes high and cracks are generated from the circuit pattern 8 surface side. It's easy to do. Here, “Lu” is a dimensional difference between the edge of the Cu pattern in the circuit pattern 8 and the end face of the ceramic substrate 6, and “Lp” is a Cu (corresponding value of Lp) in the back surface pattern 10. This is a dimensional difference between the pattern edge and the end face of the ceramic substrate 6. In the graph of FIG. 12 derived from the numerical analysis, the horizontal axis indicates the magnitude of Lp with respect to Lu, and the vertical axis indicates the stress ratio of the pattern edge portion (circuit / back surface). In FIG. 12, the stress on the circuit pattern side at “Lp = 1/4 Lu” is set to “1.0”. “ΔT = 82.5 K” indicates a temperature change, and “tp = 0.4 tu” indicates a relationship between the circuit pattern thickness “tu” and the back surface pattern thickness “tp”.
[0020]
Therefore, as a measure for suppressing solder cracks under the insulating substrate 4 or as a measure for suppressing cracks in the ceramic base 6 at the corners of the circuit pattern 8, the dimensional difference between the Cu pattern edge and the end face of the ceramic base 6 is determined. “Set patterning” is used which is the same on the 8 side and the back surface pattern 10 side.
[0021]
6, FIG. 7, FIG. 8 and FIG. 9 show examples of the form of a semiconductor device according to the prior art. In each of the drawings, (1) is a (partial) plan view from above with a corner portion as the center, and (2) is an enlarged longitudinal sectional view taken along a section AA and a section BB of (1).
[0022]
For example, the apparatus shown in FIG. 7 introduces “set patterning”, and the apparatus shown in FIG. 9 additionally has a large curvature R at each corner of the circuit pattern and the back pattern. On the other hand, the configuration shown in FIG. 6 adopts an “offset pattern” (conventional) configuration, and the configuration shown in FIG. 8 uses an “offset pattern” in which the curvature R of the corner portion of the circuit pattern is increased.
[0023]
Certainly, the crack suppression can be achieved by adopting the “set pattern” (see FIGS. 7 and 9) rather than employing the “offset pattern” (see FIGS. 6 and 8). Furthermore, if the curvature R of each corner part of a circuit pattern and a back surface pattern is made large (refer FIG. 9), further high reliability can be calculated | required. That is, in this case, the stress generated in the ceramic base 6 of the circuit pattern / back surface pattern is further reduced, and the solder strain under the insulating substrate is reduced as shown in FIG. FIG. 10 is a graph showing the dependency of the curvature R of the back surface pattern corner portion on the solder strain under the insulating substrate. The abscissa indicates the curvature R, and the ordinate indicates the solder strain ratio under the insulating substrate where the solder strain under the insulating substrate when R = 0 is “1.0”.
[0024]
From the viewpoint of structural strength, the apparatus shown in FIG. 9 seems to be desirable. However, in the case of the structure shown in FIG. 9, since a large curvature R is taken at the circuit pattern corner, a semiconductor element or electrode near the circuit pattern corner is used. The effective area where terminals can be mounted decreases. As a result, there remains a problem that the area of the insulating substrate must be enlarged.
[0025]
Embodiment 1 FIG.
1, (1) a partial plan view (centered around a corner) of the semiconductor device according to the first embodiment of the present invention, and (2) a cross section AA and a cross section BB of (1). FIG. The ceramic substrate 6, the circuit pattern 8, and the back surface pattern 10 are shown in the partial enlarged view of the semiconductor device according to the first embodiment. Only the pattern corner portions of the circuit pattern 8 and the back surface pattern 10 are “set pattern”.
[0026]
Further, the curvature R of the corner portion of the circuit pattern 8 is the same as the curvature of the circuit pattern corner portion of the device shown in FIG. The corner curvature of the apparatus (shown in FIG. 7), for example, about 3 times larger than about 2.5 mm (for example, about 7 mm). The “offset” amount of both patterns in the peripheral portion other than the corner portion is the same as that of the conventional device, for example, the device shown in FIG.
[0027]
In the structure as described above, as shown in the graph of the point where the stress at the pattern edge portion of the insulating substrate is “Lp = Lu” in FIG. Balance on the back pattern side. Therefore, the occurrence and development of cracks from the circuit surface are suppressed as compared with the prior art.
[0028]
Further, FIG. 13 shows that the solder strain under the insulating substrate 4 is reduced by forming a set pattern in the corner portion where the strain is most likely to concentrate. In the graph of FIG. 13, the horizontal axis represents the ratio of the length of “Lp” to “Lu”, and the vertical axis represents the solder strain under the insulating substrate when “Lp = 1/4 Lu” is “1.0”. It shows the solder strain ratio under the insulating substrate. For example, when the strain ratio when “Lp = 1/3 Lu” is compared with the strain ratio when “Lp = Lu”, it can be seen that the strain ratio decreases to about ½. Further, as the curvature R of the back surface pattern corner portion is increased from about 2.5 mm to about 7 mm, the distortion ratio is approximately from about “0.63” to about “0.43” as shown in FIG. It will be reduced by 30%.
[0029]
FIG. 11 is a graph showing the solder crack length (measured value) at the lower corner portion of the insulating substrate with respect to the number of heat cycles when the curvature R of the back surface pattern corner portion is 2.5 mm or 7 mm. Here, it is shown that when the curvature R of the back surface pattern corner portion increases from 2.5 mm to 7 mm, the solder crack length of the lower corner portion of the insulating substrate with respect to the number of heat cycles is reduced by about 40%.
[0030]
Further, in the first embodiment, the curvature R of the circuit pattern corner portion is substantially the same as that of the conventional one (that is, for example, about 2.5 mm). Therefore, in the prior art apparatus shown in FIG. Has become a problem,
・ "Effective area for mounting semiconductor elements and electrode terminals near the circuit pattern corner decreases"
That cannot happen.
[0031]
Embodiment 2. FIG.
2, (1) a partial plan view (centered around a corner) of the semiconductor device according to the second embodiment of the present invention, and (2) a cross section AA and a cross section BB of (1), FIG. The semiconductor device according to the second embodiment is substantially the same as the semiconductor device according to the first embodiment. Therefore, the same parts are denoted by the same reference numerals, description thereof is omitted, and differences will be mainly described.
[0032]
In the semiconductor device shown in FIG. 2, the curvature R of the corner portion of the circuit pattern 8 is made larger than that of the first embodiment (FIG. 1) and “set patterning” is performed.
[0033]
Accordingly, not only the same effects as those of the first embodiment can be obtained, but also the stress on the ceramic substrate at the circuit pattern corner portion tends to be further reduced as compared with the first embodiment because the curvature increases (see FIG. 10). ).
[0034]
Embodiment 3 FIG.
3, (1) a partial plan view (centered around the corner) of the semiconductor device according to the third embodiment of the present invention, and (2) a cross section AA and a cross section BB of (1), FIG. Further, FIG. 4 shows a partially cutaway longitudinal sectional view of the semiconductor device according to the third embodiment of the present invention. FIG. 4 shows in particular the corner and electrode terminals. The semiconductor device according to the third embodiment is substantially the same as the semiconductor device according to the first or second embodiment. Therefore, the same parts are denoted by the same reference numerals, description thereof is omitted, and differences will be mainly described.
[0035]
3 and 4, the semiconductor device according to the third embodiment includes a brazing material 30 that joins the circuit pattern 8 or the back surface pattern 10 to the ceramic substrate 6. The brazing material 30 contains an active metal such as Ag, Cu, or Ti as a component. However, there is an unjoined portion 32 where the brazing material 30 is not disposed between the circuit pattern 8 and the ceramic substrate 6. That is, when the circuit pattern 8 and the back surface pattern 10 are overlapped with each other, the circuit pattern 8 is located between the circuit pattern 8 and the ceramic substrate 6 only in a portion where the circuit pattern 8 protrudes outward (in the corner portion) from the back surface pattern 10. The brazing material 30 is not disposed. A portion where the brazing material 30 is not disposed becomes an unjoined portion 32.
[0036]
Further, the curvature R of the corner portion of the circuit pattern 8 is the same as the curvature of the circuit pattern corner portion of the device shown in FIGS. 6 and 7 of the prior art, but the curvature R of the corner portion of the back pattern 10 is, for example, It has a larger value (for example, about 10 mm) than the embodiment shown in FIGS. 1 and 2 (Embodiment 1 and Embodiment 2).
[0037]
Therefore, in the third embodiment, not only the effect similar to “set patterning” can be obtained, but also the increase in the curvature R of the corner portion of the back surface pattern 10 can reduce the solder distortion under the insulating substrate. (FIG. 10).
[0038]
Further, if the electrode terminals 22 are arranged at the corners of the circuit pattern 8 as shown in FIG. 4, the electrode terminals 22 and the electrode terminal bonding solder at the time of the thermal cycle due to the flexibility of the circuit pattern 8 including the unbonded portion 32. The tensile / compressive stress applied to 34 can be relaxed. Furthermore, since the corner portion can also be used as a wire bond position, the effective area of the corner portion of the circuit pattern 8 does not decrease.
[0039]
【The invention's effect】
As described above, while maintaining the effective area of the circuit pattern corner portion, “set pattern” is realized at the corner portion of the circuit pattern and the back surface pattern, and the curvature R of the back surface pattern corner portion is the conventional one. In semiconductor devices that are several times larger than
(1) “Set patterning” reduces the stress on the ceramic substrate generated at the circuit pattern edge at the corner.
(2) “Set patterning” reduces solder distortion under the insulating substrate.
(3) An effective area of the circuit pattern corner can be secured.
An extremely efficient and highly reliable semiconductor device can be obtained.
[Brief description of the drawings]
1A is a partial plan view of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is an enlarged longitudinal sectional view taken along a section AA and a section BB in FIG.
2A is a partial plan view of a semiconductor device according to a second embodiment of the present invention, and FIG. 2B is an enlarged longitudinal sectional view taken along a section AA and a section BB in FIG.
FIGS. 3A and 3B are a partial plan view of a semiconductor device according to a third embodiment of the present invention, and an enlarged longitudinal sectional view taken along a section AA and a section BB in FIG.
FIG. 4 is an enlarged longitudinal sectional view in the vicinity of a corner portion and electrode terminals of a semiconductor device according to a third embodiment of the present invention.
FIG. 5 is an enlarged longitudinal sectional view of a conventional semiconductor device.
6 is a partial plan view of a semiconductor device according to the prior art, and (2) an enlarged longitudinal sectional view taken along a section AA and a section BB of (1). FIG.
7 is a partial plan view of a semiconductor device according to the prior art, and (2) an enlarged longitudinal sectional view taken along a section AA and a section BB in (1). FIG.
8 is a partial plan view of a semiconductor device according to the prior art, and (2) an enlarged longitudinal sectional view taken along a section AA and a section BB of (1). FIG.
FIG. 9 is a partial plan view of a semiconductor device according to the prior art, and (2) an enlarged longitudinal sectional view taken along a section AA and a section BB in (1).
FIG. 10 is a graph showing the dependence of the curvature R of the back surface pattern corner portion on the solder distortion under the insulating substrate.
FIG. 11 is a graph showing the length of a solder crack in the lower corner portion of the insulating substrate with respect to the number of heat cycles when the curvature R of the back surface pattern corner portion is 2.5 mm or 7 mm.
FIG. 12 is a graph showing the relationship between Lu and Lp and the stress (ratio) at the pattern edge portion.
FIG. 13 is a graph showing the relationship between Lu and Lp and solder strain (ratio) under the insulating substrate.
[Explanation of symbols]
2 Heat sink, 4 Insulating substrate, 6 Ceramic substrate, 8 Circuit pattern, 10 Back pattern, 12 Semiconductor element, 14 Substrate solder, 16 Semiconductor element solder, 18 Aluminum wire, 20 Package case, 22 Electrode terminal, 24 Adhesive , 26 silicon gel, 28 mold resin, 30 brazing material, 32 unjoined part, 34 electrode terminal joining solder.

Claims (3)

Including a heat sink and an insulating substrate;
The insulating substrate is composed of a ceramic base material, a circuit pattern and a back surface pattern, and the ceramic base material is bonded to the circuit pattern and the back surface pattern with active metal bonding or directly,
The semiconductor element is bonded to the circuit pattern via the solder under the semiconductor element,
The back surface pattern is bonded to the heat sink with solder under the substrate, so that the entire insulating substrate is fixed to the heat sink.
In semiconductor devices,
The corner portion of the circuit pattern and the corner portion of the back pattern are set pattern, and the curvature of the corner portion of the back pattern is larger than the curvature of the corner portion of the circuit pattern,
Semiconductor device. Including a heat sink and an insulating substrate;
The insulating substrate is composed of a ceramic base material, a circuit pattern and a back surface pattern, and the ceramic base material is bonded to the circuit pattern and the back surface pattern with active metal bonding or directly,
The semiconductor element is bonded to the circuit pattern via the solder under the semiconductor element,
The back surface pattern is bonded to the heat sink with solder under the substrate, so that the entire insulating substrate is fixed to the heat sink.
In semiconductor devices,
The corner part of the circuit pattern and the corner part of the back pattern are set pattern, and the vicinity other than the corner part of the circuit pattern and the vicinity other than the corner part of the back pattern are offset pattern,
The curvature of the corner portion of the circuit pattern is smaller than the curvature of the corner portion of the back pattern, but in the vicinity of the corner portion of the circuit pattern, the circuit pattern edge protrudes outward from the linear portion in the vicinity.
Semiconductor device. Including a heat sink and an insulating substrate;
The insulating substrate is composed of a ceramic base material, a circuit pattern, and a back surface pattern, and the ceramic base material is joined to the circuit pattern and the back surface pattern via a brazing material,
The semiconductor element is bonded to the circuit pattern via the solder under the semiconductor element,
The back surface pattern is bonded to the heat sink with solder under the substrate, so that the entire insulating substrate is fixed to the heat sink.
In semiconductor devices,
The curvature of the corner of the circuit pattern is smaller than the curvature of the corner of the back pattern,
When the corner part of the circuit pattern is superimposed on the ceramic substrate perpendicularly to the corner part of the back pattern, it protrudes outward.
The vicinity of the circuit pattern other than the corner and the vicinity of the back pattern other than the corner are offset patterns,
There is no brazing material between the portion of the corner portion of the circuit pattern that protrudes outward from the corner portion of the back surface pattern and the ceramic substrate, and only the protruding portion is separated from the ceramic substrate. And
Therefore, the part joined to the ceramic substrate by the brazing material at the corner portion of the circuit pattern and the corner portion of the back surface pattern are set patterns,
Semiconductor device.

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