JP2010232545A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010232545A
JP2010232545A JP2009080437A JP2009080437A JP2010232545A JP 2010232545 A JP2010232545 A JP 2010232545A JP 2009080437 A JP2009080437 A JP 2009080437A JP 2009080437 A JP2009080437 A JP 2009080437A JP 2010232545 A JP2010232545 A JP 2010232545A
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metal plate
insulating substrate
semiconductor device
corner
sides
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Masami Ogura
正巳 小倉
Norito Takayanagi
教人 高柳
Tomoko Yamada
友子 山田
Jun Kato
潤 加藤
Tsugio Masuda
次男 増田
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Honda Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having superior durable reliability. <P>SOLUTION: The semiconductor device 1 includes a semiconductor element 7 bonded on a metal plate 3a of an insulating substrate 5 via a solder layer 6, and a heat-radiating metal plate 9 bonded on a metal plate 4 via a solder layer 8. The metal plate 3 has a rectangular shape containing two pairs of sides 3a and 3b parallel to each other and angle parts 3c connecting the sides 3a and 3b. The metal plate 4 has a rectangular shape containing two pairs of sides 4a and 4b parallel to each other and angle parts 4c connecting the sides 4a and 4b. The metal plate 4 has an area larger than the metal plate 3. The metal plates 3 and 4 are so laminated that each of sides 3a and 4a, and each of sides 3b and 4b become parallel to each other via the insulating substrate 5, and at least a part of the angle part 3c overlaps with the angle part 4c. The insulating substrate 5 is formed of one kind of ceramics selected from a group of an Si<SB>3</SB>N<SB>4</SB>, an AlN and an Al<SB>2</SB>O<SB>3</SB>, and the metal plates 3 and 4 is formed of a Cu or an Al. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、電気自動車やハイブリッド車等の電動機の電力変換装置として用いられる半導体装置に関するものである。   The present invention relates to a semiconductor device used as a power conversion device for an electric motor such as an electric vehicle or a hybrid vehicle.

電気自動車やハイブリッド車等の電動機の電力変換装置として、従来、半導体パワー素子を用いる半導体装置が知られている。   2. Description of the Related Art Conventionally, semiconductor devices using semiconductor power elements are known as power conversion devices for electric motors such as electric vehicles and hybrid vehicles.

前記半導体装置は、前記電力変換装置として用いられるときには、大電圧が印加されることに伴って発熱量も大になる。そこで、半導体素子が搭載された基板の該半導体素子とは反対側の面に、ハンダ層を介して放熱板を接合した半導体装置が知られている（例えば特許文献１参照）。   When the semiconductor device is used as the power converter, the amount of heat generated increases as a large voltage is applied. Therefore, a semiconductor device is known in which a heat sink is joined to a surface of a substrate on which a semiconductor element is mounted on the side opposite to the semiconductor element via a solder layer (see, for example, Patent Document 1).

前記従来の半導体装置によれば、前記半導体素子に大電圧が印加されたときの発熱を前記放熱板により、外部に逃がすことができる。しかし、前記半導体装置では、前記基板と前記放熱板とが前記発熱により熱膨張すると、線膨張係数の相違により互いに剥離することがあるという問題がある。   According to the conventional semiconductor device, heat generated when a large voltage is applied to the semiconductor element can be released to the outside by the heat radiating plate. However, the semiconductor device has a problem that when the substrate and the heat radiating plate are thermally expanded due to the heat generation, they may be separated from each other due to a difference in coefficient of linear expansion.

前記問題を解決するために、前記基板として、セラミックスからなる基板の表裏両面に金属板を備える絶縁基板を用いることが考えられる。前記絶縁基板において、前記金属板がＣｕからなるものはＤＣＢ(Direct Copper Bonding)基板として公知である。   In order to solve the above problem, it is conceivable to use an insulating substrate having metal plates on both the front and back surfaces of a ceramic substrate as the substrate. In the insulating substrate, the metal plate made of Cu is known as a DCB (Direct Copper Bonding) substrate.

前記絶縁基板によれば、前記金属板の厚さ、大きさ等により、該絶縁基板全体の線膨張係数を調整することができる。そこで、前記絶縁基板の第１の金属板上にハンダ層を介して前記半導体素子を接合すると共に、第２の金属板上にハンダ層を介して放熱板を接合することにより、該絶縁基板と該放熱板とが熱膨張したときにも互いに剥離することを防止することができると期待される。   According to the insulating substrate, the linear expansion coefficient of the entire insulating substrate can be adjusted by the thickness, size, etc. of the metal plate. Therefore, the semiconductor element is bonded to the first metal plate of the insulating substrate via a solder layer, and the heat sink is bonded to the second metal plate via a solder layer, thereby It is expected that separation from each other can be prevented even when the heat radiating plate is thermally expanded.

前記絶縁基板を備える半導体装置では、前記絶縁基板に備えられる各金属板は互いに平行な２組の辺と、相隣り合う２辺を接続する角部とからなる矩形状を備え、該角部は例えば円弧状とされている。そして、第２の金属板は、放熱効率を向上すると共に、前記セラミックス基板に対する応力を軽減するために第１の金属板より大面積であり、平面視したときに第１の金属板が第２の金属板の内周側に配置されるように、該セラミックス基板を介して積層されている。   In the semiconductor device including the insulating substrate, each metal plate provided in the insulating substrate has a rectangular shape including two sets of sides parallel to each other and corners connecting two adjacent sides. For example, it has an arc shape. The second metal plate has a larger area than the first metal plate in order to improve heat dissipation efficiency and reduce stress on the ceramic substrate, and the first metal plate is second when viewed in plan. It is laminated via the ceramic substrate so as to be disposed on the inner peripheral side of the metal plate.

しかしながら、前記半導体装置では、経時的に、前記ハンダ層の第２の金属板との界面付近に応力集中による亀裂が生じ、耐久信頼性が低減するという不都合がある。   However, the semiconductor device has a disadvantage in that cracks due to stress concentration occur near the interface between the solder layer and the second metal plate over time, and durability reliability is reduced.

特開２００７−１４１９４８号公報JP 2007-141948 A

本発明は、かかる不都合を解消して、優れた耐久信頼性を備える半導体装置を提供することを目的とする。   An object of the present invention is to provide a semiconductor device that eliminates such disadvantages and has excellent durability and reliability.

かかる目的を達成するために、本発明は、表裏両面に金属板を備える絶縁基板と、該絶縁基板の第１の金属板上に第１のハンダ層を介して接合されている半導体素子と、該絶縁基板の第２の金属板上に第２のハンダ層を介して接合されている放熱用金属板とを備え、該絶縁基板に備えられる各金属板は互いに平行な２組の辺と、相隣り合う２辺を接続する角部とからなる矩形状を備え、第２の金属板は第１の金属板より大面積であり、第１の金属板と第２の金属板とは該絶縁基板を介して各辺が平行となるように積層されている半導体装置であって、第２の金属板の各角部の少なくとも一部が第１の金属板の各角部と重なるように積層されていることを特徴とする。   In order to achieve such an object, the present invention provides an insulating substrate having metal plates on both front and back surfaces, and a semiconductor element bonded to the first metal plate of the insulating substrate via a first solder layer, A heat dissipating metal plate joined on a second metal plate of the insulating substrate via a second solder layer, each metal plate provided on the insulating substrate having two sets of sides parallel to each other; It has a rectangular shape composed of corners connecting two adjacent sides, the second metal plate has a larger area than the first metal plate, and the first metal plate and the second metal plate are insulated from each other. A semiconductor device is laminated so that each side is parallel through a substrate, and is laminated so that at least a part of each corner of the second metal plate overlaps each corner of the first metal plate It is characterized by being.

本発明の半導体装置において、前記絶縁基板は、表裏両面に設けられた前記第１、第２の両金属板の厚さ、大きさ等により、該絶縁基板全体の線膨張係数を調整することができる。そこで、本発明の半導体装置は、第１の金属板上に半導体素子が接合されると共に、第２の金属板上に放熱用金属板が接合される構成を備えることにより、該絶縁基板と該放熱板とが熱膨張により互いに剥離することを防止することができる。   In the semiconductor device of the present invention, the insulating substrate can be adjusted in linear expansion coefficient of the entire insulating substrate by the thickness, size, etc. of the first and second metal plates provided on both the front and back surfaces. it can. Therefore, the semiconductor device of the present invention includes a structure in which a semiconductor element is bonded to the first metal plate and a heat dissipation metal plate is bonded to the second metal plate, so that the insulating substrate and the It is possible to prevent the heat sink from being separated from each other due to thermal expansion.

また、本発明の半導体装置において、前記第１、第２の両金属板は、互いに平行な２組の辺と、相隣り合う２辺を接続する角部とからなる矩形状を備えている。また、第２の金属板は第１の金属板より大面積であり、第１の金属板と第２の金属板とは前記絶縁基板を介して各辺が平行となるように積層されている。   In the semiconductor device of the present invention, each of the first and second metal plates has a rectangular shape including two sets of sides parallel to each other and corners connecting two adjacent sides. In addition, the second metal plate has a larger area than the first metal plate, and the first metal plate and the second metal plate are laminated so that each side is parallel through the insulating substrate. .

そして、本発明の半導体装置では、第１の金属板の各角部の少なくとも一部が第２の金属板の各角部と重なるように積層されている。この結果、本発明の半導体装置によれば、第２のハンダ層の第２の金属板との界面付近における応力集中を緩和することができ、該界面付近における経時的な亀裂の発生を低減して、優れた耐久信頼性を得ることができる。   And in the semiconductor device of this invention, it laminates | stacks so that at least one part of each corner | angular part of a 1st metal plate may overlap with each corner | angular part of a 2nd metal plate. As a result, according to the semiconductor device of the present invention, the stress concentration in the vicinity of the interface between the second solder layer and the second metal plate can be relaxed, and the generation of cracks over time near the interface can be reduced. Excellent durability and reliability can be obtained.

前記応力集中を緩和するために、第１の金属板の各角部は、第２の金属板の各角部と接していることが好ましいが、該応力集中を緩和することができる範囲であれば、第１の金属板の各角部が第２の金属板の各角部から外方に突出していてもよい。   In order to alleviate the stress concentration, each corner of the first metal plate is preferably in contact with each corner of the second metal plate, but the stress concentration can be alleviated. For example, each corner of the first metal plate may protrude outward from each corner of the second metal plate.

また、本発明の半導体装置において、前記絶縁基板は、セラミックス基板の表裏両面に前記金属板を備えることにより、該絶縁基板全体の線膨張係数を容易に調整することができる。前記セラミックス基板は、例えば、Ｓｉ３Ｎ４、ＡｌＮ、Ａｌ２Ｏ３からなる群から選択される１種のセラミックスからなるものを好適に用いることができる。また、前記金属板は、例えば、ＣｕまたはＡｌのいずれか１種の金属からなるものを好適に用いることができる。 In the semiconductor device of the present invention, the insulating substrate includes the metal plates on both the front and back surfaces of the ceramic substrate, whereby the linear expansion coefficient of the entire insulating substrate can be easily adjusted. As the ceramic substrate, for example, a substrate made of one kind of ceramic selected from the group consisting of Si 3 N 4 , AlN, and Al 2 O 3 can be suitably used. Moreover, the said metal plate can use suitably what consists of any 1 type of metal of Cu or Al, for example.

本発明の半導体装置の一構成例を示す説明的断面図。FIG. 6 is an explanatory cross-sectional view illustrating a structural example of a semiconductor device of the present invention. 図１に示す半導体装置を半導体素子の方向から見た平面図。The top view which looked at the semiconductor device shown in FIG. 1 from the direction of the semiconductor element. 本発明の半導体装置の一構成例を半導体素子の方向から見た平面図。The top view which looked at the example of 1 structure of the semiconductor device of this invention from the direction of the semiconductor element. 比較例の半導体装置の構成を半導体素子の方向から見た平面図。The top view which looked at the structure of the semiconductor device of the comparative example from the direction of the semiconductor element. 図１に示す半導体装置に対して熱サイクル試験を行ったときの亀裂発生率を示すグラフ。The graph which shows the crack generation rate when a heat cycle test is done with respect to the semiconductor device shown in FIG.

次に、添付の図面を参照しながら本発明の実施の形態についてさらに詳しく説明する。   Next, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

図１に示すように、本実施形態の半導体装置１は、セラミックス基板２の表裏両面に金属板３，４が接合されている絶縁基板５を備えている。絶縁基板５の金属板３には、ハンダ層６を介して半導体素子としての半導体パワー素子７が接合されている。また、絶縁基板５の金属板４には、ハンダ層８を介して放熱用金属板としてのヒートシンク９が接合されている。   As shown in FIG. 1, the semiconductor device 1 of this embodiment includes an insulating substrate 5 in which metal plates 3 and 4 are bonded to both front and back surfaces of a ceramic substrate 2. A semiconductor power element 7 as a semiconductor element is bonded to the metal plate 3 of the insulating substrate 5 via a solder layer 6. Further, a heat sink 9 as a heat radiating metal plate is joined to the metal plate 4 of the insulating substrate 5 via a solder layer 8.

セラミックス基板２としては、例えば、Ｓｉ３Ｎ４、ＡｌＮ、Ａｌ２Ｏ３からなる群から選択される１種のセラミックスからなるものを好適に用いることができる。また、金属板３，４としては、例えば、ＣｕまたはＡｌのいずれか１種の金属からなるものを好適に用いることができる。 As the ceramic substrate 2, for example, a substrate made of one kind of ceramic selected from the group consisting of Si 3 N 4 , AlN, and Al 2 O 3 can be suitably used. Moreover, as the metal plates 3 and 4, for example, those made of any one of Cu and Al can be suitably used.

ハンダ層６を形成するハンダは、金属板３と半導体パワー素子７とを接合できるものであればどのようなものであってもよい。また、ハンダ層８を形成するハンダは、金属板４とヒートシンク９とを接合できるものであればどのようなものであってもよい。   The solder for forming the solder layer 6 may be any solder as long as it can join the metal plate 3 and the semiconductor power element 7. The solder for forming the solder layer 8 may be any solder that can join the metal plate 4 and the heat sink 9.

図２に示すように、金属板３は、互いに平行な２組の辺３ａ，３ｂと、相隣り合う２辺３ａ，３ｂを接続する角部３ｃとからなる矩形状を備えている。角部３ｃは、所定の半径を備える円弧状を備えている。   As shown in FIG. 2, the metal plate 3 has a rectangular shape including two sets of sides 3 a and 3 b that are parallel to each other and a corner 3 c that connects the two sides 3 a and 3 b adjacent to each other. The corner 3c has an arc shape with a predetermined radius.

また、金属板４は、互いに平行な２組の辺４ａ，４ｂと、相隣り合う２辺４ａ，４ｂを接続する角部４ｃとからなる矩形状を備えている。角部４ｃは、角部３ｃより大きな所定の半径を備える円弧状を備えている。   Further, the metal plate 4 has a rectangular shape composed of two sets of sides 4a and 4b parallel to each other and a corner portion 4c connecting the two adjacent sides 4a and 4b. The corner 4c has an arc shape having a predetermined radius larger than that of the corner 3c.

そして、金属板３，４は、辺３ａ，４ａと、辺３ｂ，４ｂとが互いに平行となるようにされて、金属板３が金属板４の内周側に配置されると共に、角部３ｃが角部４ｃに接するように、セラミックス基板２を介して積層されている。   The metal plates 3 and 4 are arranged such that the sides 3a and 4a and the sides 3b and 4b are parallel to each other, the metal plate 3 is disposed on the inner peripheral side of the metal plate 4, and the corner 3c. Are stacked via the ceramic substrate 2 so as to be in contact with the corner 4c.

尚、図２は、ハンダ層６，８、半導体パワー素子７を省略して示している。   In FIG. 2, the solder layers 6 and 8 and the semiconductor power element 7 are omitted.

本実施形態の半導体装置１によれば、金属板３，４が前述のように積層されているので、半導体パワー素子７による発熱と冷却とが繰り返されても、経時的にハンダ層８の金属板４との界面付近に生じる応力集中を低減することができる。この結果、半導体装置１によれば、経時的にハンダ層８の金属板４との界面付近における経時的な亀裂の発生を低減して、優れた耐久信頼性を得ることができる。   According to the semiconductor device 1 of the present embodiment, since the metal plates 3 and 4 are laminated as described above, even if heat generation and cooling by the semiconductor power element 7 are repeated, the metal of the solder layer 8 over time. Stress concentration generated near the interface with the plate 4 can be reduced. As a result, according to the semiconductor device 1, it is possible to reduce the generation of cracks with time in the vicinity of the interface between the solder layer 8 and the metal plate 4 over time, and to obtain excellent durability reliability.

また、金属板４は、図３に示すように、辺４ａ，４ｂを結ぶ直線からなる角部４ｃを備えていてもよい。この場合、角部３ｃは、角部４ｃを形成する前記直線に接している。   Moreover, the metal plate 4 may be provided with the corner | angular part 4c which consists of a straight line which connects edge | side 4a, 4b, as shown in FIG. In this case, the corner 3c is in contact with the straight line forming the corner 4c.

本実施形態では、角部３ｃは角部４ｃに接するようにしているが、ハンダ層８の金属板４との界面付近に生じる前記応力集中を低減することができる範囲であれば、角部３ｃが角部４ｃから外方に突出していてもよい。   In the present embodiment, the corner 3c is in contact with the corner 4c. However, the corner 3c is within a range where the stress concentration occurring near the interface between the solder layer 8 and the metal plate 4 can be reduced. May protrude outward from the corner 4c.

次に、図１及び図２に示す半導体装置１を実施例とし、図４に示す半導体装置１０を比較例として、ハンダ層８の金属板４との界面付近における亀裂の発生を比較した。   Next, using the semiconductor device 1 shown in FIGS. 1 and 2 as an example and the semiconductor device 10 shown in FIG. 4 as a comparative example, the occurrence of cracks in the vicinity of the interface between the solder layer 8 and the metal plate 4 was compared.

図４に示す半導体装置１０は、金属板４の角部４ｃが金属板３の角部３ｃと同一の半径の円弧状であり、角部３ｃが角部４ｃの内周側に位置していて、角部４ｃに接していないことを除いて、図１及び図２に示す半導体装置１と全く同一の構成を備えている。   In the semiconductor device 10 shown in FIG. 4, the corner 4c of the metal plate 4 has an arc shape with the same radius as the corner 3c of the metal plate 3, and the corner 3c is located on the inner peripheral side of the corner 4c. The semiconductor device 1 has the same configuration as that of the semiconductor device 1 shown in FIGS. 1 and 2 except that it does not contact the corner 4c.

次に、半導体装置１，１０をそれぞれ6個ずつ用意し、半導体装置１，１０を加熱炉に入れて、半導体装置１，１０を１０５〜１５０℃の範囲の温度、例えば１２５℃の温度に３０分間保持した後、冷却して−４０℃の温度に３０分間保持する操作を１サイクルとして、熱サイクル試験を行った。そして、各サイクル毎に、ハンダ層８の金属板４との界面付近にいて亀裂が発生した半導体装置１，１０の数を調べ、全数で除することにより、亀裂発生率を算出した。結果を図５に示す。 Next, six semiconductor devices 1 and 10 are prepared, and the semiconductor devices 1 and 10 are put in a heating furnace, and the semiconductor devices 1 and 10 are heated to a temperature in the range of 105 to 150 ° C., for example, a temperature of 125 ° C. After being held for 1 minute, the operation of cooling and holding at a temperature of −40 ° C. for 30 minutes was taken as one cycle, and a thermal cycle test was conducted. Then, for each cycle, the number of semiconductor devices 1 and 10 in the vicinity of the interface between the solder layer 8 and the metal plate 4 and cracks was examined and divided by the total number to calculate the crack occurrence rate. The results are shown in FIG.

図５から、半導体装置１０（比較例）は１００サイクル付近で前記亀裂が発生し始めるのに対し、半導体装置１（実施例）は１５００サイクル付近まで前記亀裂の発生が認められず、優れた耐久信頼性を備えていることが明らかである。   From FIG. 5, the semiconductor device 10 (comparative example) begins to generate the cracks in the vicinity of 100 cycles, whereas the semiconductor device 1 (example) does not show the generation of cracks in the vicinity of 1500 cycles and has excellent durability. It is clear that it has reliability.

１…半導体装置、 ３…第１の金属板、 ３ｃ…角部、 ４…第２の金属板、 ４ｃ…角部、 ５…絶縁基板、 ６…第１のハンダ層、 ７…半導体素子、 ８…第２のハンダ層、 ９…放熱用金属板。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 3 ... 1st metal plate, 3c ... Corner | angular part, 4 ... 2nd metal plate, 4c ... Corner | angular part, 5 ... Insulating substrate, 6 ... 1st solder layer, 7 ... Semiconductor element, 8 2nd solder layer 9 ... Metal plate for heat dissipation.

Claims (3)

表裏両面に金属板を備える絶縁基板と、
該絶縁基板の第１の金属板上に第１のハンダ層を介して接合されている半導体素子と、
該絶縁基板の第２の金属板上に第２のハンダ層を介して接合されている放熱用金属板とを備え、
該絶縁基板に備えられる各金属板は互いに平行な２組の辺と、相隣り合う２辺を接続する角部とからなる矩形状を備え、第２の金属板は第１の金属板より大面積であり、
第１の金属板と第２の金属板とは該絶縁基板を介して各辺が平行となるように積層されている半導体装置であって、
第１の金属板の各角部の少なくとも一部が第２の金属板の各角部と重なるように積層されていることを特徴とする半導体装置。 An insulating substrate with metal plates on both front and back surfaces;
A semiconductor element bonded to the first metal plate of the insulating substrate via a first solder layer;
A heat dissipating metal plate joined via a second solder layer on the second metal plate of the insulating substrate,
Each metal plate provided on the insulating substrate has a rectangular shape including two sets of sides parallel to each other and corners connecting two adjacent sides, and the second metal plate is larger than the first metal plate. Area,
The first metal plate and the second metal plate are semiconductor devices stacked so that each side is parallel through the insulating substrate,
A semiconductor device, wherein at least a part of each corner of the first metal plate is stacked so as to overlap each corner of the second metal plate. 前記絶縁基板は、セラミックス基板の表裏両面に前記金属板を備えることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the insulating substrate includes the metal plate on both front and back surfaces of a ceramic substrate. 前記絶縁基板は、Ｓｉ３Ｎ４、ＡｌＮ、Ａｌ２Ｏ３からなる群から選択される１種のセラミックスからなる前記セラミックス基板の表裏両面に、ＣｕまたはＡｌのいずれか１種の金属からなる前記金属板を備えることを特徴とする請求項２記載の半導体装置。 The insulating substrate is made of any one metal of Cu or Al on both front and back surfaces of the ceramic substrate made of one kind of ceramic selected from the group consisting of Si 3 N 4 , AlN, and Al 2 O 3. The semiconductor device according to claim 2, further comprising a metal plate.
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Publication number Priority date Publication date Assignee Title
CN102856272A (en) * 2011-06-27 2013-01-02 北京兆阳能源技术有限公司 Insulating and radiating electronic subassembly
JP2013258334A (en) * 2012-06-13 2013-12-26 Denso Corp Semiconductor device and manufacturing method of the same
CN104733404A (en) * 2013-12-19 2015-06-24 株式会社东芝 Semiconductor device
JP2020533797A (en) * 2017-09-12 2020-11-19 ロジャーズ ジャーマニー ゲーエムベーハーＲｏｇｅｒｓ Ｇｅｒｍａｎｙ ＧｍｂＨ Adapter elements for joining components such as laser diodes to heat sinks, systems including laser diodes, heat sinks and adapter elements, and methods of manufacturing adapter elements.
JP7034266B2 (en) 2017-09-12 2022-03-11 ロジャーズ ジャーマニー ゲーエムベーハー Adapter elements for joining components such as laser diodes to heat sinks, systems including laser diodes, heat sinks and adapter elements, and methods of manufacturing adapter elements.
DE102020134951A1 (en) 2020-02-07 2021-08-12 Fuji Electric Co., Ltd. SEMI-CONDUCTOR DEVICE
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JP7529038B2 (en) 2020-11-16 2024-08-06 富士電機株式会社 Semiconductor device and method for manufacturing the same

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