JP2004536515A5 - - Google Patents

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Publication number
JP2004536515A5
JP2004536515A5 JP2003514417A JP2003514417A JP2004536515A5 JP 2004536515 A5 JP2004536515 A5 JP 2004536515A5 JP 2003514417 A JP2003514417 A JP 2003514417A JP 2003514417 A JP2003514417 A JP 2003514417A JP 2004536515 A5 JP2004536515 A5 JP 2004536515A5
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JP
Japan
Prior art keywords
memory
access operation
port
memory access
switch fabric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003514417A
Other languages
English (en)
Japanese (ja)
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JP2004536515A (ja
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Publication date
Application filed filed Critical
Priority claimed from PCT/US2002/020288 external-priority patent/WO2003009142A1/en
Publication of JP2004536515A publication Critical patent/JP2004536515A/ja
Publication of JP2004536515A5 publication Critical patent/JP2004536515A5/ja
Pending legal-status Critical Current

Links

JP2003514417A 2001-07-17 2002-06-26 デュアルポートメモリエミュレーション方式によるスイッチファブリック Pending JP2004536515A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30617401P 2001-07-17 2001-07-17
PCT/US2002/020288 WO2003009142A1 (en) 2001-07-17 2002-06-26 Switch fabric with dual port memory emulation scheme

Publications (2)

Publication Number Publication Date
JP2004536515A JP2004536515A (ja) 2004-12-02
JP2004536515A5 true JP2004536515A5 (https=) 2006-01-05

Family

ID=23184152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003514417A Pending JP2004536515A (ja) 2001-07-17 2002-06-26 デュアルポートメモリエミュレーション方式によるスイッチファブリック

Country Status (5)

Country Link
US (1) US20030016689A1 (https=)
EP (1) EP1407362A4 (https=)
JP (1) JP2004536515A (https=)
CN (1) CN1545658A (https=)
WO (1) WO2003009142A1 (https=)

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US7289523B2 (en) * 2001-09-13 2007-10-30 International Business Machines Corporation Data packet switch and method of operating same
US7292593B1 (en) * 2002-03-28 2007-11-06 Advanced Micro Devices, Inc. Arrangement in a channel adapter for segregating transmit packet data in transmit buffers based on respective virtual lanes
US7239645B2 (en) * 2003-01-21 2007-07-03 Applied Micro Circuits Corporation Method and apparatus for managing payload buffer segments in a networking device
US7515584B2 (en) * 2003-09-19 2009-04-07 Infineon Technologies Ag Switching data packets in an ethernet switch
US8370557B2 (en) * 2008-12-19 2013-02-05 Intel Corporation Pseudo dual-port SRAM and a shared memory switch using multiple memory banks and a sideband memory
CN102081591A (zh) * 2011-01-27 2011-06-01 中国第一汽车集团公司 双端口存储器在双cpu结构设计中的应用
CN103594110B (zh) * 2012-08-15 2017-09-15 上海华虹集成电路有限责任公司 替代双端口静态存储器的存储器结构
CN103677971B (zh) * 2012-09-21 2017-11-24 上海斐讯数据通信技术有限公司 多线程处理系统及方法
US10847213B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Write data processing circuits and methods associated with computational memory cells
US10777262B1 (en) 2016-12-06 2020-09-15 Gsi Technology, Inc. Read data processing circuits and methods associated memory cells
US10998040B2 (en) 2016-12-06 2021-05-04 Gsi Technology, Inc. Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
US10854284B1 (en) 2016-12-06 2020-12-01 Gsi Technology, Inc. Computational memory cell and processing array device with ratioless write port
US10891076B1 (en) 2016-12-06 2021-01-12 Gsi Technology, Inc. Results processing circuits and methods associated with computational memory cells
US10943648B1 (en) 2016-12-06 2021-03-09 Gsi Technology, Inc. Ultra low VDD memory cell with ratioless write port
US11227653B1 (en) 2016-12-06 2022-01-18 Gsi Technology, Inc. Storage array circuits and methods for computational memory cells
US10770133B1 (en) 2016-12-06 2020-09-08 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits
US10860318B2 (en) 2016-12-06 2020-12-08 Gsi Technology, Inc. Computational memory cell and processing array device using memory cells
US10847212B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers
US10860320B1 (en) * 2016-12-06 2020-12-08 Gsi Technology, Inc. Orthogonal data transposition system and method during data transfers to/from a processing array
US10877731B1 (en) 2019-06-18 2020-12-29 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
US10958272B2 (en) 2019-06-18 2021-03-23 Gsi Technology, Inc. Computational memory cell and processing array device using complementary exclusive or memory cells
US10930341B1 (en) 2019-06-18 2021-02-23 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
CN111679599B (zh) * 2020-05-22 2022-01-25 中国航空工业集团公司西安航空计算技术研究所 一种cpu与dsp数据高可靠交换方法

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