JP2004523879A - システム・オン・ア・チップのフィールド・プログラマブル・ゲート・アレイとマイクロコントローラ - Google Patents

システム・オン・ア・チップのフィールド・プログラマブル・ゲート・アレイとマイクロコントローラ Download PDF

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JP2004523879A
JP2004523879A JP2002525997A JP2002525997A JP2004523879A JP 2004523879 A JP2004523879 A JP 2004523879A JP 2002525997 A JP2002525997 A JP 2002525997A JP 2002525997 A JP2002525997 A JP 2002525997A JP 2004523879 A JP2004523879 A JP 2004523879A
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JP2004523879A5 (enExample
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アルナングシュ・クンドゥ
アーノルド・ゴールドフェイン
ウィリアム・シー・プランツ
デイヴィット・ハイタワー
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アクテル・コーポレイシヨン
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

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  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Microcomputers (AREA)
JP2002525997A 2000-09-02 2001-08-31 システム・オン・ア・チップのフィールド・プログラマブル・ゲート・アレイとマイクロコントローラ Pending JP2004523879A (ja)

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US09/654,237 US6751723B1 (en) 2000-09-02 2000-09-02 Field programmable gate array and microcontroller system-on-a-chip
PCT/US2001/027130 WO2002021693A2 (en) 2000-09-02 2001-08-31 Field programmable gate array and microcontroller system-on-a-chip

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JP2004523879A true JP2004523879A (ja) 2004-08-05
JP2004523879A5 JP2004523879A5 (enExample) 2011-11-24

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US (4) US6751723B1 (enExample)
EP (1) EP1382117B9 (enExample)
JP (1) JP2004523879A (enExample)
AU (1) AU2001286967A1 (enExample)
WO (1) WO2002021693A2 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010506293A (ja) * 2006-10-03 2010-02-25 アルカテル−ルーセント ユーエスエー インコーポレーテッド Icアーキテクチャを再構成するための方法および装置
US7886130B2 (en) 2000-09-02 2011-02-08 Actel Corporation Field programmable gate array and microcontroller system-on-a-chip

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6150837A (en) * 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US20020066088A1 (en) * 2000-07-03 2002-05-30 Cadence Design Systems, Inc. System and method for software code optimization
AU2001289045A1 (en) * 2000-09-08 2002-03-22 Avaz Networks Hardware function generator support in a dsp
US6880070B2 (en) * 2000-12-08 2005-04-12 Finisar Corporation Synchronous network traffic processor
US7962716B2 (en) 2001-03-22 2011-06-14 Qst Holdings, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7400668B2 (en) 2001-03-22 2008-07-15 Qst Holdings, Llc Method and system for implementing a system acquisition function for use with a communication device
US6836839B2 (en) 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7752419B1 (en) 2001-03-22 2010-07-06 Qst Holdings, Llc Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US6577678B2 (en) 2001-05-08 2003-06-10 Quicksilver Technology Method and system for reconfigurable channel coding
US6986021B2 (en) * 2001-11-30 2006-01-10 Quick Silver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US8412915B2 (en) 2001-11-30 2013-04-02 Altera Corporation Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
US20030112758A1 (en) * 2001-12-03 2003-06-19 Pang Jon Laurent Methods and systems for managing variable delays in packet transmission
US20030105799A1 (en) * 2001-12-03 2003-06-05 Avaz Networks, Inc. Distributed processing architecture with scalable processing layers
US7602740B2 (en) 2001-12-10 2009-10-13 Qst Holdings, Inc. System for adapting device standards after manufacture
US7215701B2 (en) 2001-12-12 2007-05-08 Sharad Sambhwani Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
US20030108012A1 (en) * 2001-12-12 2003-06-12 Quicksilver Technology, Inc. Method and system for detecting and identifying scrambling codes
US7403981B2 (en) * 2002-01-04 2008-07-22 Quicksilver Technology, Inc. Apparatus and method for adaptive multimedia reception and transmission in communication environments
JP3510618B2 (ja) * 2002-02-05 2004-03-29 沖電気工業株式会社 バスブリッジ回路及びそのアクセス制御方法
US6941538B2 (en) * 2002-02-22 2005-09-06 Xilinx, Inc. Method and system for integrating cores in FPGA-based system-on-chip (SoC)
US7577540B2 (en) * 2002-03-01 2009-08-18 Nec Corporation Re-configurable embedded core test protocol for system-on-chips (SOC) and circuit boards
US7493375B2 (en) 2002-04-29 2009-02-17 Qst Holding, Llc Storage and delivery of device features
US7328414B1 (en) 2003-05-13 2008-02-05 Qst Holdings, Llc Method and system for creating and programming an adaptive computing engine
US7660984B1 (en) 2003-05-13 2010-02-09 Quicksilver Technology Method and system for achieving individualized protected space in an operating system
US20030217306A1 (en) * 2002-05-17 2003-11-20 Harthcock Jerry D. Self-programmable microcomputer and method of remotely programming same
US8108656B2 (en) 2002-08-29 2012-01-31 Qst Holdings, Llc Task definition for specifying resource requirements
US7269814B1 (en) * 2002-10-08 2007-09-11 Actel Corporation Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA
US7937591B1 (en) 2002-10-25 2011-05-03 Qst Holdings, Llc Method and system for providing a device which can be adapted on an ongoing basis
US8949576B2 (en) * 2002-11-01 2015-02-03 Nvidia Corporation Arithmetic node including general digital signal processing functions for an adaptive computing machine
US8276135B2 (en) * 2002-11-07 2012-09-25 Qst Holdings Llc Profiling of software and circuit designs utilizing data operation analyses
US7225301B2 (en) 2002-11-22 2007-05-29 Quicksilver Technologies External memory controller node
US6946871B1 (en) * 2002-12-18 2005-09-20 Actel Corporation Multi-level routing architecture in a field programmable gate array having transmitters and receivers
US6800884B1 (en) * 2002-12-30 2004-10-05 Actel Corporation Inter-tile buffer system for a field programmable gate array
US7199609B1 (en) * 2003-05-30 2007-04-03 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US6867615B1 (en) * 2003-05-30 2005-03-15 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US7385419B1 (en) * 2003-05-30 2008-06-10 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US7609297B2 (en) 2003-06-25 2009-10-27 Qst Holdings, Inc. Configurable hardware based digital imaging apparatus
US20050102573A1 (en) * 2003-11-03 2005-05-12 Macronix International Co., Ltd. In-circuit configuration architecture for embedded configurable logic array
US20050097499A1 (en) * 2003-11-03 2005-05-05 Macronix International Co., Ltd. In-circuit configuration architecture with non-volatile configuration store for embedded configurable logic array
US20050093572A1 (en) * 2003-11-03 2005-05-05 Macronix International Co., Ltd. In-circuit configuration architecture with configuration on initialization function for embedded configurable logic array
US7106098B1 (en) * 2004-05-04 2006-09-12 Xilinx, Inc. Split FIFO configuration of block RAM
US7313730B1 (en) * 2004-05-20 2007-12-25 Xilinx, Inc. Configuration logic for embedded software
US7299339B2 (en) * 2004-08-30 2007-11-20 The Boeing Company Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework
US7676661B1 (en) 2004-10-05 2010-03-09 Xilinx, Inc. Method and system for function acceleration using custom instructions
US7346739B1 (en) 2004-11-19 2008-03-18 Xilinx, Inc. First-in-first-out memory system and method for providing same
US7664891B2 (en) * 2004-12-06 2010-02-16 Stmicroelectronics Inc. Modular data transfer architecture
US7635987B1 (en) * 2004-12-13 2009-12-22 Massachusetts Institute Of Technology Configuring circuitry in a parallel processing environment
CA2593247A1 (en) * 2005-01-10 2006-11-16 Quartics, Inc. Integrated architecture for the unified processing of visual media
US20070283311A1 (en) * 2006-05-30 2007-12-06 Theodore Karoubalis Method and system for dynamic reconfiguration of field programmable gate arrays
US20080182021A1 (en) * 2007-01-31 2008-07-31 Simka Harsono S Continuous ultra-thin copper film formed using a low thermal budget
GB0706134D0 (en) * 2007-03-29 2007-05-09 Nokia Oyj A modular device component
US7761632B2 (en) 2007-04-27 2010-07-20 Atmel Corporation Serialization of data for communication with slave in multi-chip bus implementation
US7769933B2 (en) * 2007-04-27 2010-08-03 Atmel Corporation Serialization of data for communication with master in multi-chip bus implementation
US7814250B2 (en) * 2007-04-27 2010-10-12 Atmel Corporation Serialization of data for multi-chip bus implementation
US7743186B2 (en) * 2007-04-27 2010-06-22 Atmel Corporation Serialization of data for communication with different-protocol slave in multi-chip bus implementation
EP2255440A1 (en) * 2008-03-16 2010-12-01 Nxp B.V. Methods, circuits, systems and arrangements for undriven or driven pins
US8276105B2 (en) * 2009-09-18 2012-09-25 International Business Machines Corporation Automatic positioning of gate array circuits in an integrated circuit design
US8365024B2 (en) * 2010-02-26 2013-01-29 Honeywell International Inc. High integrity data bus fault detection using multiple signal components
US8054208B2 (en) 2010-03-30 2011-11-08 Honeywell International Inc. Re-configurable multipurpose analog interface
US8782299B2 (en) 2010-04-27 2014-07-15 Honeywell International Inc. Re-configurable multi-purpose digital interface
US9537488B1 (en) * 2010-05-13 2017-01-03 Altera Corporation Apparatus for configurable interface and associated methods
US9780789B2 (en) * 2010-05-13 2017-10-03 Altera Corporation Apparatus for automatically configured interface and associated methods
US8390324B2 (en) 2010-09-20 2013-03-05 Honeywell International Inc. Universal functionality module
US8467218B1 (en) 2010-12-13 2013-06-18 Altera Corporation System and apparatus with IC resource interconnect
CN102637157B (zh) * 2011-02-15 2014-12-03 郑磊 一种片上数字模板系统dtsoc
US20120284501A1 (en) 2011-05-06 2012-11-08 Xcelemor, Inc. Computing system with hardware reconfiguration mechanism and method of operation thereof
US8868820B2 (en) * 2011-10-31 2014-10-21 Microsemi SoC Corporation RAM block designed for efficient ganging
US8854079B2 (en) * 2013-01-30 2014-10-07 Texas Instruments Incorporated Error detection in nonvolatile logic arrays using parity
US20140282390A1 (en) * 2013-03-15 2014-09-18 Nvidia Corporation System, method, and computer program product for creating a compute construct
US9323502B2 (en) 2013-03-15 2016-04-26 Nvidia Corporation System, method, and computer program product for altering a line of code
DE102014012660A1 (de) * 2013-12-11 2015-06-11 Diehl Aerospace Gmbh Konfigurierbare Schnittstellenschaltung
CN103731133A (zh) * 2014-01-20 2014-04-16 四川九洲电器集团有限责任公司 基于fpga的旋转变压器输出装置及方法
US9153531B1 (en) 2014-02-27 2015-10-06 Altera Corporation Methods and apparatus for reducing crosstalk and twist region height in routing wires
US9721528B2 (en) * 2014-11-10 2017-08-01 Xilinx, Inc. Processing system display controller interface to programmable logic
US9564394B1 (en) 2014-11-18 2017-02-07 Altera Corporation Methods and apparatus for reducing spatial overlap between routing wires
US10432196B2 (en) 2015-07-22 2019-10-01 Nuvoton Technology Corporation Communication device, communication system and operation method thereof
TWI561007B (en) 2015-07-22 2016-12-01 Nuvoton Technology Corp Function programmable circuit and operation method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002511173A (ja) * 1997-06-27 2002-04-09 カメレオン・システムズ・インコーポレーテッド 再構成可能なコンピューティングのための、集積化されたプロセッサとプログラム可能なデータ・パス・チップ

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6096978A (ja) * 1983-10-31 1985-05-30 Clarion Co Ltd 有料テレビジヨンシステム
US4870302A (en) 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
DE3513169A1 (de) 1985-04-12 1986-10-16 Hopstabil Hopfenverarbeitungs-Gesellschaft mbH, 8069 Wolnzach Verfahren zur herstellung von isohumulonen
US4758745B1 (en) 1986-09-19 1994-11-15 Actel Corp User programmable integrated circuit interconnect architecture and test method
US5162988A (en) * 1986-10-31 1992-11-10 Ncr Corporation Multiplexing character processor
US5333198A (en) * 1993-05-27 1994-07-26 Houlberg Christian L Digital interface circuit
US5355162A (en) * 1993-07-13 1994-10-11 Pacific Ray Video Limited Multi-standard cable television system
US5625651A (en) * 1994-06-02 1997-04-29 Amati Communications, Inc. Discrete multi-tone data transmission system using an overhead bus for synchronizing multiple remote units
US6052773A (en) * 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5854752A (en) 1996-01-19 1998-12-29 Ikos Systems, Inc. Circuit partitioning technique for use with multiplexed inter-connections
US5784636A (en) * 1996-05-28 1998-07-21 National Semiconductor Corporation Reconfigurable computer architecture for use in signal processing applications
US5896414A (en) * 1996-09-17 1999-04-20 Sarnoff Corporation Method and apparatus for providing control channel communications for an information distribution system
US5834947A (en) 1996-11-01 1998-11-10 Waferscale Integration Inc. Microcontroller accessible macrocell
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US6188381B1 (en) * 1997-09-08 2001-02-13 Sarnoff Corporation Modular parallel-pipelined vision system for real-time video processing
US5915123A (en) * 1997-10-31 1999-06-22 Silicon Spice Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
DE19819505A1 (de) 1998-04-30 1999-11-04 Alcatel Sa Integrierte Schaltung
US6226735B1 (en) * 1998-05-08 2001-05-01 Broadcom Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements
US6467009B1 (en) 1998-10-14 2002-10-15 Triscend Corporation Configurable processor system unit
US7129860B2 (en) * 1999-01-29 2006-10-31 Quickshift, Inc. System and method for performing scalable embedded parallel data decompression
US6751723B1 (en) 2000-09-02 2004-06-15 Actel Corporation Field programmable gate array and microcontroller system-on-a-chip
GB2373595B (en) * 2001-03-15 2005-09-07 Italtel Spa A system of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol
EP1579716B1 (en) * 2002-12-17 2014-09-03 Girish P. Saraph Routing scheme based on virtual space representation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002511173A (ja) * 1997-06-27 2002-04-09 カメレオン・システムズ・インコーポレーテッド 再構成可能なコンピューティングのための、集積化されたプロセッサとプログラム可能なデータ・パス・チップ

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7886130B2 (en) 2000-09-02 2011-02-08 Actel Corporation Field programmable gate array and microcontroller system-on-a-chip
JP2010506293A (ja) * 2006-10-03 2010-02-25 アルカテル−ルーセント ユーエスエー インコーポレーテッド Icアーキテクチャを再構成するための方法および装置
KR101133800B1 (ko) 2006-10-03 2012-04-05 알카텔-루센트 유에스에이 인코포레이티드 Ic 아키텍처 재구성 방법, 아키텍처를 포함하는 시스템 및 이를 포함하는 네트워크

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WO2002021693A8 (en) 2002-06-20
US7886130B2 (en) 2011-02-08
US7069419B2 (en) 2006-06-27
WO2002021693A2 (en) 2002-03-14
AU2001286967A1 (en) 2002-03-22
EP1382117B9 (en) 2012-09-05
US20090106531A1 (en) 2009-04-23
WO2002021693A3 (en) 2003-10-23
US20050257031A1 (en) 2005-11-17
US7516303B2 (en) 2009-04-07
EP1382117A2 (en) 2004-01-21
US20040232942A1 (en) 2004-11-25
EP1382117B1 (en) 2012-06-20
US6751723B1 (en) 2004-06-15

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