JP2004523132A - イオン打ち込みによってサイドウォールの密度を局所的に高くする方法 - Google Patents

イオン打ち込みによってサイドウォールの密度を局所的に高くする方法 Download PDF

Info

Publication number
JP2004523132A
JP2004523132A JP2003513034A JP2003513034A JP2004523132A JP 2004523132 A JP2004523132 A JP 2004523132A JP 2003513034 A JP2003513034 A JP 2003513034A JP 2003513034 A JP2003513034 A JP 2003513034A JP 2004523132 A JP2004523132 A JP 2004523132A
Authority
JP
Japan
Prior art keywords
insulating layer
copper
forming
opening
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003513034A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004523132A5 (https=
Inventor
エム． アペルグレン エリック
ジルト クリスチャン
アイ． マーティン ジェレミー
アール． ベセル ポール
チューン フレッド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2004523132A publication Critical patent/JP2004523132A/ja
Publication of JP2004523132A5 publication Critical patent/JP2004523132A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/095—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by irradiating with electromagnetic or particle radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/40—Ion implantation into wafers, substrates or parts of devices into insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/086—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving buried masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/097—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by thermally treating

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2003513034A 2001-07-10 2002-06-12 イオン打ち込みによってサイドウォールの密度を局所的に高くする方法 Pending JP2004523132A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/902,024 US6610594B2 (en) 2001-07-10 2001-07-10 Locally increasing sidewall density by ion implantation
PCT/US2002/018842 WO2003007367A1 (en) 2001-07-10 2002-06-12 Locally increasing sidewall density by ion implantation

Publications (2)

Publication Number Publication Date
JP2004523132A true JP2004523132A (ja) 2004-07-29
JP2004523132A5 JP2004523132A5 (https=) 2006-01-19

Family

ID=25415200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003513034A Pending JP2004523132A (ja) 2001-07-10 2002-06-12 イオン打ち込みによってサイドウォールの密度を局所的に高くする方法

Country Status (7)

Country Link
US (1) US6610594B2 (https=)
EP (1) EP1405339A1 (https=)
JP (1) JP2004523132A (https=)
KR (1) KR100860133B1 (https=)
CN (1) CN1316589C (https=)
TW (1) TW573341B (https=)
WO (1) WO2003007367A1 (https=)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7049034B2 (en) * 2003-09-09 2006-05-23 Photronics, Inc. Photomask having an internal substantially transparent etch stop layer
TWI253684B (en) * 2003-06-02 2006-04-21 Tokyo Electron Ltd Method and system for using ion implantation for treating a low-k dielectric film
TWI302720B (en) * 2003-07-23 2008-11-01 Tokyo Electron Ltd Method for using ion implantation to treat the sidewalls of a feature in a low-k dielectric film
US20060051681A1 (en) * 2004-09-08 2006-03-09 Phototronics, Inc. 15 Secor Road P.O. Box 5226 Brookfield, Conecticut Method of repairing a photomask having an internal etch stop layer
KR100613346B1 (ko) * 2004-12-15 2006-08-21 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
EP1715517A1 (en) * 2005-04-22 2006-10-25 AMI Semiconductor Belgium BVBA Ion implantation of spin on glass materials
US7482267B2 (en) * 2005-04-22 2009-01-27 Ami Semiconductor Belgium Bvba Ion implantation of spin on glass materials
CN100499069C (zh) * 2006-01-13 2009-06-10 中芯国际集成电路制造(上海)有限公司 使用所选掩模的双大马士革铜工艺
US20100109155A1 (en) * 2008-11-05 2010-05-06 Chartered Semiconductor Manufacturing, Ltd. Reliable interconnect integration
FR2969375A1 (fr) 2010-12-17 2012-06-22 St Microelectronics Crolles 2 Structure d'interconnexion pour circuit intégré
KR101932532B1 (ko) 2012-06-22 2018-12-27 삼성전자 주식회사 반도체 장치 및 그 제조 방법
TWI509689B (zh) * 2013-02-06 2015-11-21 國立中央大學 介電質材料形成平台側壁的半導體製造方法及其半導體元件
US9231098B2 (en) 2013-10-30 2016-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanism for forming metal gate structure
CN105336666B (zh) * 2014-06-19 2019-06-18 中芯国际集成电路制造(上海)有限公司 基于金属硬掩膜的超低k互连的制造方法及制造的产品
US11270962B2 (en) * 2019-10-28 2022-03-08 Nanya Technology Corporation Semiconductor device and method of manufacturing the same
US11488857B2 (en) 2019-10-31 2022-11-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture using a contact etch stop layer (CESL) breakthrough process
CN112750761A (zh) 2019-10-31 2021-05-04 台湾积体电路制造股份有限公司 半导体装置及其制造方法
US11257753B2 (en) * 2020-01-21 2022-02-22 Taiwan Semiconductor Manufacturing Company Ltd. Interconnect structure and method for manufacturing the interconnect structure
US11776895B2 (en) * 2021-05-06 2023-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method for manufacturing the same
US12469745B2 (en) * 2021-07-30 2025-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive structures with bottom-less barriers and liners

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0969562A (ja) * 1994-09-14 1997-03-11 Sanyo Electric Co Ltd 半導体装置の製造方法および半導体装置
JPH09306915A (ja) * 1996-05-17 1997-11-28 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP2000164707A (ja) * 1998-11-27 2000-06-16 Sony Corp 半導体装置およびその製造方法
US6114259A (en) * 1999-07-27 2000-09-05 Lsi Logic Corporation Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage
US6225204B1 (en) * 1998-07-28 2001-05-01 United Microelectronics Corp. Method for preventing poisoned vias and trenches

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
US6197688B1 (en) * 1998-02-12 2001-03-06 Motorola Inc. Interconnect structure in a semiconductor device and method of formation
KR100279300B1 (ko) * 1998-05-11 2001-02-01 윤종용 금속 배선 연결 방법
US6221780B1 (en) 1999-09-29 2001-04-24 International Business Machines Corporation Dual damascene flowable oxide insulation structure and metallic barrier
JP3863331B2 (ja) 1999-12-24 2006-12-27 株式会社リコー 光学的情報記録再生方法及び光学的情報記録再生装置
US6355555B1 (en) * 2000-01-28 2002-03-12 Advanced Micro Devices, Inc. Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer
JP2001267418A (ja) 2000-03-21 2001-09-28 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US6444136B1 (en) * 2000-04-25 2002-09-03 Newport Fab, Llc Fabrication of improved low-k dielectric structures
US6329234B1 (en) * 2000-07-24 2001-12-11 Taiwan Semiconductor Manufactuirng Company Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0969562A (ja) * 1994-09-14 1997-03-11 Sanyo Electric Co Ltd 半導体装置の製造方法および半導体装置
JPH09306915A (ja) * 1996-05-17 1997-11-28 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US6225204B1 (en) * 1998-07-28 2001-05-01 United Microelectronics Corp. Method for preventing poisoned vias and trenches
JP2000164707A (ja) * 1998-11-27 2000-06-16 Sony Corp 半導体装置およびその製造方法
US6114259A (en) * 1999-07-27 2000-09-05 Lsi Logic Corporation Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage

Also Published As

Publication number Publication date
WO2003007367A1 (en) 2003-01-23
US20030013296A1 (en) 2003-01-16
CN1316589C (zh) 2007-05-16
KR20040015789A (ko) 2004-02-19
KR100860133B1 (ko) 2008-09-25
US6610594B2 (en) 2003-08-26
CN1579017A (zh) 2005-02-09
EP1405339A1 (en) 2004-04-07
TW573341B (en) 2004-01-21

Similar Documents

Publication Publication Date Title
US6355555B1 (en) Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer
US6303486B1 (en) Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer and an unconstrained copper anneal
US6368967B1 (en) Method to control mechanical stress of copper interconnect line using post-plating copper anneal
US6261963B1 (en) Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices
US7132363B2 (en) Stabilizing fluorine etching of low-k materials
US20010051420A1 (en) Dielectric formation to seal porosity of low dielectic constant (low k) materials after etch
US6972254B1 (en) Manufacturing a conformal atomic liner layer in an integrated circuit interconnect
US8178437B2 (en) Barrier material and process for Cu interconnect
US6958291B2 (en) Interconnect with composite barrier layers and method for fabricating the same
JP2004523132A (ja) イオン打ち込みによってサイドウォールの密度を局所的に高くする方法
US7514354B2 (en) Methods for forming damascene wiring structures having line and plug conductors formed from different materials
US8119519B2 (en) Semiconductor device manufacturing method
US6426558B1 (en) Metallurgy for semiconductor devices
US6498112B1 (en) Graded oxide caps on low dielectric constant (low K) chemical vapor deposition (CVD) films
CN100378953C (zh) 在层间介质互连中形成低电阻和可靠过孔的方法
US6514844B1 (en) Sidewall treatment for low dielectric constant (low K) materials by ion implantation
CN1601742A (zh) 金属联机结构及其制造方法
US6881665B1 (en) Depth of focus (DOF) for trench-first-via-last (TFVL) damascene processing with hard mask and low viscosity photoresist
US6649511B1 (en) Method of manufacturing a seed layer with annealed region for integrated circuit interconnects
KR100386628B1 (ko) 반도체 소자의 금속 배선 형성방법
KR20020052566A (ko) 반도체장치의 배선 및 배선연결부 제조방법

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050524

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051124

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081125

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20090223

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20090302

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20090325

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20090401

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20090424

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20090507

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090525

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090811

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20091109

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20091116

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20091210

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20091217

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20100112

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20100202

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100212

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100330

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20100421

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100730

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20100902

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20100916

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20101112