JP2004349604A - Thin film transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor of a GOLD structure which can be manufactured by a simple self-alignment process, and its manufacturing method. <P>SOLUTION: A semiconductor film 12 has a channel region 12a, a first impurity implantation region 12b provided adjacent to both sides of the channel region 12a and a second impurity implantation region 12c which is provided adjacent to the first impurity implantation region 12b and whereto impurity of higher concentration than the first impurity implantation region 12b is implanted. A gate electrode 14 has a conductive film 14a formed on a gate insulating film 13 in opposition to the channel region 12a and a conductive oxide film 14b which is formed to cover the surface of the conductive film 14a and faces the first impurity implantation region 12b. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, to a thin film transistor having a GOLD (Gate Overlapped Lightly Doped Drain) structure and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in order to realize high reliability of a thin film transistor (hereinafter, also referred to as a TFT) element, an LDD (Lightly doped) in which an LDD region doped with a low concentration impurity is provided between a channel region and a source / drain region of the TFT. Drain) structure was mainstream. However, in the TFT having the LDD structure, the current flowing through the channel is limited by the resistance of the LDD portion, so that there is a disadvantage that the ON current decreases. Therefore, a GOLD structure TFT in which a gate electrode is overlapped with an upper part of an LDD region is attracting attention as a device structure that achieves both reliability and initial characteristics. In a TFT having a GOLD structure, when the channel portion is completely ON, Si in the GOLD region also forms an inversion layer and does not act as a resistor, so that a good ON current and high reliability can be secured at the same time.
[0003]
In addition, as a gate electrode material used for a TFT element, in addition to low resistance, reliability against chemicals such as acids and alkalis, migration reliability, and ease of processing by etching and the like are required. It has been difficult to select a material that satisfies all of these conditions.
Conventionally, it has been difficult to form a GOLD structure by a self-aligned process, so that the GOLD structure has been formed by repeating a photolithography process a plurality of times at the expense of pattern accuracy.
[0004]
Patent Document 1 discloses a method of manufacturing a thin film transistor having a GOLD structure, in which an LDD region is formed by injecting impurities into a semiconductor film using a resist pattern as a mask, and then a gate electrode overlapping the LDD region is formed. A method of forming source / drain regions by implanting impurities using a gate electrode as a mask is disclosed.
[0005]
Further, Patent Document 2 has a semiconductor layer on an insulating substrate, a gate insulating film on the semiconductor layer, and a gate electrode having a sidewall made of a conductive film on the gate insulating film. A thin film transistor is disclosed in which a semiconductor layer overlapping with a sidewall includes an N-type impurity at a lower concentration than an N-type impurity in a source region and a drain region.
[0006]
In Patent Document 3, the gate electrode is composed of a first-layer gate electrode and a second-layer gate electrode, and the first-layer gate electrode is formed to be longer in the channel direction than the second-layer gate electrode. A first impurity region is formed in a semiconductor layer corresponding to the exposed region of the first layer gate electrode, and a second impurity region and a third impurity region are formed in a semiconductor layer corresponding to the outside of the gate electrode from a side closer to the gate electrode. A thin film transistor in which the first impurity region is formed adjacent to the second impurity region, the impurity concentration of the first impurity region is higher than the impurity concentration of the second impurity region, and lower than the impurity concentration of the third impurity region. I have.
[0007]
Further, Patent Document 4 discloses a thin film transistor having a GOLD structure in which a metal film is deposited on a side surface and an upper surface of a gate wiring by an electrolytic plating method, and the metal film is overlapped with an LDD region via a gate insulating film.
[0008]
[Patent Document 1]
JP-A-2002-134756
[Patent Document 2]
JP 2001-203366 A
[Patent Document 3]
JP-A-2002-190479
[Patent Document 4]
JP 2001-210833 A
[0009]
[Problems to be solved by the invention]
However, the method disclosed in Patent Literature 1 does not form a GOLD structure by a self-aligned process, but performs the photolithography process twice, which reduces the pattern accuracy and increases the number of photolithography processes. And so on.
[0010]
Further, the method disclosed in Patent Document 2 uses a gate electrode having sidewalls, but is not configured so that an upper gate electrode covers a lower gate electrode. There has been a problem that it is not possible to achieve both low reliability and low reliability with respect to chemicals such as acids and alkalis and migration.
[0011]
In addition, the method disclosed in Patent Document 3 uses backside exposure, and requires a device for backside exposure, and can be manufactured only when a transparent substrate is used. there were. In addition, the etching of the gate electrode is performed by taper etching, and there is a problem that dimensional variations are increased. In addition, although a gate electrode having a two-layer structure is used, the gate electrode material of the lower layer is not covered with the gate electrode material of the upper layer. There is a problem that it is not possible to achieve both low reliability and low resistance.
[0012]
In addition, the method using electrolytic plating disclosed in Patent Document 4 has a problem that it is difficult to form a metal film on a metal surface on which a natural oxide film is easily formed on the surface. Metal materials (Al, Cr, Mo, Ti, etc.) frequently used for wiring of semiconductors and liquid crystal displays easily form a natural oxide film on the surface thereof, so that electrolytic plating on these metal surfaces is difficult. It has not been widely used industrially. In addition, the electrolytic plating method has a problem that it is difficult to form a metal film having acid resistance and alkali resistance because a metal dissolved in acid or alkali is precipitated.
[0013]
The present invention has been made to solve the above problems, and has as its object to provide a GOLD structure thin film transistor that can be manufactured by a simple self-alignment process, and a method of manufacturing the same.
[0014]
[Means for Solving the Problems]
A thin film transistor according to the present invention includes: a substrate having a surface made of an insulating material; a channel region formed on the substrate; a first impurity implantation region provided adjacent to both sides of the channel region; A semiconductor film having a second impurity-implanted region provided adjacent to the impurity-implanted region and having a higher impurity concentration implanted than the first impurity-implanted region, and a gate insulating film formed on the substrate and the semiconductor film And a conductive film formed on the gate insulating film so as to face the channel region, and a conductive oxide film formed so as to cover the surface of the conductive film and face the first impurity implantation region. And a source / drain electrode electrically connected to the second impurity-implanted region.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a cross-sectional configuration of a thin film transistor according to Embodiment 1 of the present invention. The structure of the thin film transistor according to the first embodiment will be described with reference to FIG.
[0016]
As shown in FIG. 1, a semiconductor film 12 such as polycrystalline silicon is formed in a predetermined pattern on an insulating substrate 11 such as a glass substrate. The substrate 11 only needs to have a surface made of an insulating material. The pattern of the semiconductor film 12 includes a channel region 12a, a low-concentration impurity implantation region 12b, and a contact region 12c. The channel region 12a is formed at the center of the pattern of the semiconductor film 12, and the contact region 12c is formed at both ends of the pattern of the semiconductor film 12. The low-concentration impurity implantation region 12b is formed between the channel region 12a and the contact region 12c.
SiO 2 is formed on the substrate 11 and the semiconductor film 12. ₂ A gate insulating film 13 is formed. Gate electrode 14 is formed at a predetermined position on gate insulating film 13. The gate electrode 14 includes a first conductive film 14a and a second conductive film 14b formed so as to cover the first conductive film 14a. As the first conductive film 14a, a low-resistance metal film is desirable, and as the second conductive film 14b, a conductive oxide film is desirable. When a metal film is used as the second conductive film 14b, there is a concern that its surface is oxidized in the manufacturing process to increase the resistance, but when a conductive oxide is used, there is no such a problem. It is more desirable in that respect.
The region facing the first conductive film 14a is the channel region 12a, and the region facing the second conductive film 14b is the low-concentration impurity implantation region 12b.
On the gate insulating film 13 on which the gate electrode 14 is formed, an interlayer insulating film 15 is provided. The interlayer insulating film 15 is provided to insulate between the gate electrode 14 and the source electrode 16 and between the gate electrode 14 and the drain electrode 17.
On the interlayer insulating film 15, a source electrode 16 and a drain electrode 17 are provided so as to be connected to the contact region 12c via contact holes opened in the interlayer insulating film 15 and the gate insulating film. On the interlayer insulating film 15 on which the source electrode 16 and the drain electrode 17 are formed, a protective film 18 is provided.
[0017]
In the thus configured thin film transistor of the first embodiment, the gate electrode 14 is constituted by the first conductive film 14a and the second conductive film 14b formed so as to cover the first conductive film 14a. Therefore, by using a low-resistance material as the first conductive film 14a and using a material having excellent chemical resistance and migration resistance as the second conductive film 14b, both low resistance and reliability can be achieved. Also, since the gate electrode 14 overlaps over the entire surface of the low-concentration impurity implantation region 12b, the low-concentration impurity implantation region 12b also becomes an inversion layer when the thin film transistor is turned on, and does not act as a resistor. Good on-current can be obtained.
[0018]
Note that the thin film transistor of Embodiment 1 can be used for various semiconductor devices. For example, the present invention can be used as an active matrix display device in which a thin film transistor is arranged in each of a large number of pixels arranged in a matrix. Further, the present invention can be used for a driving circuit provided around a display device.
[0019]
Next, a method of manufacturing the thin film transistor according to the first embodiment will be described.
2 to 8 are diagrams for explaining a method of manufacturing the thin film transistor according to the first embodiment of the present invention.
[0020]
First, as shown in FIG. 2, a polycrystalline silicon film 42 is formed on an insulating substrate 11 such as glass. In this method, an amorphous silicon film is formed on a substrate 11, and then the amorphous silicon film is crystallized by using a solid phase growth method (SPC), an excimer laser annealing process, or a combination thereof. Thus, a polycrystalline silicon film 42 is obtained.
[0021]
Next, as shown in FIG. 3, after processing the polycrystalline silicon film 42 into a predetermined shape, the formation of the gate insulating film 13 and the formation of the first conductive film 14a constituting the gate electrode 14 are performed. As the gate insulating film 13, for example, about 100 nm of SiO ₂ To form As the first conductive film 14a, a low-resistance metal film such as Al or Mo is used. For example, an Al film having a thickness of 300 nm is used. After forming an Al film of 300 nm, it is processed into a predetermined shape. As shown in FIG. 3, in the TFT portion, the first conductive film 14a is formed substantially at the center of the region where the polycrystalline silicon film is formed.
[0022]
Next, phosphorus or boron is implanted using the first conductive film 14a as a mask to form a low-concentration impurity implanted region 12b in the polycrystalline silicon film 42. This implantation is performed using an ion shower doping apparatus or an ion implantation apparatus. The implantation amount of the low concentration impurity implantation region 12b is 1 × 10 ¹⁷ atoms / cm ³ The following is assumed.
Thus, as shown in FIG. 4, low-concentration impurity-implanted regions 12b to which impurities are added are formed in the polycrystalline silicon films on both sides of the region facing the first conductive film 14a. Further, a region opposite to the first conductive film 14a where the impurity is not added becomes the channel region 12a.
[0023]
Next, as shown in FIG. 5, a second conductive film 14b is formed on the exposed upper surface and side surfaces of the first conductive film 14a by an electrophoretic electrodeposition method. Here, an Al film is used as the first conductive film 14a, and a SnO film is used as the second conductive film 14b. ₂ The case of a film will be described. First, tin ethoxide (Sn (OC ₂ H ₅ ) ₄ ) And the like, and in a colloidal aqueous solution of fine particles of tin dioxide formed by hydrolyzing a tin alkoxide, the Al film 14a is used as an anode and then pulled up. Then, it heats at the temperature of 400-500 degreeC, and dehydrates and bake. Thus, electrophoretic electrodeposition is performed on the Al film 14a, and SnO, which is a conductive oxide, is formed on the upper surface and side surfaces of the Al film 14a. ₂ The film 14b can be formed. In this case, the conductive SnO ₂ The thickness of the film 14b is desirably 1 μm or more and 3 μm or less. This SnO ₂ Due to the volume increase accompanying the film formation, a part of the low-concentration impurity implanted region 12b becomes SnO ₂ Covered by a membrane. Al film 14a and SnO covering this Al film 14a ₂ The gate electrode 14 is constituted by the film 14b.
[0024]
The conductive material formed by the electrophoretic electrodeposition method is ZnO. ₂ And ReO ₃ Other conductive oxides may be used. Further, a metal such as Cr or Mo may be used. Note that ZnO ₂ In the case of Aene ethoxide (Zn (OC ₂ H ₅ ) ₂ ), ReO ₃ In the case of, rhenium ethoxide (Re (OC ₂ H ₅ ) ₃ ) Is subjected to electrophoretic electrodeposition using a metal oxide colloid solution formed by hydrolyzing a metal alkoxide. When a metal is electrophoretically deposited, a metal colloid solution formed by dispersing metal fine particles formed by a gas evaporation method, a spraying method, or the like in water is used for electrophoresis.
[0025]
Thereafter, the surface is cleaned using aqueous ammonia, nitric acid, or the like. Conventionally, when an Al film was used for the gate electrode, most of the acids and alkalis could not be used for the cleaning immediately after, and effective cleaning was difficult. ₂ And ReO ₃ Is poorly soluble in acid and alkali, ZnO ₂ Is hardly soluble in alkali, so that the metal Al inside is protected and metal ions other than the gate wiring portion can be removed. When a metal such as Cr or Mo is used as the protective film, the effect of the protective film is generally limited by the conductive oxide. However, since Cr is insoluble in alkali, cleaning using ammonia water is not possible. Since Mo is insoluble in hydrochloric acid, hydrofluoric acid and dilute sulfuric acid, it is possible to wash with various acids.
[0026]
Next, as shown in FIG. 6, phosphorus or boron is implanted by using the gate electrode 14 as a mask, and a region of the low-concentration impurity implantation region 12b that is not covered with the gate electrode 14 has a higher density than the low-concentration impurity implantation region 12b. A contact region 12c into which a high concentration impurity is implanted is formed. This implantation is performed using an ion shower doping apparatus or an ion implantation apparatus. The active species to be implanted are the same as those used for forming the low-concentration impurity implantation region 12b, of phosphorus or boron. The injection amount of the contact region 12c is 1 × 10 ¹⁹ atoms / cm ³ Above.
[0027]
At this time, of the low-concentration impurity implantation region, SnO ₂ No phosphorus or boron is implanted into the portion covered by the film. This SnO ₂ The portion covered by the film functions as an LDD region. The gate electrode 14 overlaps on the LDD region to form a GOLD structure.
[0028]
As shown in FIG. 6, the width of the Al film 14a becomes the width of the channel region, and the SnO film formed on the side surface of the Al film 14a is formed. ₂ The thickness of the film 14b becomes the width of the LDD region. The width of the channel region is the channel length Lc, and the width of the LDD region is the LDD length (GOLD length) Ld.
[0029]
Next, the contact region 12c is activated by performing a heat treatment.
[0030]
Next, as shown in FIG. 7, an interlayer insulating film 15 is formed on the gate electrode 14 and the gate insulating film 13. About 400 nm of SiO ₂ Is used.
[0031]
Next, hydrogenation is performed for the purpose of terminating dangling bonds in the polycrystalline silicon film with hydrogen. This treatment is performed by heating at 300 ° C. to 450 ° C. for one hour or more under hydrogen plasma.
[0032]
Next, a contact hole is opened on the contact region 12c, a metal film to be a source electrode and a drain electrode is deposited, and processed into a predetermined pattern. Thereby, the source electrode 16 and the drain electrode 17 are electrically connected to the contact region 12c through the contact hole.
[0033]
Finally, by forming a protective film 18 on this surface, the thin film transistor of the first embodiment shown in FIG. 1 is completed.
[0034]
In the method for manufacturing a thin film transistor according to the first embodiment of the present invention, a thin film transistor having a GOLD structure can be manufactured by a self-alignment process using a gate electrode as a mask. Since a mask for forming two types of impurity-implanted regions having different impurity concentrations is formed by one photolithography process, the number of steps can be reduced and a pattern shift can be prevented.
Further, by forming the gate electrode so as to cover the surface of the first conductive film with the second conductive film having good chemical resistance and migration resistance, after forming the gate electrode pattern, various kinds of acid and alkali chemicals are removed. The effects of removing metal ions and organic contaminants and preventing adverse effects due to migration can be obtained by the used cleaning.
Further, by using the electrophoretic electrodeposition method, the conductive film can be formed on a material on which a natural oxide film such as Al, Cr, Mo, and Ti is easily formed, which has been conventionally difficult to form by the electrolytic plating method. The formation can take place.
As described above, according to the method for manufacturing a thin film transistor of Embodiment 1, a highly reliable thin film transistor can be reliably obtained.
[0035]
Embodiment 2 FIG.
FIG. 9 is a diagram illustrating a cross-sectional configuration of the thin film transistor according to the second embodiment of the present invention. The structure of the thin film transistor according to the second embodiment will be described with reference to FIG.
[0036]
In the first embodiment, the gate electrode 14 includes the first conductive film 14a and the second conductive film 14b formed so as to cover the first conductive film 14a by an electrophoretic electrodeposition method. In the second embodiment, the gate electrode 24 includes a first conductive film 24a and a conductive oxide film 24b obtained by oxidizing the first conductive film 24a. Things.
In the semiconductor film 22, a region facing the first conductive film 24a is a channel region 22a, and a region facing the conductive oxide film 24b is a low concentration impurity region 22b. The region on both sides of the region facing the gate electrode 24 is a contact region 22c into which an impurity having a higher concentration is implanted than the low concentration impurity region 22b.
Except for these points, the configuration is the same as that of the first embodiment.
[0037]
Next, a method for manufacturing the thin film transistor according to the second embodiment will be described.
10 to 14 are views for explaining a method for manufacturing a thin film transistor according to the second embodiment of the present invention.
[0038]
First, as shown in FIG. 10, a polycrystalline silicon film 42 is formed on a substrate 11 into a predetermined shape by a method similar to that of the first embodiment, and then a gate insulating film 13 is formed and a gate electrode 24 is formed. One conductive film 24a is formed.
As the first conductive film 24a, a metal material which becomes a conductive oxide film by an oxidation treatment is used. As such a metal material, Sn, In, Zn, Mo, or the like can be used. Here, a case where Mo containing Ni is used as the first conductive film 24a will be described.
[0039]
Next, as shown in FIG. 11, the surface of the Mo film 24a is oxidized to form a conductive oxide film 24b on the exposed upper surface and side surfaces of the Mo film 24a. This oxidation treatment is performed, for example, by placing a substrate having a Mo film formed on its surface in a steam-oxygen mixed gas atmosphere in which oxygen and steam are mixed at a ratio of 2: 8, at about 350 ° C. under a pressure of 1 atm. By holding for several tens minutes. By such an oxidation treatment, for example, 100 nm of the surface of the Mo film is thermally oxidized, and a MoO film having a thickness of 125 nm is formed. ₂ A film 24b is obtained. This MoO ₂ The film is a conductive oxide. Mo film 24a and MoO covering this Mo film 24a ₂ The film 24b forms the gate electrode 24. This MoO ₂ The thickness (125 nm) of the film 24b becomes the LDD length.
[0040]
Next, as shown in FIG. 12, phosphorus or boron is implanted into the polycrystalline silicon film 42 in a region not covered with the gate electrode 24 using the gate electrode 24 as a mask. This implantation is performed using an ion shower doping apparatus or an ion implantation apparatus. By this implantation process, the contact region 22c into which the impurity has been implanted is obtained. The implantation amount of this contact region 22c is 1 × 10 ¹⁹ atoms / cm ³ Above.
In this implantation process, Mo (density 10.28) and MoO ₂ MoO formed on the side surface due to the density difference of (density 6.44) ₂ In the polycrystalline silicon film below the film 24b, a low-concentration impurity implantation region 22b in which an impurity having a lower concentration than the contact region 22c is implanted is formed. The injection amount of this low concentration impurity implantation region 22b is 1 × 10 ¹⁷ atoms / cm ³ It is as follows. This low-concentration impurity implantation region 22b functions as an LDD region. The gate electrode 24 overlaps on the LDD region to form a GOLD structure.
[0041]
As shown in FIG. 12, the width of the Mo film 24a becomes the width Lc of the channel region, and the MoO 24 formed on the side surface of the Mo film 24a is formed. ₂ The thickness of the film 24b becomes the width Ld of the LDD region. The width Lc of the channel region is the channel length, and the width Ld of the LDD region is the LDD length (GOLD length).
[0042]
Next, as in Embodiment 1, activation of the contact region, formation of the interlayer insulating film 15, hydrogenation, and formation of the source electrode 16 and the drain electrode 17 are performed (see FIG. 13). Finally, by forming the protective film 18, the thin film transistor of the second embodiment shown in FIG. 9 is completed.
[0043]
In the above-described method for manufacturing a thin film transistor according to the second embodiment, similarly to the first embodiment, a thin film transistor having a GOLD structure can be manufactured by a self-alignment process using a gate electrode as a mask. Since a mask for forming two types of impurity-implanted regions having different impurity concentrations is formed by one photolithography process, the number of steps can be reduced and a pattern shift can be prevented.
In addition, the gate electrode is covered with an oxide film having good chemical resistance and migration resistance by oxidizing the surface of the first conductive film, so that the gate electrode pattern is formed and then washed with various chemicals such as acids and alkalis. Thereby, effects such as removal of metal ions and organic contaminants and prevention of adverse effects due to migration can be obtained. Thus, a highly reliable thin film transistor can be reliably obtained.
[0044]
Further, in the first embodiment, it is necessary to perform the impurity implantation twice, but in the second embodiment, there is also an effect that the impurity implantation can be reduced to one.
[0045]
Embodiment 3 FIG.
FIG. 14 is a diagram illustrating a cross-sectional configuration of a thin film transistor according to Embodiment 3 of the present invention. The structure of the thin film transistor according to the third embodiment will be described with reference to FIG.
[0046]
In the thin film transistor according to the third embodiment, a semiconductor film 32 including a channel region 32a, a low-concentration impurity implantation region 32b, and a contact region 32c, and a gate electrode 34 formed on the semiconductor film 32 with a gate insulating film 13 interposed therebetween. It is a thing. The thin film transistors of the first and second embodiments have a GOLD structure in which the gate electrode is made of two types of materials and the entire surface of the low-concentration impurity region implantation region is covered with the gate electrode. The thin film transistor No. 3 has a GOLD structure in which only a part of the low-concentration impurity implantation region 32b on the channel region 32a side is covered with the gate electrode 34, as the gate electrode 34.
[0047]
As described above, even in a thin film transistor having a GOLD structure that covers only a part of the low-concentration impurity implantation region, a decrease in on-current can be reduced as compared with a thin film transistor having a conventional LDD structure.
In this embodiment, the gate electrode covers only a part, not the entire surface, of the low-concentration impurity-implanted region, so that a voltage in the off direction is applied to the gate electrode, and a high voltage is applied to the source / drain electrodes. The electric field does not concentrate on the interface between the low-concentration impurity implanted region and the contact region even in the state where it is present. Therefore, current leakage in the source / drain direction caused by the conduction mechanism due to the tunneling phenomenon can be suppressed. Thus, an increase in off-state current can be prevented.
[0048]
Next, a method of manufacturing the thin film transistor according to the third embodiment will be described.
15 to 19 are views for explaining a method of manufacturing the thin film transistor according to the third embodiment of the present invention.
[0049]
First, as shown in FIG. 15, a polycrystalline silicon film 42 having a predetermined pattern is formed on a substrate 11 by the same method as in the first embodiment, and then a gate insulating film 13 is formed. The conductive film 34a is formed. As the first conductive film 34a, a metal material that can facilitate an oxidation-reduction reaction is used. As such a metal material, Ti, Cr, Ta, Mo, or the like can be used. Here, a case where Mo containing Ni is used as the first conductive film 34a will be described.
[0050]
Next, as shown in FIG. 16, the surface of the Mo film as the first conductive film 34a is oxidized to form an oxide film 34b on the exposed upper surface and side surfaces of the Mo film. This oxidation treatment is performed, for example, by placing a substrate on which a Mo film is formed on a surface in a steam-oxygen mixed gas atmosphere in which oxygen and steam are mixed at a ratio of 8: 2, at about 350 ° C. under a pressure of 1 atm. This is done by holding for a few minutes. By such an oxidation treatment, for example, 100 nm of the surface of the Mo film is thermally oxidized, and the MoO film having a thickness of 148 nm is formed. ₃ A film 34b is obtained. This MoO ₂ The thickness (148 nm) of the film 34b becomes the LDD length.
[0051]
In the second embodiment described above, the MoO is formed by oxidation. ₂ In the third embodiment, a film is formed. ₂ Although one condition was exemplified as the oxidation condition for forming the film, the relationship between the oxidation condition and the formed oxide film is shown in the Mo-O system phase diagram, and the Mo-O system phase diagram is shown. The oxidation conditions can be determined with reference to the above.
[0052]
Next, as shown in FIG. 17, phosphorus or boron is implanted into the polycrystalline silicon film 42 using the first conductive film 34a whose surface is covered with the oxide film 34b as a mask. This implantation is performed using an ion shower doping apparatus or an ion implantation apparatus. By this implantation process, the contact region 32c into which the impurity has been implanted is obtained. The implantation amount of this contact region 32c is 1 × 10 ¹⁹ atoms / cm ³ Above.
In this implantation process, Mo (density 10.28) and MoO ₃ MoO formed on the side surface due to the density difference of (density 4.69) ₃ In the polycrystalline silicon below the film 34b, a low-concentration impurity implantation region 32b in which an impurity having a lower concentration than the contact region 32c is implanted is formed. The injection amount in this region is 1 × 10 ¹⁷ atoms / cm ³ It is as follows. This low-concentration impurity implantation region 32b functions as an LDD region.
The region opposite to the first conductive film 34a where the impurity is not added becomes the channel region 32a. The width of the first conductive film 34a becomes the width of the channel region.
The thickness of the oxide film 34b formed on the side surface of the first conductive film 34a becomes the width of the LDD region. The width of the channel region is the channel length Lc, and the width of the LDD region is the LDD length Ld.
[0053]
Next, the surface is cleaned using ammonia water, nitric acid, or the like. MoO ₃ Is insoluble in these acids and alkalis, the metal Mo inside is protected, and it is possible to remove metal ions other than the gate electrode and the gate wiring portion.
[0054]
Next, as shown in FIG. ₃ Reduce the membrane. This reduction treatment is performed, for example, by placing the substrate in a hydrogen-nitrogen mixed gas atmosphere in which hydrogen and nitrogen are mixed at a ratio of 3:97, and holding the substrate at 400 ° C. for 1 hour under a pressure of 1 atm. By such a reduction treatment, MoO ₃ Becomes metal molybdenum.
As described above, the gate electrode 34 is obtained by performing the reduction treatment after the first conductive film 34a is oxidized.
The mixing ratio of hydrogen and nitrogen is such that the concentration of hydrogen in the mixed gas is lower than the lower limit of 4% of the explosion limit of hydrogen, so that it is easy to handle on the production line in the factory and the mixing ratio often used in the reduction step. Ratio.
[0055]
MoO ₃ The volume is reduced by reducing to Mo. Before the reduction process, the oxide film 34b covers the entire low-concentration impurity implantation region 32b, but the gate electrode 34 obtained by the reduction process covers only a part of the low-concentration impurity implantation region 32b on the channel region 32a side. Become like The amount of overlap between the low-concentration impurity implantation region 32b and the gate electrode 34 is the GOLD length Lgd. This GOLD length Lgd is equal to the thickness of the conductive film oxidized during the oxidation treatment. In the case of the above description, the GOLD length Lgd is 100 nm.
[0056]
Next, as in the first embodiment, activation of the contact region, formation of the interlayer insulating film 15, hydrogenation, and formation of the source electrode 16 and the drain electrode 17 are performed (see FIG. 19). Finally, by forming the protective film 18, the thin film transistor according to the third embodiment shown in FIG. 14 is completed.
[0057]
The same effect as in the second embodiment can be obtained also in the method of manufacturing the thin film transistor according to the third embodiment as described above. Furthermore, in the third embodiment, a GOLD structure thin film transistor that covers only a part of the low-concentration impurity implantation region can be reliably manufactured.
[0058]
In the manufacturing methods of the second and third embodiments, the impurity is implanted once after the oxide film is formed as described above. However, as in the first embodiment, the impurity is implanted before and after the oxide film is formed. An injection may be performed.
[0059]
【The invention's effect】
As described above, according to the present invention, since the gate electrode includes the conductive film and the conductive oxide film formed so as to cover the surface of the conductive film, both good electrical characteristics and high reliability are achieved. be able to. Further, it can be manufactured by a simple self-alignment process.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a cross-sectional configuration of a thin film transistor according to Embodiment 1 of the present invention.
FIG. 2 is a diagram illustrating a method for manufacturing the thin film transistor according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating a method for manufacturing the thin film transistor according to the first embodiment of the present invention.
FIG. 4 is a diagram illustrating a method for manufacturing the thin film transistor according to the first embodiment of the present invention.
FIG. 5 is a diagram illustrating a method for manufacturing the thin film transistor according to the first embodiment of the present invention.
FIG. 6 is a diagram illustrating a method for manufacturing the thin film transistor according to the first embodiment of the present invention.
FIG. 7 is a diagram illustrating a method for manufacturing the thin film transistor according to the first embodiment of the present invention.
FIG. 8 is a diagram illustrating a method for manufacturing the thin film transistor according to the first embodiment of the present invention.
FIG. 9 is a diagram illustrating a cross-sectional configuration of a thin film transistor according to a second embodiment of the present invention.
FIG. 10 is a diagram illustrating a method for manufacturing the thin film transistor according to the second embodiment of the present invention.
FIG. 11 is a diagram illustrating a method for manufacturing the thin-film transistor according to the second embodiment of the present invention.
FIG. 12 is a diagram illustrating a method for manufacturing the thin film transistor according to the second embodiment of the present invention.
FIG. 13 is a diagram illustrating a method for manufacturing the thin film transistor according to the second embodiment of the present invention.
FIG. 14 is a diagram illustrating a cross-sectional configuration of a thin film transistor according to Embodiment 3 of the present invention.
FIG. 15 is a diagram illustrating a method for manufacturing the thin film transistor according to the third embodiment of the present invention.
FIG. 16 is a diagram illustrating a method for manufacturing the thin-film transistor according to the third embodiment of the present invention.
FIG. 17 is a diagram illustrating a method for manufacturing the thin-film transistor according to the third embodiment of the present invention.
FIG. 18 is a diagram illustrating a method for manufacturing the thin-film transistor according to the third embodiment of the present invention.
FIG. 19 is a diagram illustrating a method for manufacturing the thin-film transistor according to the third embodiment of the present invention.
[Explanation of symbols]
11 substrate, 12, 22, 32 semiconductor film, 12a, 22a, 32a channel region, 12b, 22b, 32b low concentration impurity implantation region (first impurity implantation region), 12c, 22c, 32c contact region (second impurity Injection region), 13 gate insulating film, 14, 24, 34 gate electrode, 14a, 24a, 34a first conductive film, 14b, 24b second conductive film (conductive oxide film), 34b oxide film, 16 source electrode , 17 drain electrode.

Claims (8)

A substrate having a surface made of an insulating material;
A channel region formed on the substrate, a first impurity implantation region provided adjacent to both sides of the channel region, and the first impurity implantation region provided adjacent to the first impurity implantation region; A semiconductor film having a second impurity-implanted region into which a higher-concentration impurity is implanted;
A gate insulating film formed on the substrate and the semiconductor film,
A conductive film formed on the gate insulating film to face the channel region; and a conductive oxide film formed to cover the surface of the conductive film and facing the first impurity implantation region. A gate electrode;
Source / drain electrodes electrically connected to the second impurity implantation region,
A thin film transistor comprising: 2. The thin film transistor according to claim 1, wherein the conductive oxide film is obtained by oxidizing a surface of the conductive film. A substrate having a surface made of an insulating material;
A channel region formed on the substrate, a first impurity implantation region provided adjacent to both sides of the channel region, and the first impurity implantation region provided adjacent to the first impurity implantation region; A semiconductor film having a second impurity-implanted region into which a higher-concentration impurity is implanted;
A gate insulating film formed on the substrate and the semiconductor film,
A gate electrode formed on the gate insulating film so as to face the channel region and to face a part of the first impurity implantation region on the channel region side;
Source / drain electrodes electrically connected to the second impurity implantation region,
A thin film transistor comprising: A step of forming a semiconductor film over a substrate having a surface made of an insulating material, a step of forming a gate insulating film over the substrate and the semiconductor film, and a step of forming a conductive film constituting a gate electrode over the gate insulating film A step of implanting a first concentration impurity into the semiconductor film using the conductive film as a mask, a step of forming a conductive oxide film forming a gate electrode on a surface of the conductive film, A step of implanting an impurity at a higher concentration than the first concentration into the semiconductor film using the conductive oxide film as a mask; and forming a source / drain electrode electrically connected to the semiconductor film at the high concentration of the impurity implanted. Forming,
A method for manufacturing a thin film transistor comprising: 5. The method according to claim 4, wherein the conductive oxide film is formed by an electrophoretic deposition method. 5. The method according to claim 4, wherein the conductive oxide film is formed by oxidizing a surface of the conductive film. A step of forming a semiconductor film over a substrate having a surface made of an insulating material, a step of forming a gate insulating film over the substrate and the semiconductor film, and a step of forming a conductive film constituting a gate electrode over the gate insulating film A step of oxidizing the surface of the conductive film to form an oxide film, implanting impurities into the semiconductor film using the conductive film and the oxide film as a mask, and a channel region facing the conductive film; Forming a first impurity-implanted region facing the oxide film formed on the side surface of the conductive film, and a second impurity-implanted region into which an impurity having a higher concentration than the first impurity-implanted region is implanted; Forming a source / drain electrode electrically connected to the second impurity-implanted region. 8. The method according to claim 7, further comprising the step of reducing the oxide film after injecting impurities into the semiconductor film.

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