JPH10261798A - Manufacture of thin film transistor and manufacture of liquid crystal panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for the manufacture of TFT and an active matrix substrate wherein when the TFT of LDD structure or offset gate structure is manufactured, variation in its on current or off-leak current can be reduced. SOLUTION: In order to manufacture TFT of LDD structure or offset gate structure, impurity is selectively implanted in a region to be a source and drain region 15 in a semiconductor film 12 away by a specified distance (LDD length or offset length) from the end of a gate electrode 14. For the purpose, a film 50 is formed on the top and side of the gate electrode 14 using electrolytic reaction in advance, and the semiconductor film 12 is implanted with the impurity using the gate electrode 14 with the film 50 formed thereon as mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (hereinafter referred to as TF) having an LDD structure or an offset gate structure.
Called T. ) And a method of manufacturing a liquid crystal panel using the same. For more information,
LD of TFT with LDD structure or offset gate structure
The present invention relates to a technique for stabilizing a D length or an offset length.

[0002]

2. Description of the Related Art When a TFT used for a driving circuit or a pixel switching element is formed in a self-aligned structure on an active matrix substrate with a built-in driving circuit of a liquid crystal display panel, its transfer characteristics are as shown in FIG. There is a problem that the off-leak current is large. FIG.
, A solid line L21 indicates a case where the source / drain voltage is 4V, and a dotted line L22 indicates a case where the source / drain voltage is 8V.
Is the case. Thus, the TF having a large off-leakage current
When T is used as the pixel TFT, the contrast is reduced,
It is likely to cause flicker and display unevenness. In addition, a large off-leakage current of a TFT for a driving circuit is likely to cause unnecessary power consumption, malfunction, and deterioration with time.

[0005] Therefore, in many cases, each TFT is made to have an LDD structure or an offset gate structure to alleviate the electric field intensity at the drain end, and take measures to reduce the off-leak current as shown in FIG. FIG. 10 shows the result of measuring the off-leak current of the TFT having the offset gate structure. The solid line L11 and the dotted line L12 show the measurement results when the source / drain voltage is 4V and 8V, respectively. Further, when a large number of TFTs having an offset gate structure are formed on a large-sized substrate, the relationship between the offset length and the ratio of the off-leak current in the TFT having the offset gate structure to the off-leak current in the TFT having the self-aligned structure and its variation. Have the relationship shown in FIG. 11, and the longer the offset length is, the greater the effect of reducing the off-leak current is. The TFT having the LDD structure has almost the same tendency as the TFT having the offset gate structure.

A TFT having such an LDD structure or an offset gate structure is conventionally manufactured by the following method.

First, as shown in FIG. 12B, a base protective film (not shown) is formed on a substrate 11 shown in FIG.
After sequentially forming a silicon film 12 (semiconductor film), FIG.
As shown in FIG. 2C, the silicon film 12 is patterned to form an island-shaped silicon film 12. Next, FIG.
As shown in FIG.
After the formation of the gate electrode 3, a conductive film is formed on the surface thereof, and is patterned to form the gate electrode 14.

Next, when manufacturing an N-type (first conductivity type) TFT having an LDD structure, as shown in FIG. 12E, a low-concentration N-type (eg, Low concentration first conductivity type) impurities, for example,
The implantation is performed at a dose of × 10 ¹⁴ cm ^-2 . As a result, in the silicon film 12, a low-concentration N-type region 151 having an impurity concentration of about 3 × 10 ¹⁹ cm ⁻³ is self-aligned with the gate electrode.
Are formed, and the portion where the impurity is not introduced becomes the channel region 17.

Next, as shown in FIG. 12 (F), after forming a resist mask 71 which slightly widens the gate electrode 14, as shown in FIG. 12 (G), a high-concentration N-type About 3% impurity of the first conductivity type).
The implantation is performed at a dose of × 10 ¹⁵ cm ^-2 . As a result, a part of the low-concentration N-type region 151 has an impurity concentration of about 3 × 10 ^20.
A high-concentration N-type region 152 of cm ⁻³ is obtained.

Next, as shown in FIG. 12H, after forming an interlayer insulating film 18 on the surface side of the gate electrode 14, a contact hole is formed in the interlayer insulating film 18, and thereafter, the interlayer insulating film 18 is formed. A source electrode 51 and a drain electrode 52 electrically connected to the high-concentration N-type region 152 through the contact hole of FIG.

In the TFT 10 configured as described above, the portion of the source / drain region 15 where the source electrode 51 and the drain electrode 52 are electrically connected is the high-concentration N-type region 1.
In 52, the portion facing the end of the gate electrode 14 via the gate insulating film 13 has the LDD structure of the low concentration region 151.

If the step of introducing a low-concentration N-type impurity shown in FIG. 12E is omitted, the portion corresponding to the low-concentration N-type region 151 in the TFT 10 is different from the channel region 17 in impurity concentration. It will have the same offset gate structure.

In the case of manufacturing a TFT having a P-type (first conductivity type) LDD structure, a low-concentration N-type (low-concentration first conductivity type) impurity is formed in the step shown in FIG. Instead, a low-concentration P-type (low-concentration second conductivity type) such as boron ions is implanted at a dose of, for example, about 2 × 10 ¹⁴ cm ⁻² , and in the step shown in FIG. Instead of the (low-concentration first conductivity type) impurity, a high-concentration P-type (high-concentration second conductivity type) impurity such as boron ion is added to, eg,
The implantation is performed at a dose of × 10 ¹⁵ cm ^-2 .

[0012]

However, FIG.
In the conventional manufacturing method described with reference to FIG.
When the resist mask 71 is formed in the process shown in (1), an alignment error tends to occur between the resist mask 71 and the gate electrode 14, so that the LDD length or the offset length varies, and as a result, the ON current and the OFF leak current also vary. There is a problem. In particular, when a large number of TFTs are formed on a large substrate 11 such as an active matrix substrate of a liquid crystal display panel, the positional relationship between the resist mask 71 and the gate electrode 14 tends to vary because of the large substrate 11. . For example, when a large number of TFTs having an offset gate structure are formed on a large substrate, the relationship between the offset length and the ratio of the ON current of the TFT having the offset gate structure to the ON current of the TFT having the self-aligned structure and the variation thereof. Are in a relationship indicated by a dotted line L31 in FIG.
At T, the on-current tends to vary greatly. The TFT having the LDD structure has almost the same tendency as the TFT having the offset gate structure.

[0013] In view of the above problems, an object of the present invention is to provide:
When a TFT having an LDD structure or an offset gate structure is manufactured, a method of manufacturing a TFT capable of reducing variations in on-current and off-leakage current, and a method of manufacturing an active matrix substrate for a liquid crystal display panel using the same. To provide.

[0014]

In order to solve the above problems, according to the present invention, a substrate has a channel region facing a gate electrode via a gate insulating film, and a source / drain connected to the channel region. In a method of manufacturing a TFT having a region, a semiconductor film for forming the source / drain region, the gate insulating film, and the gate electrode are sequentially formed, and thereafter, a surface portion and a side portion of the gate electrode are subjected to an electrolytic reaction. An LDD structure or an offset gate structure by performing an electrolysis step of depositing a film and a high concentration first conductivity type impurity introducing step of introducing a high concentration first conductivity type impurity into the semiconductor film after forming the film. Is characterized in that a TFT of the first conductivity type is formed.

In the specification of the present application, the high or low impurity concentration means that a portion of a source / drain region in a TFT having an LDD structure which faces a gate electrode via a gate insulating film is a low concentration region. The portion where the source electrode and the drain electrode are electrically connected to each other is a term used to express that the impurity concentration is high, and the absolute value of the impurity concentration is not limited. Further, in the specification of the present application, the first conductivity type and the second conductivity type mean opposite conductivity types, and if the first conductivity type is N-type, the second conductivity type is P-type. Conversely, if the first conductivity type is P-type, the second conductivity type is N-type.

According to the present invention, in order to manufacture a TFT having an LDD structure or an offset gate structure, a predetermined dimension (LDD length or offset length) from an end of a gate electrode to a semiconductor film to be a source / drain region. When impurities are selectively introduced into the region separated from the gate electrode, a film is formed in advance on the gate electrode using an electrolytic reaction. Therefore, when impurities are introduced into the semiconductor film using the film and the gate electrode as a mask, the impurity is formed on the portion of the semiconductor film that is blocked by the gate electrode and on the side surface of the gate electrode without forming a resist mask. No impurity is introduced into the portion blocked by the film. Therefore, the LD corresponding to the thickness of the film formed on the side surface of the gate electrode
A TFT having an LDD structure or an offset gate structure having a D length or an offset length can be manufactured. Here, since the film is deposited on the surface and side surfaces of the gate electrode by an electrolytic reaction, the film thickness can be controlled by the amount of electricity (electrical amount) during the electrolytic reaction. In other words, as long as the amount of current applied during the electrolytic reaction is constant, a film having a constant thickness can be formed, and even when a large number of TFTs are manufactured on the same substrate, the film is deposited on each gate electrode. The film thickness does not vary. Therefore, unlike the case where a resist mask is used, there is no variation in the LDD length or offset length due to an alignment error between the resist mask and the gate electrode. However, variations in the on-current and off-leak current can be significantly reduced.

In the present invention, in the electrolysis step, a film is formed by, for example, an electrophoretic electrodeposition method. When an inorganic film is formed by this electrophoretic electrodeposition method, the inorganic film is left even after the high-concentration impurity introduction step is performed,
An interlayer insulating film may be formed on the surface side of the inorganic film. On the other hand, when the organic film is formed by the electrophoretic electrodeposition method, it is preferable to remove the organic film after performing the high-concentration impurity introduction step and before forming the interlayer insulating film. .

In the present invention, in the electrolysis step, an organic film may be formed by an electrolytic polymerization method. In this case, it is preferable to remove the organic film after performing the high-concentration impurity introduction step and before forming the interlayer insulating film.

In the present invention, after forming a plurality of the semiconductor film, the gate insulating film, and the gate electrode on the substrate, a surface portion of a part of the gate electrode among the plurality of gate electrodes and By forming a film on the side surface in the electrolysis step, and performing the high-concentration first conductivity type impurity introduction step without forming a film in the electrolysis step on the surface and side surfaces of the other gate electrodes, The first conductivity type TFT having the LDD structure or the offset gate structure and the first conductivity type TF having the self-aligned structure;
T and T may be manufactured on the same substrate. In other words, in the electrolysis process, it is possible to selectively deposit a film only on some of the gate electrodes only by energizing some of the gate electrodes and not energizing the other gate electrodes, thereby increasing the number of steps. Thus, the first conductivity type TFT having the LDD structure or the offset gate structure and the first conductivity type TFT having the self-aligned structure can be manufactured on the same substrate.

In the present invention, after forming a plurality of the semiconductor film, the gate insulating film, and the gate electrode on the substrate, a surface of a part of the plurality of gate electrodes is The first conductive type of the LDD structure or the offset gate structure is formed by forming a thick film in the electrolytic process and forming the thin film in the other electrolytic process on the other gate electrodes and then performing the high-concentration impurity introducing process. TFTs having different LDD lengths or offset lengths may be manufactured on the same substrate. That is, in the electrolysis process, a film having a predetermined thickness corresponding to the amount of current can be formed without changing the film thickness by simply changing the amount of current for the electrolytic reaction between the plurality of gate electrodes. Therefore, without increasing the number of processes
TFTs having different LDD lengths or offset lengths can be manufactured on the same substrate.

In the present invention, a semiconductor film for forming a second conductivity type TFT, a gate insulating film,
And forming the gate electrode as a mask after the formation of each of the gate electrodes, without introducing the film in the electrolysis step, and introducing a high-concentration second conductivity type impurity into the semiconductor film using the gate electrode as a mask. By performing the type impurity introducing step, the first conductive type TFT having the LDD structure or the offset gate structure and the second conductive type TFT having the self-aligned structure may be formed on the same substrate.

Also, a TFT of the second conductivity type is provided on the substrate.
After forming a semiconductor film, a gate insulating film, and a gate electrode, respectively, the film is also formed on the gate electrode in the electrolysis step, and after forming the film, the semiconductor has a high concentration of second conductive material. By performing the second conductivity type impurity introduction step of introducing a second type impurity, the second conductivity type TFT having the LDD structure or the offset gate structure and the first conductivity type TFT having the LDD structure or the offset gate structure are formed. They may be formed on the same substrate.

The method of manufacturing a TFT having such a structure is similar to that of an active matrix substrate for a liquid crystal display panel.
It is suitable for manufacturing a large number of TFTs on a large substrate.

[0024]

Embodiments of the present invention will be described with reference to the drawings. In the following description, the method of manufacturing a TFT to which the present invention is applied has the same basic configuration as the conventional method of manufacturing a TFT described with reference to FIG. Is attached.

Embodiment 1 (Outline of TFT Manufacturing Process) FIG. 1 shows a TF according to the present embodiment.
FIG. 4 is a process cross-sectional view illustrating a basic configuration of a method for manufacturing T.

First, as shown in FIG. 1 (A), a transparent insulating substrate 11 such as glass is
(Tetraethoxysilane), oxygen gas, or the like as a source gas, and has a thickness of, for example, about 20 by a plasma CVD method.
A base protective film (not shown) made of a 00 Å silicon oxide film is formed.

Next, as shown in FIG.
Is set to, for example, 350 ° C., and a thickness of, for example, about 60
A semiconductor film 12 such as a 0 Å amorphous silicon film is formed (semiconductor film forming step). When an amorphous silicon film is formed as the semiconductor film 12, the amorphous silicon film is crystallized by a method such as laser annealing or rapid heat treatment, and the semiconductor film 12 is formed as a polysilicon film. In the laser annealing method, for example, the beam length of an excimer laser is 400 m
m line beam, and the output intensity is, for example, 20
0 mJ / cm ² . The line beam is scanned such that a portion corresponding to 90% of the peak value of the laser intensity in the width direction overlaps in each region.

Next, as shown in FIG. 1C, the semiconductor film 12 which has been a polysilicon film is patterned by using a photolithography technique to form an island-shaped semiconductor film 12.
During the above steps, low-concentration impurities may be introduced in order to adjust the threshold value of the TFT.

Next, as shown in FIG. 1D, a thickness of, for example, about 1000 is applied to the surface of the semiconductor film 12 by plasma CVD using TEOS (tetraethoxysilane), oxygen gas or the like as a source gas. A gate insulating film 13 made of an angstrom silicon oxide film is formed (gate insulating film forming step).

Next, after a conductive film such as tantalum is formed on the surface of the gate insulating film 13 by a sputtering method or the like, it is patterned to form a gate electrode 14 (gate electrode forming step).

Next, when manufacturing an N-type (first conductivity type) TFT having an LDD structure, as shown in FIG.
Using the gate electrode 14 as a mask, a low-concentration N-type (low-concentration first conductivity type) impurity such as phosphorus ions is, for example, about 3 × 1
It is implanted at a dose of 0 ¹⁴ cm ^-2 (low concentration first conductivity type impurity introduction step). As a result, the impurity concentration in the silicon film 12 is about 3 × 10
A low-concentration N-type region 151 of ¹⁹ cm ^-3 is formed, and a portion where impurities are not introduced becomes a channel region 17.

Next, as will be described in detail later, the substrate 11 is immersed in an electrolytic solution, a counter electrode is arranged on the substrate 11, and a current is applied between the counter electrode and the gate electrode 14. As shown in FIG. 1 (F), a film 50 having a thickness of about 0.1 μm to about 2.0 μm is formed on the surface and side surfaces of the gate electrode 14 by an electrolytic reaction (electrolysis step).

Here, when the inorganic film 50 having an extremely low insulating or conductive property is formed as the film 50, there is no problem even if the inorganic film 50 is left as it is. I do.

That is, as shown in FIG. 1 (G), a high concentration N-type (high concentration first conductivity type) impurity such as phosphorus ions is used as a mask with the gate electrode 14 having the film 50 formed on the surface and side portions. Is implanted at a dose of, for example, about 3 × 10 ¹⁵ cm ⁻² (high concentration first conductivity type impurity introduction step). As a result, the silicon film 12 has a high N concentration of about 3 × 10 ²⁰ cm ⁻³ in a region at a predetermined distance (0.1 μm to about 2.0 μm) from the end of the gate electrode 14.
A mold region 152 is formed.

Next, if necessary, a heat treatment is performed in a forming gas or the like to activate the impurities introduced into the semiconductor film 12, and then, as shown in FIG.
An interlayer insulating film 18 made of a silicon oxide film having a thickness of, for example, about 5000 angstroms is formed on the surface side (surface side of the film 50) by plasma CVD using TEOS (tetraethoxysilane), oxygen gas, or the like as a source gas. I do. Next, a contact hole is formed in the interlayer insulating film 18, and thereafter, a source electrode 19 and a drain electrode 20 that are electrically connected to the high-concentration N-type region 152 via the contact hole in the interlayer insulating film 18 are formed.

In the TFT 10 configured as described above, the portion of the source / drain region 15 where the source electrode 51 and the drain electrode 52 are electrically connected is the high-concentration N-type region 1.
In 52, the portion facing the end of the gate electrode 14 via the gate insulating film 13 has the LDD structure of the low concentration region 151.

If the low-concentration N-type impurity conducting step shown in FIG. 1E is omitted, the TFT 10 has a portion corresponding to the low-concentration N-type region 151 having the same impurity concentration as the channel region 17. It will have a gate structure.

When the TFT 10 is manufactured for a pixel, the source electrode 51 is a part of a data line made of aluminum or an alloy thereof, and the source electrode 51 is a part of the gate electrode 14.
Is a part of the scanning line. Also, the drain electrode 52 is
It is a pixel electrode made of a transparent electrode such as an O film.

As a method of introducing impurities, for example, a method of implanting all ions generated from a dopant gas without mass separation, a so-called ion doping method can be used. In this method, for example, when N-type impurities are implanted at a high concentration, a mixed gas containing about 5% of PH ₃ and the balance of hydrogen gas is used, and all ions generated from the mixed gas are separated by mass. Drive without releasing. In contrast, when N-type impurities are implanted at a low concentration,
After implanting all ions generated from a mixed gas containing about 5% of PH ₃ and the remainder consisting of hydrogen gas without mass separation, ions generated from pure hydrogen gas are implanted without mass separation, and a silicon film is formed. It is preferable to terminate the asymmetric bond therein. Further, as a method for introducing impurities, a plasma doping method, a laser doping method, or the like may be used in addition to the ion implantation method and the ion doping method.

When a TFT having a P-type (second conductivity type) LDD structure is manufactured, a low-concentration N-type (low-concentration first conductivity type) impurity is formed in the step shown in FIG. Instead, a low-concentration P-type (low-concentration second conductivity type) such as boron ions is implanted at a dose of, for example, about 2 × 10 ¹⁴ cm ⁻² , and in the step shown in FIG. Instead of the (low-concentration first conductivity type) impurities, a high-concentration P-type (high-concentration second conductivity type) impurity such as boron ions is, for example, about 2 ×
The implantation is performed at a dose of 10 ¹⁵ cm ^-2 .

(One Example of Electrolysis Step) In the method of manufacturing a TFT according to the present embodiment, in the electrolysis step described with reference to FIG. There is a law. In this electrophoretic electrodeposition method, the substrate 11 that has been subjected to the steps described with reference to FIG. 1E is immersed in the electrolytic cell 101 shown in FIG. This electrolytic cell 101 contains an electrolytic solution 102, and the substrate 11
And the counter electrode 103 such as platinum.
1 is arranged.

Here, in the electrolytic solution 102, the surface of fine particles of colloidal silica (SiO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide (TaO _x ), alumina (Al ₂ O ₃ ), etc. The charged fine particles which have been subjected to a surface treatment with a silane coupling agent, an anionic surfactant, a cationic surfactant or the like are in a state of being dispersed in a solvent. Therefore, when a direct current is applied between the gate electrode 14 on the substrate 11 side and the counter electrode 103, the charged fine particles made of the oxide adhere to and deposit on the surface and side surfaces of the gate electrode 14. At this time, the current is supplied to the electrolyte 102
The gate electrode 14 is used as a positive electrode or a negative electrode depending on the type of the charged fine particles dispersed therein. As a result, a film 50 (inorganic film) having a thickness corresponding to the amount of electricity (electrical amount) defined by the electrolysis current and the electrolysis time is formed on the surface portion and the side portion of the gate electrode 14. According to such a method, there is an advantage that processing can be performed with a relatively simple apparatus regardless of the size and shape of the substrate. Further, according to the electrophoretic electrodeposition method, the film thickness is about 0.1 μm to about 2.0 μm.
m, a thick film 50 can be formed.
The D length and the offset length can be set to dimensions sufficient to reduce the off-leak current.

(Effect of this Embodiment) As described above, in the method of manufacturing the TFT 10 according to this embodiment, in order to manufacture the TFT 10 having the LDD structure or the offset gate structure, the source / drain is introduced in the high-concentration first conductivity type impurity introducing step. Area 15
When impurities are selectively introduced into the semiconductor film 12 to be formed into a region separated by a predetermined dimension (LDD length or offset length) from the end of the gate electrode 14, the film is formed by using an electrolytic reaction. Impurities are introduced into the semiconductor film 12 using the gate electrode 14 after the formation of the mask 50 as a mask. As a result, even if a resist mask is not formed, a high portion of the semiconductor film 12 is blocked by the gate electrode 14 and a portion blocked by the coating 50 formed on the side surface of the gate electrode 14. No impurity concentration is introduced. Therefore, the TFT 10 having the LDD structure or the offset gate structure having the LDD length or the offset length corresponding to the thickness of the film 50 formed on the side surface of the gate electrode 14 can be manufactured. Here, the film 50 is formed only by the electrolytic reaction on the gate electrode 14.
The film thickness can be controlled by the amount of electricity (electrical amount) during the electrolytic reaction.
In other words, as long as the amount of current applied during the electrolytic reaction is constant, a film 50 having a constant thickness can be formed, and even when a large number of TFTs 10 are manufactured on the same substrate 11, The thickness of the deposited film 50 does not vary. Therefore, unlike the case where the resist mask is used, the variation in the LDD length or the offset length due to the alignment error between the resist mask and the gate electrode 14 does not occur, so that the TFT 10 having the LDD structure or the offset gate structure is manufactured. In this case, the variation in the on-current and the off-leak current can be reduced. For example, when a TFT 10 having an offset gate structure is manufactured, the relationship between the offset length, the ratio of the ON current of the TFT having the offset gate structure to the ON current of the TFT having the self-aligned structure, and the variation thereof are shown in FIG. The relationship indicated by L32 is obtained, and the variation can be significantly suppressed.

Further, in the present embodiment, the film 50 formed on the surface and the side surface of the gate electrode 14 is an inorganic film (oxide film) to the last, and this inorganic film has an extremely low insulating property or electric conductivity. Therefore, even if the TFT is left as it is, the TFT 10 exhibits good characteristics as a TFT having an LDD structure or an offset gate structure. Further, since the film 50 is an inorganic film, it has high heat resistance and the like, and does not lower the reliability of the TFT 10.

[Second Embodiment] In the first embodiment, the inorganic film is deposited on the surface and the side of the gate electrode 14. However, the surface and the side of the gate electrode 14 are formed. On the other hand, as a film 50, an organic film,
Alternatively, an example in which a conductive inorganic film is formed will be described. In this case, the film 50 is finally removed so as not to be left so as not to impair the characteristics and reliability of the TFT.

(Outline of TFT Manufacturing Process) FIG. 3 is a process sectional view showing a basic configuration of a TFT manufacturing method according to the present embodiment. Note that the substrate 11 shown in FIG.
A semiconductor film forming step shown in FIG. 3B, a patterning step shown in FIG. 3C, a gate electrode forming step shown in FIG.
The low concentration first conductivity type impurity introduction step shown in FIG.
Embodiment 1 FIGS. 1A, 1B, 1C,
Since these steps are common to the steps described with reference to (D) and (E), the steps after the electrolysis step shown in FIG.

In the present embodiment, in the electrolysis step shown in FIG. 3 (F), the substrate 11 is immersed in an electrolytic solution, and a counter electrode is disposed on the substrate 11. The first embodiment differs from the first embodiment in that a current flows between the gate electrode 14 and an electrolytic reaction to form a film 50 having a thickness of about 0.1 μm to about 2.0 μm on the surface and side surfaces of the gate electrode 14. Common (electrolysis process).
However, in this embodiment, since the organic film or the conductive inorganic film is formed as the film 50, the TFT 10 is formed as described below.

First, as shown in FIG. 3 (G), a high concentration N-type (high concentration first conductivity type) impurity such as phosphorus ions is formed by using a gate electrode 14 having a film 50 formed on the surface and side surfaces as a mask. Is implanted at a dose of, for example, about 3 × 10 ¹⁵ cm ⁻² to form a high-concentration N-type region 152, a low-concentration N-type region 151, and a channel region 17 in the same manner as in the first embodiment (high-concentration). First conductivity type impurity introduction step)).

However, in this embodiment, as shown in FIG. 3H, after the film 50 is removed from the surface and the side surface of the gate electrode 14, TEOS is applied to the surface of the gate electrode 14.
(Tetraethoxysilane), oxygen gas, or the like as a raw material gas to a thickness of, for example, about 50 by a plasma CVD method or the like.
An interlayer insulating film 18 made of a 00 Å silicon oxide film is formed. Next, a contact hole is formed in the interlayer insulating film 18, and thereafter, a source electrode 19 and a drain electrode 20 that are electrically connected to the high-concentration N-type region 152 via the contact hole in the interlayer insulating film 18 are formed.

In the TFT 10 configured as described above, the portion of the source / drain region 15 where the source electrode 51 and the drain electrode 52 are electrically connected to each other is the high-concentration N-type region 152, and the end of the gate electrode 14 has a gate insulating film. A portion facing the film 13 has the LDD structure of the low-concentration region 151.

By omitting the low-concentration N-type impurity introduction step shown in FIG. 3E, the TFT 10 can have an offset gate structure, and the impurity to be introduced into the semiconductor film 12 is changed to an N-type impurity. If it is a P-type impurity, TFT
The point that 10 can be a P type is the same as in the first embodiment.

(Example of Electrolysis Step) In this embodiment, FIG.
In the electrolytic process described with reference to (F), the film 50
Electrophoretic electrodeposition can also be used to form an organic film. Also in the electrophoretic electrodeposition method at this time, as described in Embodiment 1, the substrate 11 that has been subjected to the steps described with reference to FIG. 3E is immersed in the electrolytic cell 101 shown in FIG. . Electrolyte solution 102 is stored in electrolytic cell 101, and substrate 11 is arranged such that substrate 11 and counter electrode 103 face each other, as in the first embodiment. However, in the present embodiment, in the electrolytic solution 102, fine particles of a polymer having a functional group such as a carboxyl group are dispersed as charged fine particles.

For example, the electrolytic solution 102 has the following composition: Composition 1 Polyester resin polymer 6 parts by weight Melamine resin polymer 2 parts by weight Ethyl cellosolve 2 parts by weight Water 90 parts by weight Electrolysis voltage 4 V Electrolysis time Several minutes Polyester after deposition of film 50 Crosslinking conditions between resin and melamine resin Heat treatment at 180 ° C for 30 minutes Composition 2 Epoxy resin polymer 6 parts by weight Urethane resin polymer 2 parts by weight Ethyl cellosolve 2 parts by weight Water 90 parts by weight Electrolysis voltage 10 V Electrolysis time Several minutes may be used. Acrylic resin, phenol resin and the like can be used as the polymer.

Using such an electrolytic solution 102, the substrate 1
When a DC power supply is applied between the gate electrode 14 on the first side and the counter electrode 103, the charged fine particles (charged polymer) adhere to the surface and side surfaces of the gate electrode 14,
accumulate. At this time, depending on the polarity of the charged fine particles dispersed in the electrolytic solution 102, the gate electrode 14 is set to a positive electrode or a negative electrode. As a result, a film 5 having a film thickness corresponding to the amount of electricity (electrical amount) defined by the electrolytic current and the electrolytic time.
0 will be formed on the surface and side surfaces of the gate electrode 14. In addition, according to the electrophoretic electrodeposition method, a film 50 having a thickness of about 0.1 μm to about 2.0 μm can be formed, so that the LDD length and the offset length of the TFT 10 are sufficiently large to reduce the off-leak current. It can be.

(Another Example of Electrolysis Step) TFT According to the Present Embodiment
In the electrolytic method described with reference to FIG. 3 (F), an electrolytic polymerization method can also be used to form an organic film as the film 50 in the manufacturing method described above. In this electrolytic polymerization method, FIG.
Substrate 11 that has completed the steps described with reference to FIG.
Is immersed in the electrolytic cell 201 shown in FIG. This electrolytic cell 2
An electrolytic solution 202 is put in 01, and the substrate 11 is arranged so that the substrate 11 and the counter electrode 203 (cathode) face each other. Here, in the electrolytic solution 202, a monomer or oligomer of a conductive polymer such as polypyrrole, polyaniline, or polyparaphenylin is used as a solvent using water, acetonitrile, or the like as a solvent (CH ₃ ) ₄ NClO ₄ , (C ₂ H ₅ ). _Four
Supporting electrolytes such as BF ₄ , 0.1 mol / dm ³ -1.
It is blended together with 0 mol / dm ³ .

As the electrolytic solution 202 for forming a polypyrrole film by this electrolytic polymerization, for example, a solvent appropriately mixed with methanol, ethanol, benzonitrile, acetic anhydride, water, or the like is used as a solvent, and LiPF together with monomers and oligomers is added thereto. ₆ or a mixture of a supporting electrolyte such as LiAsF ₆ and a surfactant such as alkylsulfonic acid can be used. Using such an electrolytic solution 202, while controlling the potential during electrolysis by the reference electrode 204, using a DC power supply 205 to ~ 4.0V vs SC
E. FIG. Or ~ 1.0V vs SCE. The electrolysis is performed under the electrolysis conditions described above. As a result, a polypyrrole film having a thickness corresponding to the amount of electricity (electricity) defined by the electrolysis current and the electrolysis time is formed on the surface and side surfaces of the gate electrode 14 as the film 50. Moreover, according to the electrolytic polymerization method,
Since the film 50 having a thickness of about 0.1 μm to about 2.0 μm can be formed, the LDD length and the offset length of the TFT 10 can be set to a size sufficient to reduce the off-leak current.

(Effects of the present embodiment) As described above, in the method of manufacturing a TFT according to the present embodiment, the film 50 is formed on the gate electrode 14 in advance by utilizing the electrolytic reaction, similarly to the first embodiment. In the high-concentration first-conductivity-type impurity introduction step, impurities are introduced into the semiconductor film 12 using the gate electrode 14 after the formation of the film 50 as a mask. As a result, even if the resist mask is not formed, the portion of the semiconductor film 12 that is blocked by the gate electrode 14 and the portion that is blocked by the coating 50 formed on the side surface of the gate electrode 14 have impurities. Is not introduced, a TFT having an LDD structure or an offset gate structure having an LDD length or an offset length corresponding to the thickness of the film 50 formed on the side surface of the gate electrode 14 can be manufactured. Here, since the film 50 is deposited only on the surface and side surfaces of the gate electrode 14 by an electrolytic reaction, the thickness of the film 50 can be controlled by the amount of electricity (electricity) during electrolysis. Multiple T on top
Even when the FT 10 is manufactured, the thickness of the film 50 deposited on each gate electrode 14 does not vary. Therefore, unlike the case where the resist mask is used, the LDD caused by the positioning error between the resist mask and the gate electrode 14 is different.
Since there is no variation in the length or the offset length, even when the TFT 10 having the LDD structure or the offset gate structure is manufactured, the variation in the ON current and the OFF leak current can be reduced.

[Modification of Second Embodiment] In the method of manufacturing a TFT described with reference to FIG. 3, since the film 50 formed on the surface portion and the side portion of the gate electrode 14 is removed, FIG. , A low-concentration N-type impurity introduction step may be performed after the film 50 is removed.

Also in this embodiment, the substrate 1 shown in FIG.
1, (A), (B), and (C) until the semiconductor film forming step shown in FIG. 5B, the patterning step shown in FIG. 5C, and the gate electrode forming step shown in FIG. ) And (D) are common to the steps described with reference to FIG. 5 (E).

In this embodiment, after the gate electrode 14 is formed in the step shown in FIG. 5D, an electrolysis step is performed as it is as shown in FIG. A film 50 is formed.

Next, as shown in FIG. 5 (F), using the gate electrode 14 having the film 50 formed on the surface and side surfaces as a mask, a high-concentration N-type (high-concentration first conductivity type) of phosphorus ions or the like is used. Impurities are implanted at a dose of, for example, about 3 × 10 ¹⁵ cm ⁻² to form a high-concentration N-type region 152.

Next, since the film 50 is an organic film, as shown in FIG. 5 (G), the film 50 is removed from the surface and side surfaces of the gate electrode 14, and then the gate electrode 14 is masked. As low-concentration N such as phosphorus ions
Type (low-concentration first conductivity type) impurities of, for example, about 3 × 10
^The low-concentration N-type region 15 is implanted at a dose of ¹⁴ cm ^-2.
1 and a channel region 17 are formed.

Thereafter, as shown in FIG. 5H, after the film 50 is removed from the surface and the side surface of the gate electrode 14, TEOS (tetraethoxysilane), oxygen gas or the like is applied to the surface of the gate electrode 14. Insulating film 18 made of a silicon oxide film having a thickness of, for example, about 5000 .ANG.
To form Next, a contact hole is formed in the interlayer insulating film 18, and thereafter, a source electrode 19 and a drain electrode 20 that are electrically connected to the high-concentration N-type region 152 via the contact hole in the interlayer insulating film 18 are formed.

In the TFT 10 configured as described above, a portion of the source / drain region 15 where the source electrode 51 and the drain electrode 52 are electrically connected to each other is the high-concentration N-type region 152. A portion facing the film 13 has the LDD structure of the low-concentration region 151.

[Third Embodiment] A method of manufacturing an active matrix substrate for a liquid crystal display panel using the TFT manufacturing methods according to the first and second embodiments and the modifications thereof will be described.

(Configuration of Active Matrix Substrate) FIG.
FIG. 6A is a block diagram schematically showing the configuration of an active matrix substrate with a built-in drive circuit used for a liquid crystal display panel, and FIG. 6B is a CMOS diagram of the drive circuit.
It is a circuit diagram of a circuit.

As shown in FIG. 6A, a pixel area defined by data lines 90 and scanning lines 91 is provided on a substrate 11 for an active matrix of a liquid crystal display panel. There is a liquid crystal capacitor 94 of a liquid crystal cell to which an image signal is input via the TFT 10 for use. For the data line 90, the shift register 84, the level shifter 8
5, a data driver unit 82 having a video line 87 and an analog switch 86 is formed on an active matrix substrate. For a scanning line 91, a scanning driver unit 83 including a shift register 88 and a level shifter 89 is formed on an active matrix substrate.
In the pixel region, a storage capacitor 93 is provided between the pixel region and the scanning line 91 in the preceding stage.
May be formed, and the storage capacitor 93 has a function of improving the charge holding characteristics of the liquid crystal cell (liquid crystal capacitor 94).

The data driver section 82 and the scan driver section 8
In FIG. 3, as shown in FIG.
The FT 20 and the TFT 30 for the P-type driving circuit make the CM
An OS circuit is configured. Therefore, it can be said that three types of TFTs 10, 20, and 30 are used in the active matrix substrate with a built-in drive circuit in terms of conductivity and use.

(Method of Manufacturing Active Matrix Substrate)
Therefore, in this embodiment, an active matrix substrate is manufactured by using the method for manufacturing a TFT described with reference to the first embodiment. Moreover, three different types of TFT
The method for manufacturing the will be described. In this case, the film 50 is formed on the gate electrode of each TFT of the active matrix substrate by an electrolytic reaction.
As shown in (A), a power supply pattern 101 and a terminal 102 electrically connected to each gate electrode of all the pixel TFTs 10, and a power supply pattern 201 electrically connected to each gate electrode of every N-type drive circuit TFT 20. And terminal 2
02, and a power supply pattern 301 and a terminal 302 that are electrically connected to each gate electrode of all the P-type drive circuit TFTs 30 are formed as necessary by appropriately using other wiring layer forming steps, Power is supplied to each gate electrode by using them. Here, the power supply patterns 101, 201,
301 are electrically independent from each other. After the electrolysis step is completed, these power supply patterns 101, 201, 301 and terminals 102, 202,
Since 302 is electrically separated from each gate electrode, there is no hindrance to the operation of the liquid crystal display panel.

In this embodiment, first, as shown in FIG. 7, semiconductor films 12 and 22 for forming an N-type TFT, gate insulating films 13 and 23, and gate electrodes 14 and 24 are formed on a substrate 11. After the formation, the plurality of gate electrodes 1
4 and 24, a film 50 is formed on the surface and side surfaces of some of the gate electrodes 14 by the electrolytic process described with reference to FIG. The film 50 is not formed on the side surface in the electrolysis step.
Thereafter, in this state, the high-concentration N-type impurity introduction step described with reference to FIG. 1G is performed so that the semiconductor film 12 has a high height in a region separated by a predetermined dimension from the end of the gate electrode 14. Concentration N type region 152 (source / drain region)
To form At the same time, the gate electrode 24 is
Then, a high-concentration N-type region 252 (source / drain region) is formed in a separate manner. As a result, the N-type TFT 10 (pixel TFT) having an offset gate structure and the N-type thin film transistor 20 (N-type drive circuit TFT) having a self-aligned structure can be manufactured on the same substrate.

At the same time, a P-type TFT 30
, A gate insulating film 33, and a gate electrode 34 are also formed, and the film 50 is formed on the gate electrode 34 by the electrolytic process described with reference to FIG.
Is formed, a high-concentration P-type impurity is introduced into the semiconductor film 32 using the gate electrode 34 as a mask (second conductivity type impurity introduction step). As a result, the semiconductor film 32 has a high concentration P-type region
(Source / drain regions) are formed, so that the N-type TFT 10 (pixel TF) having the above-described offset gate structure is formed.
T), a self-aligned N-type TFT 20 (N-type drive circuit TFT), and a self-aligned P-type TFT 30 (P-type drive circuit TFT) can be formed on the same substrate. .

During this time, when introducing a high concentration N-type impurity, the P-type TFT 30 is covered with a resist mask,
When introducing high-concentration P-type impurities, the N-type TFT 1
Needless to say, 0 and 20 are covered with a resist mask.

In a state where the film 50 has not been formed in the above-described electrolytic process, or in a state where the film 50 has been formed in the electrolytic process but removed as in the modification of the second embodiment, the film 50 is formed. Using the gate electrode 14 as a mask,
If a low concentration N-type impurity is introduced into the semiconductor film 12, the TFT
10 can have an LDD structure.

As described above, according to the present embodiment, in the electrolysis step, only the gate electrode 14 is energized and the other gate electrodes 24 and 34 are not energized, and the coating 50 is selectively applied only to the gate electrode 14. Can be deposited. Therefore, the N-type TFT 10 having the LDD structure or the offset gate structure and the N-type and P-type TFTs 20 and 30 having the self-aligned structure can be manufactured on the same substrate without increasing the number of steps. Moreover, in the N-type TFT 10 having the LDD structure or the offset gate structure, the variation in the ON current and the OFF leak current is small.

[Embodiment 4] A method of manufacturing an active matrix substrate for a liquid crystal display panel using the method of manufacturing a TFT according to Embodiments 1 to 3 will be described.
Note that the configuration of the active matrix substrate and the method of supplying power to the gate electrode are the same as those in Embodiment 3, and thus description thereof is omitted.

In the present embodiment, as shown in FIG.
A semiconductor film 12, 2 for forming an N-type TFT is formed thereon.
2, gate insulating films 13 and 23, and gate electrode 14,
After the formation of each of the gate electrodes 24, the surface of some of the gate electrodes 14, 24 is coated by increasing the amount of electricity in the electrolysis step described with reference to FIG. 50 is formed thick, and the other gate electrode 2 is formed.
In No. 4, the film 50 is formed thinner by reducing the amount of electricity in the electrolysis step. Next, by performing the high-concentration impurity introduction step described with reference to FIG. 1F, TFTs having different offset lengths are formed on the same substrate as the N-type TFTs 10 and 20 having the offset gate structure.

After a semiconductor film 32 for forming a P-type TFT, a gate insulating film 33, and a gate electrode 34 are also formed on the substrate 11, the gate electrode 34 is also provided with a structure shown in FIG. In the electrolytic process described with reference to FIG.
Then, a second conductivity type impurity introduction step of introducing a high concentration second conductivity type impurity into the semiconductor film 34 is performed using the gate electrode 34 on which the film 50 is formed as a mask. As a result, a P-type TFT 3 having an offset gate structure is formed.
0 (P-type driving circuit TFT), an N-type TFT 20 having the same offset length as the TFT 30 (N-type driving circuit TFT), and an N-type TFT 10 (pixel TFT having a shorter offset length than the TFT 20). ) Can be formed on the same substrate.

During this time, when introducing a high concentration N-type impurity, the P-type TFT 30 is covered with a resist mask,
When introducing high-concentration P-type impurities, the N-type TFT 1
Needless to say, 0 and 20 are covered with a resist mask.

In the state where the film 50 has not been formed yet in the above-described electrolytic process, or in the state where the film 50 has been formed in the electrolytic process but has been removed as described in the modification of the second embodiment, the film 50 is formed. Low concentration N-type impurities are introduced into the semiconductor films 12 and 22 using the gate electrodes 14 and 24 without 50 as a mask, and low concentration P-type impurities are introduced into the semiconductor film 32 using the gate electrode 34 without the film 50 as a mask. If so, any of the TFTs 10, 20, 30 can have an LDD structure. In this case, the LDD length of the TFT 10 is long,
The LDD lengths of the TFTs 20 and 30 are short.

As described above, according to the present embodiment, in the electrolysis step, the thickness of the plurality of gate electrodes 14, 24, and 34 is not varied by merely changing the amount of electricity for the electrolytic reaction. On the surface and side surfaces of the gate electrodes 14, 24, 34, a film 50 having a predetermined thickness in accordance with the amount of electricity can be formed. Therefore, N-type and P-type semiconductor devices having different LDD lengths or offset lengths can be used without increasing the number of steps.
Type TFTs 10, 20, 30 can be manufactured on the same substrate.

In the specification of the present application, the first conductivity type is N-type, and the second conductivity type is P-type. That is, in the third and fourth embodiments, the pixel TFT may be configured as a P-type TFT. Further, in the third and fourth embodiments, the embodiment using the electrolysis process performed in the first embodiment has been described. However, the embodiment may use the electrolysis process performed in the second embodiment or a modification thereof. . Furthermore, Embodiment 3,
For the three types of TFTs shown in FIG. 4, respectively,
The combination may be formed on the same substrate in an appropriately changed form.

Although not shown, using the active matrix substrate formed in the above embodiment, a counter substrate having a counter electrode is arranged at an appropriate distance,
Liquid crystal is sealed in the space between the active matrix substrate and the opposing substrate, whereby a liquid crystal display panel can be manufactured.

[0083]

As described above, according to the present invention, in a semiconductor film to be a source / drain region, an impurity is placed in a region separated by a predetermined dimension (LDD length or offset length) from an end of a gate electrode. When selectively introducing,
Impurities are introduced into the semiconductor film using the gate electrode after the film is formed on the side surface in the electrolytic process as a mask. Therefore, even if a resist mask is not formed, the LDD structure or offset gate structure having an LDD length or an offset length corresponding to the thickness of the film formed on the side surface of the gate electrode.
FT can be manufactured. Here, since the film is deposited on the surface and side surfaces of the gate electrode by an electrolytic reaction, the film thickness can be controlled by the amount of electricity (electricity) during electrolysis. In other words, as long as the amount of current applied during the electrolytic reaction is constant, a film having a constant thickness can be formed, and even when a large number of TFTs are manufactured on the same substrate, the film is deposited on each gate electrode. The film thickness does not vary. Therefore, unlike the case where a resist mask is used, there is no variation in the LDD length or offset length due to an alignment error between the resist mask and the gate electrode.
Even when a TFT having a DD structure or an offset gate structure is manufactured, it is possible to reduce variations in the ON current and the OFF leak current.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a TFT according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an electrophoretic electrodeposition method.

FIG. 3 is a process sectional view illustrating the method for manufacturing the TFT according to the second embodiment of the present invention.

FIG. 4 is an explanatory diagram of an electrolytic polymerization method.

FIG. 5 is a process sectional view illustrating the method for manufacturing the TFT according to the modification of the second embodiment of the present invention.

FIG. 6A is an explanatory diagram of an active matrix substrate of a liquid crystal display device, and FIG. 6B is an explanatory diagram showing a CMOS circuit thereof.

FIG. 7 is a cross-sectional view for describing a method for manufacturing an active matrix substrate for a liquid crystal display panel according to Embodiment 3 of the present invention.

FIG. 8 is a cross-sectional view for explaining a method of manufacturing an active matrix substrate for a liquid crystal display panel according to Embodiment 4 of the present invention.

FIG. 9 is a graph showing transfer characteristics of a self-aligned TFT.

FIG. 10 is a graph showing transfer characteristics of a TFT having an offset gate structure.

FIG. 11 is a graph showing a relationship between an offset length of a TFT, a ratio of an off-leak current in an offset-gate TFT to an off-leak current in a self-aligned TFT, and its variation.

FIG. 12 is a process sectional view showing a method for manufacturing a conventional TFT having an LDD structure or an offset gate structure.

FIG. 13 is a graph showing the relationship between the offset length of the TFT, the ratio of the on-current of the TFT having the offset gate structure to the on-current of the TFT having the self-aligned structure, and its variation.

[Explanation of symbols]

 10, 20 N-type TFT 11 Substrate 12, 22, 32 Semiconductor film 13, 23, 33 Gate insulating film 14, 24, 34 Gate electrode 15 Source / drain region 30 P-type TFT 50 Film 151 Low-concentration N-type region 152 , 252 High concentration N-type region 352 High concentration P-type region

Claims (11)

[Claims] 1. A method for manufacturing a thin film transistor comprising a channel region on a substrate facing a gate electrode via a gate insulating film, and a source / drain region connected to the channel region, wherein the source / drain region is formed. Semiconductor film,
After the gate insulating film and the gate electrode are sequentially formed, an electrolytic step of depositing a film on the surface and side surfaces of the gate electrode by an electrolytic reaction, and after forming the film, a high concentration first A method of introducing a high-concentration first conductivity type impurity for introducing a conductivity type impurity. 2. The method according to claim 1, wherein in the electrolysis step,
A method for manufacturing a thin film transistor, wherein the film is formed by an electrophoretic electrodeposition method. 3. The method according to claim 2, wherein in the electrolysis step, an inorganic film is formed as the film by electrophoretic electrodeposition.
A method for manufacturing a thin film transistor, wherein the inorganic film is left even after the high-concentration impurity introduction step is performed, and an interlayer insulating film is formed on a surface side of the inorganic film. 4. The method according to claim 2, wherein in the electrolysis step, an organic film is formed as the film by electrophoretic electrodeposition.
A method of manufacturing a thin film transistor, comprising: removing the organic film after forming the high-concentration impurity introduction step and before forming an interlayer insulating film. 5. The method according to claim 1, wherein in the electrolysis step,
A method for manufacturing a thin film transistor, wherein an organic film is formed as the film by an electrolytic polymerization method. 6. The method according to claim 5, wherein the organic film is removed after forming the high-concentration impurity introduction step and before forming an interlayer insulating film. 7. The method according to claim 1, wherein
After forming a plurality of the semiconductor film, the gate insulating film, and the gate electrode on the substrate, respectively, a surface portion and a side portion of some of the plurality of gate electrodes are formed by the electrolytic process. Manufacturing the thin film transistor, wherein the high-concentration first-conductivity-type impurity introducing step is performed on the surface and side surfaces of the other gate electrodes without forming the film in the electrolytic step. Method. 8. The method according to claim 1, wherein
After forming a plurality of the semiconductor film, the gate insulating film, and the gate electrode on the substrate, the surface of some of the plurality of gate electrodes is coated with the film in the electrolysis step. A method for manufacturing a thin film transistor, comprising: forming a thick film; forming a thin film on the other gate electrodes in the electrolytic process; and then performing the high-concentration impurity introducing process. 9. The semiconductor device according to claim 1, 7 or 8, wherein a semiconductor film, a gate insulating film, and a gate electrode for forming a thin film transistor of the second conductivity type are formed on the substrate, respectively. Manufacturing a thin film transistor, wherein a second conductivity type impurity introduction step of introducing a high concentration second conductivity type impurity into the semiconductor film using the gate electrode as a mask without forming the film in the electrolysis step is performed. Method. 10. The semiconductor device according to claim 1, 7 or 8, wherein a semiconductor film, a gate insulating film, and a gate electrode for forming a thin film transistor of a second conductivity type are formed on the substrate. Forming a film in the electrolysis step, and performing a second conductivity type impurity introduction step of introducing a high concentration second conductivity type impurity into the semiconductor film after forming the film. . 11. An active matrix substrate formed by using the method of manufacturing a thin film transistor according to claim 1 and a counter substrate having a counter electrode are arranged at an appropriate distance. In addition, a method of manufacturing a liquid crystal panel, wherein liquid crystal is sealed in a space between the active matrix substrate and the counter substrate.