KR20020032196A - Polysilicon-thin film transistor device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A polysilicon thin film transistor and a method of fabricating the thin film transistor are provided to increase mobility in the silicon surface and to mitigate damages in the thin film transistor. CONSTITUTION: A substrate(150) is prepared, and a thin film transistor including a gate electrode(170), a source electrode(192), a drain electrode(194), an active layer(160) and ohmic contact layers(162a,162b) is formed on the substrate. The active layer is formed in such a manner that an amorphous silicon is deposited, eximer laser is irradiated on the amorphous silicon to change the amorphous silicon into polysilicon, and grain boundaries of the polysilicon exposed to the surface of the polysilicon are flattened through plasma etch.

Description

Polysilicon thin film transistor device and method of manufacturing the same {Polysilicon-thin film transistor device and method of fabricating the same}

The present invention relates to an image display device, and more particularly, to a method of manufacturing a liquid crystal display device (LCD) including a thin film transistor (TFT) and a liquid crystal display device according to the method. It is about.

Recently, as the information society has progressed rapidly, a display field for processing and displaying a large amount of information has been developed.

Recently, the need for a flat panel display (plate panel display) has emerged in order to meet the era of thinning, light weight, low power consumption. Accordingly, a thin film transistor-liquid crystal display (hereinafter referred to as TFT-LCD) having excellent color reproducibility and thinness has been developed.

In general, the driving principle of the liquid crystal display device is the optical anisotropy and polarization property of the liquid crystal. The polarization property of the liquid crystal is thin and long structure of the liquid crystal and has an orientation in the arrangement of molecules. It means that the direction of the can be controlled.

Accordingly, the molecular arrangement of the liquid crystal is changed by applying an electric field to the liquid crystal, and when the light is irradiated, the light is polarized by the optical anisotropy of the liquid crystal.

Currently, many active matrix LCDs (AM-LCDs) in which the above-described thin film transistors and pixel electrodes connected to the thin film transistors are arranged in a matrix manner are used. Such active matrix liquid crystal display devices have a number of pixels. Increasing the value of is not the deterioration (contrast), such as (damage), the resolution and the ability to implement the video is attracting the most attention.

The structure of a liquid crystal panel which is a basic component constituting a general liquid crystal display will be described in detail with reference to FIG.

The liquid crystal panel 20 is formed in such a manner that two substrates 2 and 4 having various kinds of elements are formed to correspond to each other, and the liquid crystal layer 10 is filled between the two substrates 2 and 4. have.

In this case, the two substrates constituting the liquid crystal panel 20 may include a color filter substrate 8 and a color filter substrate 4 having a common electrode 12 covering the color filter layer 8 and a liquid crystal layer. Is divided into a thin film transistor (S) which is a switching circuit capable of converting a molecular arrangement direction of the array substrate and an array substrate (2) divided into a pixel portion (P). In particular, the above-described array substrate (2) is separated from the thin film transistor (S). It further includes a pixel electrode 14 serving as the other electrode for receiving a signal and applying a voltage to the liquid crystal layer.

In order to prevent leakage of the liquid crystal 10 injected between the color filter substrate 4 and the array substrate 2 and to fix the substrates, a coated sealant 6 is disposed at the edge of the liquid crystal layer.

In the above-described active matrix liquid crystal display device, a thin film transistor positioned on an array substrate and serving as a switching element will be described in more detail. The thin film transistor includes a gate electrode, a gate insulating film, an active layer, an ohmic contact layer, a source electrode, and a drain electrode. The elements constituting the thin film transistor are stacked in the form of a thin film to form the thin film transistor.

In particular, the activation layer and the ohmic contact layer form a channel layer by receiving an electrical signal from the above-described gate electrode, and serve to transfer the image signal input through the source electrode to the drain electrode. Amorphous silicon (a-Si: H), which is a material, is mainly used because amorphous silicon has some advantageous properties compared to crystalline silicon (monocrystalline silicon, polycrystalline silicon).

In other words, amorphous silicon can be deposited at low temperature in large area compared to crystalline silicon, and when it forms boundary with other materials, it has various advantages such as good boundary property and strong scratch resistance and formation of fine patterns using transfer photos. Because of this, the active layer of the thin film transistor is widely used in comparison with crystalline silicon. However, such amorphous silicon has a high defect due to its unique aperiodic lattice characteristics, and has a low concentration of charge carriers. Since it also has disadvantages that are not suitable for operation, research is being conducted and developed to solve these problems.

In order to solve these problems, laser crystallization is performed to anneal the amorphous silicon thin film by irradiation of an energy beam, preferably an excimer laser, to convert selected portions of the amorphous silicon thin film into a polysilicon (poly Si: H) film. A laser crystallization method has been proposed.

The laser crystallization method described above will be described taking a coplanar thin film transistor as an example.

First, the coplanar thin film transistor will be described. As shown in FIG. 2, the coplanar thin film transistor has a substrate 50 and a buffer layer 55 deposited on the front surface of the substrate, and is formed on the buffer layer 55. The activating layer 60 having a shape of island and the ohmic contact layers 62a and 62b doped with ions in both of the activating layer 60 are positioned in a horizontal direction in contact with the activating layer 60. The island-like gate insulating film 65 and the gate electrode 70 are sequentially stacked on the layer 60.

Contact holes exposing portions of the ohmic contact layers 62a and 62b which are horizontally connected to both sides of the activation layer 60 on the front surface of the substrate on which the gate electrode 70 is formed, in contact with the activation layer 60. A passivation layer 75 having 80a and 80b is deposited, and a source electrode 92 and a drain contacting the ohmic contact layers 62a and 62b through the contact holes 80a and 80b of the passivation layer 75. The electrode 94 is positioned to complete the coplanar thin film transistor.

Referring to the process sequence for manufacturing the coplanar thin film transistor, first, as shown in FIG. 3, a substrate 50 made of an organic substrate, a wafer, or a plastic material capable of withstanding a high temperature of 600 ° C. or higher is provided. A buffer layer 55 having a predetermined thickness is formed on the entire surface in order to prevent diffusion of impurities generated in a later process.

Subsequently, amorphous silicon having a thickness of about 300 mW to 1000 mW is deposited on the entire surface of the substrate having the buffer layer 55 in the form of a thin film using plasma chemical vapor deposition or low pressure CVD. The amorphous silicon thin film 57a is converted into polysilicon using a laser crystallization method.

In the crystallization method using an excimer laser, as shown in the drawing, the amorphous silicon thin film 57a is melted by irradiating an energy beam while moving the entire substrate on which the amorphous silicon thin film 57a is deposited.

The energy beam used is preferably an excimer laser, which is a pulsed UV beam, which is short in the order of tens of nsec when the excimer laser is used despite the high temperature at which amorphous silicon is fused. This is because it has the advantage of not damaging the substrate because the heat treatment in time.

The excimer laser is repeatedly irradiated with a predetermined repetition rate to scan the amorphous silicon thin film 57a formed on the substrate by a scan method. When the excimer laser is scanned on the amorphous silicon thin film 57a, the entire surface of the substrate is scanned. The upper surface of the amorphous silicon thin film 57a is melted.

At this time, by controlling the energy of the excimer laser appropriately, the amorphous silicon thin film 57a deposited on the entire surface of the substrate is almost melted, and only a portion of the buffer layer 55 and the amorphous silicon 57a that are not partially melted, that is, in the subsequent crystallization process Make sure there is a part that can be a seed (58).

Subsequently, when the irradiation of the excimer laser is stopped, the molten amorphous silicon thin film solidifies as the seed 58 existing at the interface between the buffer layer 55 and the amorphous silicon thin film 57a of the substrate becomes a crystal nucleus and is solidified. The polycrystalline silicon 57b is changed as shown in FIG.

When the molten amorphous silicon thin film is solidified and changed into polycrystalline silicon 57b, first, the grains grow in the vertical direction with the seed 58 as the crystal nucleus, and the growth of the crystal grains in the vertical direction is completed. When the growth is continuously performed in the horizontal direction, collisions occur between neighboring grains. Particularly, since silicon has a higher density than liquid, the grain boundary protrudes from the surface. The length of the grain boundary 59 protruding to the surface is proportional to the energy of the excimer laser to be irradiated, but is generally larger than the thickness of the polycrystalline silicon thin film 57b, and its component is oxidized silicon (Si-rich). oxide), which contains more oxygen than inter grains of polycrystalline silicon.

Subsequently, the polycrystalline silicon thin film 57b is patterned and etched to form a semiconductor layer as shown in FIG. 5, and then the island-like gate insulating film 65 and the gate electrode 70 are sequentially stacked on the semiconductor layer. Afterwards, when the doped impurities are doped in the lower exposed semiconductor layer using the gate electrode 70 as a mask, the activation layer 60 and the activation layer 60 positioned at the bottom in contact with the gate insulating layer are activated. The ohmic contact layers 62a and 62b formed in a horizontal direction in contact with the layer 60 are formed.

Subsequently, an insulating material is deposited on the entire surface of the substrate and patterned to form a passivation layer 75 having contact holes 80a and 80b which are exposed portions of the ohmic contact layers 62a and 62b.

Thereafter, as shown in FIG. 6, the source electrode 92 and the drain electrode 94 electrically connected to the ohmic contact layers 60a and 60b through the respective contact holes 80a and 80b formed in the above-described process, are formed. This completes the thin film transistor.

In order to form the active layer 60 and the ohmic contact layers 62a and 62b which constitute the thin film transistors as described above, a method of changing amorphous silicon into polycrystalline silicon through a crystallization method using an excimer laser as described above is provided. When fabricating a thin film transistor using the same, as shown in the circle, protruding grain boundaries 59 are formed on the surfaces of the active layer 60 and the ohmic contact layers 62a and 62b, which are polycrystalline silicon composed of a plurality of crystal grains. The length is generally formed to a length of 300 Å to 1000 Å larger than the thickness of the polysilicon thin film.

The grain boundary 59 protruding on the surfaces of the activation layer 60 and the ohmic contact layers 62a and 62b not only roughens the surfaces of the activation layer 60 and the ohmic contact layers 62a and 62b, but also the activation layer. The gate insulating layer 62 deposited on the 60 may be broken to cause a short with the gate electrode 70, and the ohmic contact layers 62a and 62b, the drain electrode 94, and the source electrode 92 may be formed. This causes problems such as poor contact and decreases device mobility.

The present invention has been made to solve the above problems, and in the manufacturing process of a general thin film transistor, amorphous silicon is melted and solidified through excimer laser annealing to form polycrystalline silicon having a plurality of crystal grains, and then By planarizing the grain boundaries protruding from the surface by using a plasma etching process method, the purpose is to increase the device mobility of the silicon surface and to reduce the degradation on the device.

Another object of the present invention is to provide a method for manufacturing a liquid crystal display device including a thin film transistor having excellent characteristics.

1 is a cross-sectional view showing a part of a liquid crystal panel of a general liquid crystal display device.

2 is a cross-sectional view schematically showing a cross section of a typical coplanar thin film transistor

3 to 6 are manufacturing process diagrams sequentially showing a manufacturing process of a common coplanar thin film transistor.

7 is a cross-sectional view schematically showing a cross section of a coplanar thin film transistor according to the present invention.

8 to 12 are manufacturing process diagrams sequentially showing the manufacturing process of the coplanar thin film transistor according to the present invention.

<Description of the symbols for the main parts of the drawings>

150: lower substrate 155: buffer layer

160: active layer 159: grain boundaries protruding to the surface

160a, 160b: ohmic contact layer 165: gate insulating film

170: gate electrode

Providing a substrate to achieve the object; A method of forming a thin film transistor including a gate electrode, a source electrode, a drain electrode, an active layer, and an ohmic contact layer on the substrate, the method comprising: depositing amorphous silicon; Irradiating the amorphous silicon with an excimer laser to form polycrystalline silicon composed of a plurality of crystal grains; It provides a thin film transistor manufacturing method comprising the step of planarizing the grain boundary protruding to the surface of the polycrystalline silicon through a plasma etching process.

In particular, the amorphous silicon is characterized in that it further comprises a dehydrogenation process.

In addition, the gas used in the plasma etching treatment is characterized in that consisting of CF ₄ and H ₂ ,

The gas used in the plasma etching process is characterized in that it further comprises HCl.

In addition, the addition ratio of H ₂ gas in the gas used in the plasma etching method is characterized in that 20% to 30%.

Hereinafter will be described in detail with reference to embodiments and drawings according to the present invention.

As an embodiment according to the present invention, a coplanar thin film transistor is described as an example.

In the coplanar thin film transistor according to the present invention, as shown in FIG. 7, the substrate 150 and the buffer layer 155 are disposed on the entire surface of the substrate, and an activation layer having an island shape is formed on the buffer layer 155. The ohmic contact layers 162a and 162b doped with both the 160 and the activating layer 160 are horizontally connected to the activating layer 160 and have an island shape on the above-described activating layer 160. The gate insulating film 165 and the gate electrode 170 are stacked in this order.

A contact hole exposing a part of the ohmic contact layers 162a and 162b horizontally connected to both sides of the activation layer 160 on the front surface of the substrate on which the gate electrode 170 is formed. A passivation layer 175 having 180a and 180b is deposited, and a source electrode 192 and a drain contacting the ohmic contact layer 162a and 162b through the contact holes 180a and 180b of the passivation layer 175. When the electrode 194 is positioned, the coplanar thin film transistor is completed.

The coplanar thin film transistor according to the present invention described above will be described with reference to Figs.

First, the manufacturing process of the coplanar thin film transistor according to the present invention includes a substrate 150 made of an organic substrate, a wafer, or a plastic material capable of withstanding a high temperature of 600 ° C. or higher, as shown in FIG. 8. A buffer layer 155 having a predetermined thickness is formed to prevent diffusion of impurities generated in a later process.

Subsequently, amorphous silicon having a thickness of about 300 μs to 1000 μs is deposited on the entire surface of the substrate having the above-described buffer layer 155 in the form of a thin film by using plasma chemical vapor deposition or low pressure CVD. In addition, the amorphous silicon thin film 157a is transformed into polycrystalline silicon having a plurality of crystal grains by using a laser crystallization method. The excimer laser crystallization method according to the present invention will be described in more detail with a substrate on which the amorphous silicon thin film 157a is deposited. The amorphous silicon thin film 157a is melted by irradiating an energy beam while moving the whole.

The energy beam used is preferably an excimer laser, which is a pulsed UV beam, which is short in the order of tens of nsec when the excimer laser is used despite the high temperature at which amorphous silicon is fused. This is because it has the advantage of not damaging the substrate because the heat treatment in time.

The excimer laser is repeatedly irradiated with a predetermined repetition rate to scan the amorphous silicon thin film 157a formed on the substrate by scanning. When the excimer laser is scanned on the amorphous silicon thin film 157a, the entire surface of the substrate is scanned. It melts from the upper end of the amorphous silicon thin film 157a.

At this time, by controlling the energy of the excimer laser appropriately, the amorphous silicon thin film 157a deposited on the entire surface of the substrate is almost melted and partially melted only at the interface between the buffer layer 155 and the amorphous silicon 157a, that is, in a later crystallization process. Make sure there is a part that can be a seed (158).

Subsequently, when the irradiation of the excimer laser is stopped, as shown in FIG. 9, the molten amorphous silicon thin film 157a is determined at the interface between the buffer layer 155 of the substrate and the amorphous silicon thin film 157a as described above. As the nucleus is solidified, the polycrystalline silicon 157b is composed of a plurality of grains and has a grain boundary 159 protruding from the surface thereof.

Since the present invention is characterized in that it further comprises a plasma etching process for controlling the grain boundary 159 protruding on the surface of the polycrystalline silicon thin film 157b in particular.

That is, as shown in FIG. 9, the grain boundary 159 protruding from the surface of the polysilicon thin film 157b described above has more O ₂ than Si-rich oxide than grains forming the polycrystalline silicon thin film 157b. ; SiO 4) component, CF ₄ / H ₂ (or CF ₄ / H ₂ / HCl), which is a gas capable of etching the grain boundary 159 protruding on the surface faster than the grains of the polycrystalline silicon (157b) is used. In this way, when the plasma etching process is performed, CF ₄ reacts with Si to generate volatile SiF ₄ , and H ₂ reacts with O ₂ , thus protruding from the surface of oxidized silicon (SiOx). The grain boundary 159 may be selectively etched to control the roughness of the surface of the polycrystalline silicon thin film 157b.

At this time, HCl added to the gas used in the plasma etching process according to the present invention serves to further increase the reaction rate.

In addition, the addition ratio of H ₂ in CF ₄ / H ₂ (or CF ₄ / H ₂ / HCl), which is a gas used in the plasma etching process according to the present invention, is about 20% to 30% of the total surface of the polycrystalline silicon. In controlling the roughness by etching the protruding grain boundary, it may be the most preferred embodiment of the present invention.

When the plasma etching process is performed with the addition ratio of H ₂ below 20%, both the grains constituting the polysilicon thin film and the grain boundaries formed on the surface of the polysilicon thin film are etched. Since it becomes impossible, and adding more than 30%, the time of the plasma etching process for controlling the grain boundary protruding on the surface is long, the time to be exposed to the plasma gas is long, which impairs the characteristics of the device.

Subsequently, as shown in FIG. 11, the polycrystalline silicon thin film 157b is patterned and etched to form a semiconductor layer. Then, the island-like gate insulating film 165 and the gate electrode 170 are sequentially stacked on the semiconductor layer. By using the gate electrode 170 as a mask, the doped impurities are doped in the lower exposed semiconductor layer to be in contact with the gate insulating layer 165 and disposed at both ends of the activation layer 160 and the activation layer 160. The ohmic contact layers 162a and 162b formed in a horizontal direction in contact with the activation layer 160 are formed, and an insulating material is deposited and patterned on the entire surface of the substrate to expose the ohmic contact layers 162a and 162b. The passivation layer 175 having the contact holes 180a and 180b is formed.

Thereafter, as shown in FIG. 12, a source electrode 192 and a drain electrode 194 are electrically connected to the ohmic contact layers 160a and 160b through the respective contact holes 180a and 180b formed in the above-described process. The coplanar thin film transistor according to the present invention is completed.

As such, the active layer 160 and the ohmic contact layers 162a and 162b, which constitute the thin film transistor, are changed into polycrystalline silicon composed of a plurality of crystal grains through a crystallization method using an excimer laser as described above. When a thin film transistor is fabricated using the method and the grain boundary protruding from the surface thereof is subjected to the plasma etching process according to the present invention, the surface of the active layer 160 and the ohmic contact layer 162a, 162b as shown in the circle. The length of the protruding grain boundary 159 formed in the control panel 300 Å or less can be flattened.

In a thin film transistor using polycrystalline silicon formed through an excimer laser crystallization method as an active layer and an ohmic contact layer, a method of plasma etching according to the present invention is used to crystal grain boundaries protruding from the surface of the active layer and the ohmic contact layer. By planarization, it is possible to effectively control the short circuit of the device due to the breakdown of the insulating layer which can occur in the general thin film transistor and the reduction of electron mobility, thereby providing a more reliable thin film transistor.

While specific embodiments of the invention have been described and illustrated, it will be apparent that the invention may be embodied in various modifications by those skilled in the art.

Such modified embodiments should not be understood individually from the technical idea or the viewpoint of the present invention, and such modified embodiments should fall within the scope of the appended claims of the present invention.

Claims (5)

Providing a substrate; In the method of forming a thin film transistor including a gate electrode, a source electrode and a drain electrode, an active layer and an ohmic contact layer on the substrate, the activation layer is Depositing amorphous silicon; Irradiating the amorphous silicon with an excimer laser to form polycrystalline silicon composed of a plurality of crystal grains; Planarizing the grain boundaries protruding from the surface of the polycrystalline silicon through a plasma etching process Thin film transistor manufacturing method comprising a. The method according to claim 1, The amorphous silicon is a method of manufacturing a thin film transistor further comprising a dehydrogenation process The method according to claim 1, Gas used in the plasma etching process is a manufacturing method of a thin film transistor consisting of CF ₄ and H ₂ The method according to claim 3, Method for manufacturing a thin film transistor further comprising HCl as a gas used in the plasma etching process The method according to claim 3 or 4, A method of manufacturing a thin film transistor in which the addition ratio of H ₂ gas in the gas used in the plasma etching treatment method is 20% to 30%.