JP2004341337A - Liquid crystal device, its manufacturing method, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a redox reaction between an electrode and an alignment layer due to incident light and to suppress the occurrence of image persistence phenomenon. <P>SOLUTION: The liquid crystal device is provided with a first electrode 9a formed on a first transparent substrate 10 of the first and a second substrates which are disposed opposite to each other and between which a liquid crystal is enclosed, a second electrode 21 formed on the second transparent substrate 20, a first passivation film 91 formed on the first electrode 9a and containing a conductive material, a second passivation film 92 formed on the second electrode 21 and containing a conductive material, a first alignment layer 16 formed on the first passivation film 91 and a second alignment layer 22 formed on the second passivation film 92. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal device capable of preventing a burn-in phenomenon, a manufacturing method thereof, and an electronic apparatus.
[0002]
[Prior art]
A liquid crystal device is configured by sealing liquid crystal between two substrates such as a glass substrate and a quartz substrate. In an active matrix type liquid crystal device, active elements such as thin film transistors (hereinafter, referred to as TFTs) are arranged in a matrix on one substrate, and a counter electrode (transparent electrode (ITO) is disposed on the other substrate). (Tin Oxide))) is arranged to change the optical characteristics of the liquid crystal layer sealed between the two substrates according to an image signal, thereby enabling image display. The optical characteristics of the liquid crystal layer are controlled by applying a voltage based on an image signal to the liquid crystal layer to change the arrangement of liquid crystal molecules.
[0003]
In order to regulate the arrangement of liquid crystal molecules when no voltage is applied, an alignment film is formed on a surface of one substrate (active matrix substrate) and the other substrate (counter substrate) that are in contact with the liquid crystal layer, and a rubbing process is performed on the alignment film. Is applied. The alignment film is formed by forming an organic film of, for example, polyimide on the surfaces of both substrates with a thickness of about several tens of nanometers. The alignment film can align liquid crystal molecules along the substrate surface. Further, by performing a rubbing treatment on the surface of the alignment film, the alignment film is made an alignment anisotropic film and the alignment of the liquid crystal molecules is defined.
[0004]
Then, by turning on the TFT element, an image signal is supplied to the pixel electrodes (ITO) arranged in a matrix, and a voltage based on the image signal is applied to a liquid crystal layer between the pixel electrode and the counter electrode, and the liquid crystal is turned on. Changes the arrangement of molecules. Thus, the image display is performed by changing the transmittance of the pixel and changing the light passing through the pixel electrode and the liquid crystal layer according to the image signal.
[0005]
The TFT element is turned on and off by a scanning signal (gate signal) supplied via a scanning line (gate line). In a state where the scanning signal is applied to turn on the TFT element, an image signal of a voltage corresponding to the gradation is applied to the pixel electrode via the data line (source line). Even if the TFT element is turned off after the voltage is supplied to the pixel electrode, the voltage applied to each pixel is maintained by the capacitance of the liquid crystal layer, the storage capacitance, and the like.
[0006]
Incidentally, an oxidation-reduction reaction occurs between the pixel electrode (ITO) and the alignment film. This redox reaction is accelerated by light and heat. When a liquid crystal device is used for a projector, a large amount of light is incident on the pixel region to increase the brightness of the projected image, so that the oxidation-reduction reaction between the pixel electrode and the alignment film is promoted, and the alignment film is Deteriorates.
[0007]
Therefore, by interposing a passivation film (reaction prevention film) on the entire surface of the substrate between the ITO and the alignment film, the deterioration of the alignment film due to such a redox reaction is prevented. Note that there is a proposal in Patent Document 1 as an example in which a passivation film is formed.
[0008]
[Patent Document 1]
Japanese Patent Application No. 5-241196
[Problems to be solved by the invention]
In a liquid crystal device, for example, the application of a DC component of an applied signal causes decomposition of the liquid crystal component and contamination by impurities in the liquid crystal cell, thereby causing a phenomenon such as burn-in of a display image. Therefore, in general, inversion driving is performed in which the polarity of the driving voltage of each pixel electrode is inverted for each field in an image signal, for example.
[0010]
As described above, in the liquid crystal device, the driving voltage is applied to the pixel only in a part of the period in consideration of the capacitance. However, during a period in which the drive voltage is not applied, the voltage applied to the pixel gradually decreases due to the influence of the coupling capacitance and the leakage of the charge. In this case, the decrease in the electrode applied voltage during the positive drive is greater than the decrease in the electrode applied voltage during the negative drive. Therefore, negative charges are likely to be accumulated on the counter substrate side.
[0011]
Conversely, the counter substrate and the TFT substrate have different irregularities on the surface on which the alignment film is formed, and this effect makes it easier for negative ions to remain on the TFT substrate side.
[0012]
Negative ions near the alignment film in the liquid crystal diffuse into the liquid crystal or are relaxed between the ITO electrodes. However, when a passivation film is formed between the alignment film and the ITO, the negative ions relaxed between the ITO electrodes by the passivation film having a high insulating property decrease, and the ions easily remain near the alignment film. turn into. That is, there is a problem that ions in the liquid crystal are easily adsorbed on the alignment film, and the effect of the DC component applied to the liquid crystal by the adsorbed ions increases, thereby accelerating the burn-in phenomenon.
[0013]
The present invention has been made in view of such a problem, and improves the charge mobility of a passivation film by lowering the resistance of a passivation film formed on a pair of substrates disposed to face each other. It is an object of the present invention to provide a liquid crystal device, a method of manufacturing the same, and an electronic apparatus capable of preventing ions from remaining at an interface and preventing a burn-in phenomenon.
[0014]
[Means for Solving the Problems]
The liquid crystal device according to the present invention includes: a first electrode formed on the first transparent substrate among the first and second transparent substrates which are disposed to face each other and in which liquid crystal is sealed; A second electrode formed on the substrate, a first passivation film formed on the first electrode, a second passivation film formed on the second electrode, A first alignment film formed on a passivation film; and a second alignment film formed on the second passivation film, wherein at least one of the first passivation film and the second passivation film is provided. One includes a conductive material, and the passivation film including the conductive material has a specific resistance of 10 ⁶ to 10 ¹⁴ [Ω · cm].
[0015]
According to such a configuration, the first passivation film intervenes between the first electrode and the first alignment film, and the second passivation film intervenes between the second electrode and the second alignment film. A passivation film is interposed. The first and second passivation films prevent a redox reaction between the first electrode and the first alignment film and a redox reaction between the second electrode and the second alignment film. Further, at least one of the first and second passivation films is formed to contain a conductive material, and has a low resistance. Therefore, at least one of the first and second passivation films has a high charge mobility, and charges are relatively easily transferred to at least one of the first and second electrodes via at least one of the first and second passivation films. , Ions at the interface of at least one of the first and second alignment films are reduced. Thereby, ions do not stay at at least one interface between the first and second alignment films, and a DC component is prevented from being applied to the liquid crystal, so that a burn-in phenomenon can be prevented.
[0016]
In the liquid crystal device according to the present invention, the first electrode is a pixel electrode provided on a first transparent substrate corresponding to pixels arranged in a matrix, and the second electrode is Wherein the specific resistance of the second passivation film is lower than the specific resistance of the first passivation film.
[0017]
According to such a configuration, the charge mobility of the second passivation film can be improved, and the image sticking phenomenon can be suppressed.
[0018]
Further, the first electrode is a pixel electrode provided on a first transparent substrate corresponding to pixels arranged in a matrix, and the second electrode is provided on the second transparent substrate. Wherein the first passivation film is patterned corresponding to each pixel electrode without straddling a plurality of adjacent pixel electrodes.
[0019]
According to such a configuration, the first electrode is a patterned pixel electrode. Even in this case, since the first passivation film is patterned without straddling a plurality of pixel electrodes, there is no short circuit between the pixel electrodes.
[0020]
Further, the first and second passivation films have a specific resistance value smaller than 10 ¹¹ [Ω · cm].
[0021]
According to such a configuration, since the first and second passivation films have relatively high specific resistance values, the first and second passivation films short-circuit the first electrodes or the second electrodes. Never.
[0022]
The method for manufacturing a liquid crystal device according to the present invention includes a step of forming a first electrode on the first transparent substrate among the first and second transparent substrates in which liquid crystal is sealed while being opposed to each other; Forming a second electrode on the second transparent substrate, forming a first passivation film on the first electrode, and forming a second passivation film on the second electrode A step of forming a first alignment film on the first passivation film, and a step of forming a second alignment film on the second passivation film, wherein the first passivation film And at least one of the second passivation film contains a conductive material, and the passivation film containing the conductive material has a specific resistance of 10 ⁶ to 10 ¹⁴ [Ω · cm].
[0023]
According to such a configuration, the first alignment film is formed on the first electrode with the first passivation film interposed therebetween, and the first alignment film is formed on the second electrode with the second passivation film interposed therebetween. 2 are formed. The first and second passivation films prevent a redox reaction between the first electrode and the first alignment film and a redox reaction between the second electrode and the second alignment film. Further, at least one of the first and second passivation films is formed to contain a conductive material, and has a low resistance. Therefore, at least one of the first and second passivation films has a high charge mobility, and charges are relatively easily transferred from at least one of the first and second electrodes via at least one of the first and second passivation films. At the interface of at least one of the first and second alignment films. Thereby, ions do not stay at at least one interface between the first and second alignment films, and a DC component is prevented from being applied to the liquid crystal, so that a burn-in phenomenon can be prevented.
[0024]
According to another aspect of the invention, there is provided an electronic apparatus configured using any one of the above liquid crystal devices.
[0025]
According to such a configuration, the burn-in phenomenon is suppressed, and a high-quality image can be obtained.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view showing a liquid crystal device according to the first embodiment of the present invention. FIG. 2 is a plan view of a TFT substrate (element substrate) constituting a liquid crystal device together with components formed thereon as viewed from the counter substrate side. FIG. FIG. 3 is a cross-sectional view of the liquid crystal device after completion of an assembling step of sealing the liquid crystal device, taken along the line HH ′ in FIG. 2. FIG. 4 is an equivalent circuit diagram of various elements, wiring, and the like in a plurality of pixels constituting a pixel region of the liquid crystal device. FIG. 5 is a sectional view showing the pixel structure of the liquid crystal device in detail. FIG. 6 is a flowchart showing a method of manufacturing the element substrate of the liquid crystal device of FIG. In each of the above drawings, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.
In this embodiment, by imparting conductivity to the passivation film, the charge mobility of the passivation film is improved, ions are prevented from staying at the interface of the alignment film, and as a result, a DC component is applied to the liquid crystal. This prevents the image sticking phenomenon. In the present embodiment, the passivation film formed between the pixel electrode on the TFT substrate side and the alignment film is patterned for each pixel to prevent short circuit between the pixel electrodes. ing.
[0027]
First, the overall structure of the liquid crystal device will be described with reference to FIGS.
[0028]
As shown in FIGS. 2 and 3, the liquid crystal device includes, for example, a TFT substrate 10 made of a quartz substrate, a glass substrate, and a silicon substrate, and an opposing substrate 20 made of, for example, a glass substrate or a quartz substrate. A liquid crystal 50 is sealed between the two. The TFT substrate 10 and the opposite substrate 20 that are arranged to be opposed to each other are bonded together with a sealant 52.
[0029]
On the TFT substrate 10, pixel electrodes (ITO) 9a and the like constituting pixels are arranged in a matrix. A counter electrode (ITO) 21 is provided on the entire surface of the counter substrate 20. On the pixel electrode 9 a of the TFT substrate 10, an alignment film 16 that has been subjected to a rubbing treatment via a passivation film 91 is provided. The passivation film 91 is formed by patterning each pixel so as not to straddle the adjacent pixel electrode 9a. On the other hand, an alignment film 22 that has been subjected to a rubbing treatment via a passivation film 92 is also provided on the counter electrode 21 formed over the entire surface of the counter substrate 20. In the present embodiment, the passivation films 91 and 92 have a relatively high conductivity by, for example, mixing a carbon material or the like. Each of the alignment films 16 and 22 is made of, for example, a transparent organic film such as a polyimide film.
[0030]
FIG. 4 shows an equivalent circuit of an element on the TFT substrate 10 constituting a pixel. As shown in FIG. 4, in the pixel region, a plurality of scanning lines 11a and a plurality of data lines 6a are wired so as to intersect with each other, and a pixel electrode is formed in a region defined by the scanning lines 11a and the data lines 6a. 9a are arranged in a matrix. Then, a TFT 30 is provided at each intersection of the scanning line 11a and the data line 6a, and the pixel electrode 9a is connected to the TFT 30.
[0031]
The TFT 30 is turned on by the ON signal of the scanning line 11a, whereby the image signal supplied to the data line 6a is supplied to the pixel electrode 9a. A voltage between the pixel electrode 9 a and the counter electrode 21 provided on the counter substrate 20 is applied to the liquid crystal 50. In addition, a storage capacitor 70 is provided in parallel with the pixel electrode 9a, and the storage capacitor 70 allows the voltage of the pixel electrode 9a to be held for a time that is, for example, three digits longer than the time during which the source voltage is applied. The storage capacitor 70 improves voltage holding characteristics and enables image display with a high contrast ratio.
[0032]
A plurality of pixel electrodes 9a are provided in a matrix on the TFT substrate 10, and data lines 6a and scanning lines 11a are provided along respective vertical and horizontal boundaries of the pixel electrodes 9a. The data line 6a has a laminated structure including an aluminum film and the like as described later, and the scanning line 11a is formed of, for example, a conductive polysilicon film. In addition, the scanning line 11a is electrically connected to a gate electrode 3a which is disposed to face a channel region 1a 'described later. That is, the gate electrode 3a connected to the scanning line 11a and the channel region 1a 'are opposed to each other where the scanning line 11a intersects with the data line 6a, thereby forming a pixel switching TFT 30.
[0033]
In the present embodiment, a passivation film 91 is formed between the pixel electrode 9a of the TFT substrate 10 and the alignment film 16, and a passivation film 92 is formed between the counter electrode 21 and the alignment film 22 of the counter substrate 20. ing. The passivation films 91 and 92 prevent the oxidation-reduction reaction between the electrodes 9a and 21 and the alignment films 16 and 22 and have sufficient conductivity and high charge mobility to form the alignment films 16 and 22. The ions at the interface are reduced by the effective movement of the charges to the electrodes 9a and 21.
[0034]
FIG. 5 is a schematic sectional view of a liquid crystal device focusing on one pixel. FIG. 5 is a cross-sectional view taken along the line AA ′ of FIG. 1, and FIG. 1 shows several film formation patterns.
[0035]
On the TFT substrate 10, in addition to the TFT 30 and the pixel electrode 9a, various configurations including these are provided in a laminated structure. As shown in FIG. 5, this laminated structure includes, in order from the bottom, a first layer (film formation layer) including the scanning line 11a, a second layer including the TFT 30 including the gate electrode 3a, and a third layer including the storage capacitor 70. A fourth layer including the data line 6a, a fifth layer including the shield layer 400 and the like, and a sixth layer (uppermost layer) including the pixel electrode 9a and the alignment film 16 and the like. A base insulating film 12 is provided between the first and second layers, a first interlayer insulating film 41 is provided between the second and third layers, and a second interlayer insulating film 42 is provided between the third and fourth layers. , A third interlayer insulating film 43 is provided between the fourth and fifth layers, and a fourth interlayer insulating film 44 is provided between the fifth and sixth layers, respectively. Has been prevented. In addition, the various insulating films 12, 41, 42, 43, and 44 are also provided with, for example, contact holes for electrically connecting the high-concentration source region 1d in the semiconductor layer 1a of the TFT 30 and the data line 6a. Has been. Hereinafter, each of these elements will be described in order from the bottom.
[0036]
The first layer includes, for example, a simple metal or an alloy including at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). A scanning line 11a made of metal silicide, polysilicide, a laminate thereof, or conductive polysilicon is provided. The scanning line 11a is patterned in a stripe shape in a plan view, and has a protruding portion along the data line 6a. The protruding portions extending from the adjacent scanning lines 11a are not connected to each other, and therefore, the scanning lines 11a are separated one by one.
[0037]
Thus, the scanning line 11a has a function of simultaneously controlling ON / OFF of the TFTs 30 existing in the same row. Further, since the scanning line 11a is formed so as to substantially fill a region where the pixel electrode 9a is not formed, the scanning line 11a also has a function of blocking light from entering the TFT 30 from below. This suppresses the occurrence of light leakage current in the semiconductor layer 1a of the TFT 30, and enables high-quality image display without flicker or the like.
[0038]
The TFT 30 including the gate electrode 3a is provided in the second layer. As shown in FIG. 5, the TFT 30 has an LDD (Lightly Doped Drain) structure, and includes a gate electrode 3a as described above, for example, a polysilicon film, and a channel formed by an electric field from the gate electrode 3a. A channel region 1a ′ of the semiconductor layer 1a to be formed, an insulating film 2 including a gate insulating film for insulating the gate electrode 3a from the semiconductor layer 1a, a low-concentration source region 1b and a low-concentration drain region 1c in the semiconductor layer 1a, and a high-concentration region A source region 1d and a high-concentration drain region 1e are provided.
[0039]
Then, a relay electrode 719 is formed on the second layer as the same film as the gate electrode 3a. The relay electrode 719 is formed in an island shape so as to be located substantially at the center of one side of each pixel electrode 9a when viewed in plan. Since the relay electrode 719 and the gate electrode 3a are formed as the same film, when the latter is made of, for example, a conductive polysilicon film, the former is also made of a conductive polysilicon film.
[0040]
The above-described TFT 30 preferably has an LDD structure as shown in FIG. 5, but may have an offset structure in which impurities are not implanted in the low-concentration source region 1b and the low-concentration drain region 1c. A self-aligned TFT in which impurities are implanted at a high concentration as a mask to form a high-concentration source region and a high-concentration drain region in a self-aligned manner may be used. Further, in the present embodiment, a single gate structure in which only one gate electrode of the pixel switching TFT 30 is disposed between the high-concentration source region 1d and the high-concentration drain region 1e has been described. Electrodes may be arranged. When a TFT is formed with a dual gate or triple gate or more as described above, a leak current at a junction between a channel and a source / drain region can be prevented, and a current in an off state can be reduced. Further, the semiconductor layer 1a constituting the TFT 30 may be a non-single-crystal layer or a single-crystal layer. For forming the single crystal layer, a known method such as a bonding method can be used. By using the semiconductor layer 1a as a single crystal layer, the performance of peripheral circuits in particular can be improved.
[0041]
Above the scanning line 11a and below the TFT 30, the underlying insulating film 12 made of, for example, a silicon oxide film is provided. The base insulating film 12 has a function of insulating the scanning lines 11a and the TFTs 30 and, furthermore, being formed on the entire surface of the TFT substrate 10 so that pixel switching due to roughness at the time of polishing the surface of the TFT substrate 10 and dirt remaining after washing is performed. A function of preventing a change in characteristics of the TFT 30 for use.
[0042]
In the base insulating film 12, grooves (contact holes) 12cv having the same width as the channel length of the semiconductor layer 1a extending along the data lines 6a to be described later are dug on both sides of the semiconductor layer 1a in plan view. Corresponding to the groove 12cv, the gate electrode 3a stacked thereabove includes a portion formed in a concave shape on the lower side. Further, since the gate electrode 3a is formed so as to fill the entire groove 12cv, a side wall 3b integrally formed with the gate electrode 3a is extended. I have. Thus, the semiconductor layer 1a of the TFT 30 is covered from the side as viewed in plan, and at least the incidence of light from this portion is suppressed.
[0043]
The side wall 3b is formed so as to fill the groove 12cv and to have the lower end in contact with the scanning line 11a. Therefore, the scanning line 11a and the gate electrode 3a in the same row have the same potential. Note that a structure in which another scanning line including the gate electrode 3a is formed so as to be parallel to the scanning line 11a may be employed. In this case, the scanning line 11a and the another scanning line have a redundant wiring structure. Thereby, for example, even when a part of the scanning line 11a has some defect and normal energization becomes impossible, another scanning line existing in the same row as the scanning line 11a is not used. As long as it is sound, the operation control of the TFT 30 can still be performed normally through it.
[0044]
The storage capacitor 70 is provided in the third layer. The storage capacitor 70 includes a lower electrode 71 serving as a pixel potential-side capacitor electrode connected to the high-concentration drain region 1 e and the pixel electrode 9 a of the TFT 30, and a capacitor electrode 300 serving as a fixed-potential-side capacitor electrode. It is formed by being arranged to face through. According to the storage capacitor 70, the potential holding characteristic of the pixel electrode 9a can be significantly improved. In addition, since the storage capacitor 70 is formed so as not to reach the light transmission region substantially corresponding to the formation region of the pixel electrode 9a (in other words, it is formed so as to fit within the light shielding region). The pixel aperture ratio of the entire electro-optical device is maintained relatively large, so that a brighter image can be displayed.
[0045]
More specifically, the lower electrode 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitance electrode. However, the lower electrode 71 may be formed of a single-layer film or a multilayer film containing a metal or an alloy. The lower electrode 71 has a function of relay connection between the pixel electrode 9a and the high-concentration drain region 1e of the TFT 30, in addition to a function as a pixel potential side capacitor electrode. This relay connection is performed via the relay electrode 719 as described later.
[0046]
The capacitance electrode 300 functions as a fixed potential side capacitance electrode of the storage capacitor 70. In order to set the capacitor electrode 300 to a fixed potential, the capacitor electrode 300 is electrically connected to a shield layer 400, which is set to a fixed potential and described later.
[0047]
The capacitor electrode 300 is formed in an island shape on the TFT substrate 10 so as to correspond to each pixel, and the lower electrode 71 is formed to have substantially the same shape as the capacitor electrode 300. . As a result, the storage capacitor 70 does not have a wasteful spread in a plan view, that is, does not lower the pixel aperture ratio, and can realize the maximum capacitance value under the circumstances. That is, the storage capacitor 70 has a smaller area and a larger capacitance value.
[0048]
As shown in FIG. 5, the dielectric film 75 is, for example, a relatively thin HTO (High Temperature oxide) film having a thickness of about 5 to 200 nm, a silicon oxide film such as an LTO (Low Temperature oxide) film, or a silicon nitride film. Consists of From the viewpoint of increasing the storage capacitance 70, the thinner the dielectric film 75 is, the better the reliability of the film can be obtained. The dielectric film 75 has a two-layer structure including a silicon oxide film 75a as a lower layer and a silicon nitride film 75b as an upper layer, as shown in FIG. The presence of the silicon nitride film 75b having a relatively large dielectric constant allows the capacitance value of the storage capacitor 70 to be increased, and the presence of the silicon oxide film 75a lowers the withstand voltage of the storage capacitor 70. I won't let you go. Thus, by forming the dielectric film 75 in a two-layer structure, it is possible to enjoy two opposing effects.
[0049]
Further, the presence of the silicon nitride film 75b makes it possible to prevent water from entering the TFT 30 before it occurs. Accordingly, the operation of the device can be performed for a relatively long time without causing a situation in which the threshold voltage of the TFT 30 increases. In this embodiment, the dielectric film 75 has a two-layer structure. However, the dielectric film 75 has a three-layer structure such as a silicon oxide film, a silicon nitride film, and a silicon oxide film, or more. May be configured to have a laminated structure.
[0050]
Above the TFT 30 or the gate electrode 3a and the relay electrode 719 described above and below the storage capacitor 70, for example, NSG (non-silicate glass), PSG (phosphosilicate glass), BSG (boron silicate glass), BPSG ( A silicate glass film such as boron phosphorus silicate glass, a silicon nitride film, a silicon oxide film, or the like, or a first interlayer insulating film 41 preferably made of NSG is formed. In the first interlayer insulating film 41, a contact hole 81 for electrically connecting the high-concentration source region 1d of the TFT 30 and a data line 6a described later is opened while penetrating a second interlayer insulating film 42 described later. There is a hole. In the first interlayer insulating film 41, a contact hole 83 for electrically connecting the high-concentration drain region 1e of the TFT 30 and the lower electrode 71 constituting the storage capacitor 70 is formed.
[0051]
Further, the first interlayer insulating film 41 is provided with a contact hole 881 for electrically connecting the lower electrode 71 as a pixel potential side capacitor electrode constituting the storage capacitor 70 and the relay electrode 719. . In addition, a contact hole 882 for electrically connecting the relay electrode 719 to a second relay electrode 6a2 described later is formed in the first interlayer insulating film 41 while penetrating the second interlayer insulating film 42 described later. Have been.
[0052]
As shown in FIG. 5, the contact hole 882 is formed in a region other than the storage capacitor 70, and the lower electrode 71 is drawn out to the upper layer via the contact hole 882 by bypassing the lower layer relay electrode 719 once. Therefore, even when the lower electrode 71 is connected to the upper pixel electrode 9a, it is not necessary to form the lower electrode 71 wider than the dielectric film 75 and the capacitor electrode 300. Therefore, the lower electrode 71, the dielectric film 75, and the capacitor electrode 300 can be simultaneously patterned in one etching process. This facilitates control of the etching rate of each of the lower electrode 71, the dielectric film 75, and the capacitor electrode 300, and can increase the degree of freedom in designing the thickness and the like.
[0053]
Further, since the dielectric film 75 is formed in the same shape as the lower electrode 71 and the capacitor electrode 300 and has no spread, when the semiconductor layer 1a of the TFT 30 is subjected to hydrogenation processing, hydrogen used for the processing is used. Can easily reach the semiconductor layer 1a through the opening around the storage capacitor 70.
[0054]
The first interlayer insulating film 41 may be baked at about 1000 ° C. to activate the ions implanted in the polysilicon film forming the semiconductor layer 1a and the gate electrode 3a.
[0055]
The fourth layer is provided with a data line 6a. The data line 6a is formed in a stripe shape so as to coincide with the direction in which the semiconductor layer 1a of the TFT 30 extends. As shown in FIG. 5, the data lines 6a are, in order from the lower layer, a layer made of aluminum (reference numeral 41A in FIG. 5), a layer made of titanium nitride (see reference numeral 41TN in FIG. 5), and a layer made of silicon nitride film (see FIG. 5). It is formed as a film having a three-layer structure denoted by reference numeral 401) in FIG. The silicon nitride film is patterned to have a slightly larger size so as to cover the underlying aluminum layer and titanium nitride layer. Since the data line 6a contains aluminum, which is a relatively low-resistance material, supply of image signals to the TFT 30 and the pixel electrode 9a can be realized without interruption. On the other hand, by forming a silicon nitride film having a relatively excellent effect of damping intrusion of moisture on the data line 6a, the moisture resistance of the TFT 30 can be improved, and the life of the TFT 30 can be prolonged. The silicon nitride film is preferably a plasma silicon nitride film.
[0056]
In the fourth layer, a relay layer 6a1 for a shield layer and a second relay electrode 6a2 are formed as the same film as the data line 6a. These are not formed so as to have a planar shape continuous with the data line 6a when viewed in a plan view, but are formed so as to be separated from each other in patterning. In other words, when focusing on the data line 6a, the relay layer 6a1 has a substantially quadrangular shape immediately to the right of the data line 6a, and has a substantially quadrilateral shape slightly larger than the relay layer 6a1 to the right of the shield layer. The second relay electrode 6a2 is formed. The shield layer relay layer 6a1 and the second relay electrode 6a2 are formed in the same process as the data line 6a, and have a three-layer structure of a layer made of aluminum, a layer made of titanium nitride, and a layer made of a plasma nitride film in order from the lower layer. It is formed as. The plasma nitride film is patterned to have a slightly larger size so as to cover the underlying aluminum layer and titanium nitride layer. The titanium nitride layer functions as a barrier metal for preventing penetration of etching of the contact holes 803 and 804 formed with respect to the shield layer relay layer 6a1 and the second relay electrode 6a2. In addition, by forming a plasma nitride film having a relatively excellent effect of blocking the intrusion of moisture on the relay layer 6a1 for the shield layer and the second relay electrode 6a2, it is possible to improve the moisture resistance of the TFT 30. A longer life can be achieved. Incidentally, a plasma silicon nitride film is desirable as the plasma nitride film.
[0057]
Above the storage capacitor 70 and below the data line 6a, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably, a plasma CVD method using TEOS gas The second interlayer insulating film 42 is formed. In the second interlayer insulating film 42, a contact hole 81 for electrically connecting the high concentration source region 1d of the TFT 30 and the data line 6a is opened, and the shield layer relay layer 6a1 and the storage capacitor 70 are formed. A contact hole 801 for electrically connecting the capacitor electrode 300 serving as the upper electrode is formed. Further, a contact hole 882 for electrically connecting the second relay electrode 6a2 and the relay electrode 719 is formed in the second interlayer insulating film.
[0058]
The shield layer 400 is formed on the fifth layer. The shield layer 400 is formed in a lattice shape so as to extend in the X direction and the Y direction in FIG. Particularly, a portion of the shield layer 400 extending in the Y direction in the drawing is formed so as to cover the data line 6a and to be wider than the data line 6a. In addition, the portion extending in the X direction in the drawing has a cutout near the center of one side of each pixel electrode 9a in order to secure a region for forming a third relay electrode 402 described later.
[0059]
Further, in FIG. 7, substantially triangular portions are provided at corners of intersections of the shield layers 400 extending in the X and Y directions so as to fill the corners. By providing the substantially triangular portion in the shield layer 400, light can be effectively shielded from the semiconductor layer 1a of the TFT 30. That is, light that is about to enter the semiconductor layer 1a obliquely from above is reflected or absorbed by this triangular portion, and does not reach the semiconductor layer 1a. Therefore, it is possible to display a high-quality image free from flicker or the like while suppressing the occurrence of light leakage current.
[0060]
The shield layer 400 extends from the image display area 10a in which the pixel electrode 9a is arranged to the periphery thereof, and is electrically connected to a constant potential source to have a fixed potential. Note that the constant potential source may be a constant potential source of a positive power supply or a negative power supply supplied to the data line driving circuit 101 described later, or a constant potential source supplied to the counter electrode 21 of the counter substrate 20.
[0061]
As described above, the capacitance formed between the data line 6a and the pixel electrode 9a is formed so as to cover the entire data line 6a (see FIG. 7). It is possible to eliminate the influence of the coupling. That is, it is possible to avoid a situation in which the potential of the pixel electrode 9a fluctuates in accordance with the energization of the data line 6a, which may cause display unevenness or the like along the data line 6a on an image. Can be reduced. Since the shield layer 400 is formed in a lattice shape, it is possible to suppress unnecessary capacitive coupling even at a portion where the scanning line 11a extends, without causing unnecessary capacitive coupling.
[0062]
In the fourth layer, a third relay electrode 402 as a relay layer is formed as the same film as the shield layer 400. The third relay electrode 402 has a function of relaying an electrical connection between the second relay electrode 6a2 and the pixel electrode 9a via a contact hole 89 described later. The shield layer 400 and the third relay electrode 402 are not formed continuously in a planar shape, but are formed so as to be separated on patterning.
[0063]
On the other hand, the above-mentioned shield layer 400 and third relay electrode 402 have a two-layer structure of a lower layer made of aluminum and an upper layer made of titanium nitride. In the third relay electrode 402, the lower layer made of aluminum is connected to the second relay electrode 6a2, and the upper layer made of titanium nitride is connected to the pixel electrode 9a made of ITO or the like. I have. When aluminum and ITO are directly connected, electrolytic corrosion occurs between the two, and a favorable electrical connection cannot be realized due to disconnection of aluminum or insulation due to formation of alumina. On the other hand, since the titanium nitride and the ITO are connected, a low contact resistance and a good connection can be obtained.
[0064]
As described above, since the electrical connection between the third relay electrode 402 and the pixel electrode 9a can be satisfactorily realized, the voltage application to the pixel electrode 9a or the potential holding characteristic of the pixel electrode 9a is maintained satisfactorily. It becomes possible.
[0065]
Further, since the shield layer 400 and the third relay electrode 402 include aluminum having relatively excellent light reflection performance and titanium nitride having relatively excellent light absorption performance, they can function as a light shielding layer. That is, according to these, it is possible to block the progress of the incident light (see FIG. 5) on the semiconductor layer 1a of the TFT 30 on the upper side. Note that such a light shielding function can be similarly applied to the above-described capacitance electrode 300 and data line 6a. The shield layer 400, the third relay electrode 402, the capacitor electrode 300, and the data line 6a form a part of a laminated structure built on the TFT substrate 10 and serve as an upper light-shielding film that blocks light from entering the TFT 30 from above. Function.
[0066]
Above the data line 6a and below the shield layer 400, a silicate glass film such as NSG, PSG, BSG, BPSG, etc., a silicon nitride film, a silicon oxide film, or the like, or preferably, a plasma CVD method using TEOS gas The third interlayer insulating film 43 is formed. In the third interlayer insulating film 43, a contact hole 803 for electrically connecting the shield layer 400 and the relay layer 6a1 for the shield layer, and a third relay electrode 402 and the second relay electrode 6a2 are electrically connected. The contact holes 804 for connecting to each other are opened.
[0067]
The second interlayer insulating film 42 may not be subjected to the above-described baking with respect to the first interlayer insulating film 41, so that the stress generated near the interface of the capacitor electrode 300 may be reduced.
[0068]
As described above, the pixel electrodes 9a are formed in a matrix on the sixth layer. An alignment film 16 is formed on the pixel electrode 9a with a passivation film 91 patterned so as not to extend over the adjacent pixel electrode 9a. The passivation film 91 has sufficient conductivity. Under the pixel electrode 9a, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably, a plasma film formed by a plasma CVD method using a TEOS gas. A fourth interlayer insulating film 44 made of TEOS is formed. A contact hole 89 for electrically connecting the pixel electrode 9a and the third relay electrode 402 is formed in the fourth interlayer insulating film 44.
[0069]
The surfaces of the third and fourth interlayer insulating films 43 and 44 are flattened by a CMP (Chemical Mechanical Polishing) process or the like. Poor alignment of the liquid crystal layer 50 due to steps due to various wirings, elements, etc. existing below the planarized interlayer insulating films 43, 44 is reduced. However, instead of or in addition to performing the planarization process on the third and fourth interlayer insulating films 43 and 44 in this manner, the TFT substrate 10, the base insulating film 12, the first interlayer insulating film 41, and the second interlayer insulating film 41 A flattening process may be performed by digging a groove in at least one of the insulating film 42 and the third interlayer insulating film 43 and burying the wiring such as the data line 6a or the TFT 30 or the like.
[0070]
Further, the storage capacitor 70 has a three-layer structure of a pixel potential side capacitance electrode, a dielectric film, and a fixed potential side capacitance electrode in order from the bottom, but may have a structure opposite thereto. .
[0071]
On the other hand, as shown in FIGS. 2 and 3, the opposing substrate 20 is provided with a light-shielding film 53 as a frame for dividing a display area. As described above, a transparent conductive film such as ITO is formed on the entire surface of the counter substrate 20 as the counter electrode 21, and a passivation film 92 having sufficient conductivity is interposed on the entire surface of the counter electrode 21. A polyimide-based alignment film 22 is formed. The alignment film 22 is rubbed in a predetermined direction so as to give a predetermined pretilt angle to the liquid crystal molecules.
[0072]
The specific resistance of the passivation films 91 and 92 is reduced by, for example, adjusting the gas flow rate during film formation, implanting impurities, and introducing carbon fine particles.
[0073]
In a region outside the light-shielding film 53, a sealing material 52 for enclosing liquid crystal is formed between the TFT substrate 10 and the counter substrate 20. The sealing material 52 is disposed so as to substantially match the contour shape of the counter substrate 20, and fixes the TFT substrate 10 and the counter substrate 20 to each other. The sealing material 52 is missing at a part of one side of the TFT substrate 10, and a liquid crystal injection port 108 for injecting the liquid crystal 50 is formed in a gap between the bonded TFT substrate 10 and the counter substrate 20. You. After the liquid crystal is injected from the liquid crystal injection port 108, the liquid crystal injection port 108 is sealed with a sealing material 109.
[0074]
A data line driving circuit 101 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and an external connection terminal 102 for connection to an external circuit are provided in a region outside the sealing material 52. Are provided along one side of the TFT substrate 10. Along the two sides adjacent to the one side, a scanning line driving circuit 104 for driving the gate electrode 3a by supplying a scanning signal to the scanning line 11a and the gate electrode 3a at a predetermined timing is provided. The scanning line driving circuit 104 is formed on the TFT substrate 10 at a position facing the light shielding film 53 inside the sealing material 52. Further, on the TFT substrate 10, a wiring 105 for connecting the data line driving circuit 101, the scanning line driving circuit 104, the external connection terminal 102, and the upper / lower conduction terminal 107 is provided facing three sides of the light shielding film 53. I have.
[0075]
The upper and lower conductive terminals 107 are formed on the four TFT substrates 10 at the corners of the sealing material 52. A vertical conductive material 106 is provided between the TFT substrate 10 and the counter substrate 20, the lower end of which contacts the upper and lower conductive terminals 107 and the upper end of which contacts the counter electrode 21. Electrical continuity is established between 10 and counter substrate 20.
[0076]
The present invention is not limited to the three-dimensional and two-dimensional layout of each component, but may be various other forms.
[0077]
As described above, the pixel electrode 9a and the counter electrode 21 are completely covered with the passivation films 91 and 92, respectively, and the oxidation-reduction reaction between these electrodes 9a and 21 and the alignment films 16 and 22 is prevented. Deterioration of the alignment film is suppressed.
[0078]
The passivation films 91 and 92 have sufficiently high conductivity, and the mobility of the charges in the passivation films 91 and 92 is sufficiently large. Accordingly, the electric charges relatively easily flow to the pixel electrode 9a and the counter electrode 21 via the passivation films 91 and 92, respectively, and the ions near the surfaces of the alignment films 16 and 22 are reduced. As a result, as a result, ions are less likely to stay at the interface between the alignment films 16 and 22, the DC component is prevented from being applied to the liquid crystal, and the burn-in phenomenon can be prevented. Note that the passivation film 91 is patterned so as not to straddle the adjacent pixel electrodes 9a. Even when the conductivity of the passivation film 91 is sufficiently high, the adjacent pixel electrodes 9a do not short-circuit.
[0079]
The present invention is not limited to the three-dimensional and two-dimensional layout of each component, but may be various other forms.
[0080]
Next, a method of manufacturing the element substrate of the liquid crystal device of FIG. 1 will be described with reference to FIG.
[0081]
First, a TFT substrate 10 such as a quartz substrate, glass, or silicon substrate is prepared (Step S11 in FIG. 10). Here, annealing is preferably performed at a high temperature of about 900 to 1300 ° C. in an inert gas atmosphere such as N (nitrogen), and pre-processing is performed so that distortion generated in the TFT substrate 10 in a high-temperature process performed later is reduced. Keep it.
[0082]
Next, a metal alloy film such as a metal such as Ti, Cr, W, Ta, or Mo or a metal silicide is formed on the entire surface of the TFT substrate 10 thus processed by sputtering to a thickness of about 100 to 500 nm, preferably. Is deposited to a thickness of 200 nm. Then, the metal alloy film is patterned by photolithography and etching to form the scanning lines 11a having a planar shape of a stripe (Step S12).
[0083]
Next, a TEOS (tetra-ethyl-ortho-silicate) gas, a TEB (tetra-ethyl-borate) gas, and a TMOP (tetra-methyl-oxy) gas are formed on the scanning line 11a by, for example, normal pressure or reduced pressure CVD. A silicate glass film such as NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), a silicon nitride film or a silicon oxide film using a fossate (gas) gas or the like. Then, a base insulating film 12 made of, for example, is formed (Step S13). The thickness of the base insulating film 12 is, for example, about 500 to 2000 nm.
[0084]
In the next step S14, the semiconductor layer 1a is formed. That is, first, under a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C., a low pressure CVD using a monosilane gas, a disilane gas or the like at a flow rate of about 400 to 600 cc / min on the base insulating film 12 (for example, An amorphous silicon film is formed by CVD under a pressure of about 20 to 40 Pa). Next, a p-Si (polysilicon) film having a thickness of about 50 to 200 nm is formed by performing a heat treatment in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably for 4 to 6 hours. , Preferably solid phase growth to a thickness of about 100 nm. As a method for solid phase growth, annealing using RTA or laser annealing using an excimer laser or the like may be used. At this time, depending on whether the pixel switching TFT 30 is an n-channel type or a p-channel type, a dopant of a group V element or a group III element may be slightly doped by ion implantation or the like. Then, a semiconductor layer 1a having a predetermined pattern is formed by photolithography and etching.
[0085]
Next, in step S15, the semiconductor layer 1a constituting the TFT 30 is thermally oxidized at a temperature of about 900 to 1300 ° C., preferably at a temperature of about 1000 ° C. to form a lower gate insulating film. Subsequently, an upper gate insulating film is formed by a low-pressure CVD method or the like, thereby forming an insulating film 2 (including a gate insulating film) made of a single or multilayer high-temperature silicon oxide film (HTO film) or a silicon nitride film. . As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating film 2 has a thickness of about 20 to 150 nm, preferably about 30 to 100 nm. It will be thick.
[0086]
Next, in order to control the threshold voltage Vth of the pixel switching TFT 30, a predetermined amount of a dopant such as boron is doped into the n-channel region or the p-channel region of the semiconductor layer 1a by ion implantation or the like. I do.
[0087]
Next, a groove 12cv communicating with the scanning line 11a is formed in the base insulating film 12. The groove 12cv is formed by dry etching such as reactive ion etching and reactive ion beam etching.
[0088]
Next, a polysilicon film is deposited by a low pressure CVD method or the like, and phosphorus (P) is thermally diffused to make the polysilicon film conductive. Instead of the thermal diffusion, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The thickness of the polysilicon film is about 100 to 500 nm, preferably about 350 nm. Then, a gate electrode 3a having a predetermined pattern including the gate electrode portion of the TFT 30 is formed by photolithography and etching (step S16). When the gate electrode 3a is formed, the side wall 3b extending therefrom is also formed at the same time. The side wall 3b is formed by depositing the above-described polysilicon film also on the inside of the trench 12cv. At this time, since the bottom of the groove 12cv is in contact with the scanning line 11a, the side wall 3b and the scanning line 11a are electrically connected. Further, when patterning the gate electrode 3a, a relay electrode 719 is also formed at the same time.
[0089]
Next, a low-concentration source region 1b and a low-concentration drain region 1c, and a high-concentration source region 1d and a high-concentration drain region 1e are formed on the semiconductor layer 1a.
[0090]
Here, a case where the TFT 30 is an n-channel TFT having an LDD structure will be described. Specifically, first, in order to form the low-concentration source region 1b and the low-concentration drain region 1c, the gate electrode 3a is used as a mask. Dopan of a group V element such as P is doped at a low concentration (for example, P ions at a dose of 1 to 3 × 10 ¹³ cm ₂ ). Thus, the semiconductor layer 1a below the gate electrode 3a becomes a channel region 1a '. At this time, the low concentration source region 1b and the low concentration drain region 1c are formed in a self-aligned manner by the gate electrode 3a serving as a mask. Next, a resist layer having a plane pattern wider than the gate electrode 3a is formed on the gate electrode 3a in order to form the high-concentration source region 1d and the high-concentration drain region 1e. Thereafter, a dopant of a group V element such as P is doped at a high concentration (for example, P ions are doped at a dose of 1 to 3 × 10 ¹⁵ / cm ₂ ).
[0091]
Note that doping may not be performed in two stages of low concentration and high concentration. For example, a TFT having an offset structure may be used without performing low-concentration doping, and a self-aligned TFT may be formed using a gate electrode 3a (gate electrode) as a mask and an ion implantation technique using P ions, B ions, or the like. Good. The resistance of the gate electrode 3a is further reduced by the doping of the impurity.
[0092]
Next, a silicate glass film such as NSG, PSG, BSG, BPSG, or the like, a silicon nitride film, or an oxide is formed on the gate electrode 3a by, for example, normal pressure or reduced pressure CVD using TEOS gas, TEB gas, TMOP gas, or the like. A first interlayer insulating film 41 made of a silicon film is formed (Step S17). The thickness of the first interlayer insulating film 41 is, for example, about 500 to 2000 nm. Here, preferably, annealing is performed at a high temperature of about 800 ° C. to improve the film quality of the first interlayer insulating film 41.
[0093]
Next, in step S18, the contact holes 83 and 881 are formed by dry etching such as reactive ion etching and reactive ion beam etching on the first interlayer insulating film 41. At this time, the former is formed so as to communicate with the high-concentration drain region 1e of the semiconductor layer 1a, and the latter is formed so as to communicate with the relay electrode 719.
[0094]
Next, in step S19, a metal film such as Pt or a polysilicon film is formed on the first interlayer insulating film 41 to a thickness of about 100 to 500 nm by low-pressure CVD or sputtering, and a predetermined pattern is formed. The metal film of the lower electrode 71 is formed. In this case, the formation of the metal film is performed so that both the contact hole 83 and the contact hole 881 are buried, so that the high-concentration drain region 1e, the relay electrode 719, and the lower electrode 71 are electrically connected. Can be
[0095]
Next, a dielectric film 75 is formed on the lower electrode 71. This dielectric film 75 can be formed by various known techniques generally used for forming a TFT gate insulating film, similarly to the case of the insulating film 2. The silicon oxide film 75a is formed by the above-described thermal oxidation or the CVD method, and thereafter, the silicon nitride film 75b is formed by the low pressure CVD method or the like. As the dielectric film 75 becomes thinner, the storage capacitance 70 becomes larger. Therefore, it is advantageous to form the dielectric film 75 into a very thin insulating film having a thickness of 50 nm or less on condition that defects such as film breakage do not occur. It is. Next, a metal film such as a polysilicon film or AL (aluminum) is formed on the dielectric film 75 to a thickness of about 100 to 500 nm by low-pressure CVD or sputtering, and the metal film of the capacitor electrode 300 is formed. To form
[0096]
Next, the film of the lower electrode 71, the dielectric film 75 and the capacitor electrode 300 is patterned at a time to form the lower electrode 71, the dielectric film 75 and the capacitor electrode 300, and the storage capacitor 70 is completed.
[0097]
Next, for example, a silicate glass film of NSG, PSG, BSG, BPSG, or the like, a silicon nitride film, a silicon oxide film, or the like is formed by normal pressure or reduced pressure CVD using TEOS gas or the like, preferably by plasma CVD. The two-layer insulating film 42 is formed (Step S30). When aluminum is used for the capacitor electrode 300, it is necessary to form a film at a low temperature by plasma CVD. The thickness of the second interlayer insulating film 42 is, for example, about 500 to 1500 nm. Next, in step S21, contact holes 81, 801 and 882 are formed by dry etching such as reactive ion etching and reactive ion beam etching on the second interlayer insulating film. At this time, the contact hole 81 is formed so as to communicate with the high-concentration source region 1d of the semiconductor layer 1a, the contact hole 801 is formed so as to communicate with the capacitor electrode 300, and the contact hole 882 is formed so as to communicate with the relay electrode 719. You.
[0098]
Next, in step S22, a low-resistance metal such as aluminum or a metal silicide having a light-shielding property or a metal silicide is used as a metal film on the entire surface of the second interlayer insulating film 42 by sputtering or the like, and a thickness of about 100 to 500 nm is preferable. Deposits at about 300 nm. Then, a data line 6a having a predetermined pattern is formed by photolithography and etching. At this time, at the time of the patterning, the shield layer relay layer 6a1 and the second relay layer 6a2 are also formed at the same time. The relay layer 6a1 for the shield layer is formed so as to cover the contact hole 801 and the second relay layer 6a2 is formed so as to cover the contact hole 882.
[0099]
Next, after a film made of titanium nitride is formed on the entire upper layer by a plasma CVD method or the like, a patterning process is performed so that this film remains only on the data line 6a. However, the layer made of the titanium nitride may be formed so as to remain also on the shield layer relay layer 6a1 and the second relay layer 6a2, and may be formed so as to remain on the entire surface of the TFT substrate 10 in some cases. Is also good. Alternatively, a film may be formed at the same time as the aluminum film is formed, and may be etched at a time.
[0100]
Next, a silicate such as NSG, PSG, BSG, BPSG, or the like is formed so as to cover the data line 6a or the like by a normal pressure or reduced pressure CVD method using TEOS gas or the like, preferably by a plasma CVD method capable of forming a film at a low temperature. A third interlayer insulating film 43 made of a glass film, a silicon nitride film, a silicon oxide film, or the like is formed (Step S23). The thickness of the third interlayer insulating film 43 is, for example, about 500 to 3500 nm.
[0101]
Next, in step S24, as shown in FIG. 5, the third interlayer insulating film 43 is flattened using, for example, CMP.
[0102]
Next, in step S25, contact holes 803 and 804 are formed by dry etching such as reactive ion etching and reactive ion beam etching on the third interlayer insulating film 43. At this time, the contact hole 803 is formed so as to communicate with the relay layer 6a1 for the shield layer, and the contact hole 804 is formed so as to communicate with the second relay layer 6a2.
[0103]
Next, in step S26, a metal film of the shield layer 400 is formed on the third interlayer insulating film 43 by a sputtering method, a plasma CVD method, or the like. Here, first, a lower layer film is formed directly on the third interlayer insulating film 43 using a low-resistance material such as aluminum, and then, on the lower layer film, for example, titanium nitride or another pixel electrode 9a described later. The upper layer film is formed using ITO and a material that does not cause electrolytic corrosion, and finally, the lower layer film and the upper layer film are both patterned to form the shield layer 400 having a two-layer structure. At this time, the third relay electrode 402 is also formed together with the shield layer 400.
[0104]
Next, a fourth interlayer insulating film 44 made of a silicate glass film such as NSG, PSG, BSG, BPSG, or the like, a silicon nitride film, a silicon oxide film, or the like is formed by, for example, normal pressure or reduced pressure CVD using TEOS gas or the like. (Step S27). The thickness of the fourth interlayer insulating film 44 is, for example, about 500 to 1500 nm.
[0105]
Next, in step S28, as shown in FIG. 5, the fourth interlayer insulating film 44 is planarized using, for example, CMP. Next, a contact hole 89 is formed by dry etching such as reactive ion etching or reactive ion beam etching on the fourth interlayer insulating film 44 (step S29). At this time, the contact hole 89 is formed so as to communicate with the third relay electrode 402.
[0106]
Next, a transparent conductive film such as an ITO film is deposited on the fourth interlayer insulating film 44 by sputtering or the like to a thickness of about 50 to 200 nm. Then, the pixel electrode 9a is formed by photolithography and etching (Step S20). When the electro-optical device is used as a reflection type, the pixel electrode 9a may be formed of an opaque material having a high reflectance such as AL.
[0107]
Next, in the present embodiment, in step S31, a passivation film 91 is formed on the pixel electrode 9a by an evaporation method, a sputtering method, or the like. For example, when forming by a vapor deposition method, the TFT substrate 10 on which the pixel electrode 9a is formed is carried into a vapor deposition device. Next, a conductive material such as carbon is used as an evaporation source, and the thickness of the deposited film is controlled by monitoring the thickness of the deposited film using a film thickness sensor or the like, or by controlling the applied voltage of the evaporation source over time, A passivation film having a predetermined thickness is formed. In this embodiment mode, the resistance of the passivation film is sufficiently reduced by sufficiently mixing the conductive material.
[0108]
Next, the formed passivation film is patterned by photolithography and etching so as to cover each pixel electrode 9a without straddling the adjacent pixel electrode 9a. Thus, a passivation film 91 covering each of the pixel electrodes 9a is formed.
[0109]
On the other hand, as the counter substrate 20, a glass substrate or the like is first prepared, and a light-shielding film 53 as a frame is formed by, for example, sputtering metal chromium and then performing photolithography and etching. The light-shielding film 53 does not need to be conductive, and may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist, in addition to a metal material such as Cr, Ni, or AL.
[0110]
Next, an opposing electrode 21 is formed by depositing a transparent conductive film such as ITO to a thickness of about 50 to 200 nm on the entire surface of the opposing substrate 20 by sputtering or the like. Next, in the present embodiment, a passivation film 92 is formed on the counter electrode 21 by an evaporation method, a sputtering method, or the like. That is, the counter substrate 20 on which the counter electrode 21 is formed is carried into the vapor deposition apparatus, and the thickness of the vapor deposition film is monitored by a film thickness sensor or the like using a conductive material such as carbon as an evaporation source, or the evaporation source is pulled. The thickness of the deposited film is controlled by, for example, controlling the applied voltage over time to form a passivation film 92 having a predetermined thickness. The resistance of the passivation film 92 is sufficiently reduced by sufficiently mixing a conductive material.
[0111]
It is clear that the passivation films 91 and 92 may be formed by sputtering or the like. In this case, the flow rate of gas (O2, N2, etc.) at the time of sputtering is adjusted, and a conductive material such as carbon is introduced. Thereby, the resistance of the passivation films 91 and 92 is sufficiently reduced. Otherwise, the resistance can be reduced by impurity implantation.
[0112]
Next, a coating liquid for a polyimide-based alignment film is applied on the passivation film 91 of the TFT substrate 10 and then subjected to a rubbing process in a predetermined direction so as to have a predetermined pretilt angle, and the like. Is formed.
[0113]
On the other hand, a coating liquid for a polyimide-based alignment film is applied to the entire surface of the counter electrode 21 of the counter substrate 20, and then a rubbing process is performed in a predetermined direction so as to have a predetermined pretilt angle and the like. 22 are formed.
[0114]
Then, as shown in FIGS. 2 and 3, the TFT substrate 10 on which each layer is formed and the opposing substrate 20 form the sealing material 52 along, for example, four sides of the opposing substrate 20 and The upper and lower conductive members 106 are formed at the corners, and the alignment films 16 and 22 are bonded to each other by the sealant 52 so as to face each other. As a result, the upper and lower conductive material 106 contacts the upper and lower conductive terminals 107 of the TFT substrate 10 at the lower end, and contacts the counter electrode 21 of the counter substrate 20 at the upper end.
[0115]
Then, for example, a liquid crystal obtained by mixing a plurality of types of nematic liquid crystals is sucked into a space between the two substrates by vacuum suction or the like, and a liquid crystal layer 50 having a predetermined thickness is formed.
[0116]
The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like, and is cured by ultraviolet light, heating, or the like in order to bond the two substrates together. In addition, if the liquid crystal device according to the present embodiment is applied to a liquid crystal device that is small and performs enlarged display such as a projector, the distance between the two substrates (the gap between the substrates) ) Is set to a predetermined value, and a cap material (spacer) such as glass fiber or glass beads is sprayed. Alternatively, such a gap material may be included in the liquid crystal layer 50 if the liquid crystal device is applied to a liquid crystal device that performs large-size and equal-size display such as a liquid crystal display or a liquid crystal television.
[0117]
If the delay of the scanning signal supplied to the scanning line 11a and the gate electrode 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area 10a.
[0118]
Further, on the TFT substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, etc., a sampling circuit for applying an image signal to a plurality of data lines 6a at a predetermined timing, a plurality of data lines 6a A precharge circuit for supplying a precharge signal of a predetermined voltage level prior to the image signal, an inspection circuit for inspecting the quality, defects, and the like of the electro-optical device during manufacturing or shipping. Good.
[0119]
In the above-described embodiment, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT substrate 10, for example, a driving LSI mounted on a TAB (Tape Automated Bonding) substrate is provided with a TFT substrate. The connection may be made electrically and mechanically via an anisotropic conductive film provided on the periphery of the device 10. For example, a TN (Twisted Nematic) mode, a VA (Vertically Aligned) mode, and a PDLC (Polymer Dispersed Liquid Crystal) are provided on the side of the opposite substrate 20 where the projected light is incident and on the side where the emitted light of the TFT substrate 10 is emitted, respectively. A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a mode and a normally white mode / normally black mode.
[0120]
Further, in the above embodiment, the example of the substrate for the liquid crystal device has been described. However, it is apparent that the present invention can be applied to a semiconductor substrate and the like.
[0121]
As described above, in this embodiment, since the resistance of the passivation films 91 and 92 is sufficiently reduced, the mobility of charges in the passivation films 91 and 92 is high. As a result, the ions at the interface between the alignment films 16 and 22 are reduced because the electric charges relatively easily flow to the pixel electrode 9a or the counter electrode 21 through the passivation films 91 and 92. Therefore, even if the ions are likely to be adsorbed on the alignment films 16 and 22 due to the inversion drive or the unevenness of the alignment film surface, the ions can be effectively reduced. By preventing the ions from staying, it is possible to prevent a DC component from being applied to the liquid crystal. This prevents the burn-in phenomenon from occurring.
[0122]
If the conditions under which ions tend to stay on the counter substrate side and the TFT substrate side are different, the resistance (charge mobility) between the passivation film formed on the counter substrate side and the passivation film formed on the TFT substrate side is determined. By making them different from each other, it is also possible to prevent stagnation of ions.
[0123]
FIG. 7 is a plan view of a TFT substrate (element substrate) constituting a liquid crystal device, together with components formed thereon, viewed from a counter substrate side according to a second embodiment of the present invention. 7, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.
[0124]
In the first embodiment, by sufficiently lowering the resistance of the passivation film between the electrode and the alignment film, the charge mobility is improved and ions are prevented from staying at the alignment film interface. In this case, it is necessary to pattern the passivation film 91 formed on the pixel electrode 9a on the TFT substrate 10 so as not to short-circuit the pixel electrodes 9a. However, when the resistance value of the passivation film for short-circuiting the pixel electrodes is appropriately set, it is not always necessary to pattern the passivation film between the pixel electrode and the alignment film. The present embodiment is applied to this case.
[0125]
FIG. 7 corresponds to FIG. 3. On the TFT substrate 10 side, a passivation film 111 is formed on the entire surface of the pixel electrode 9a and the fourth interlayer insulating film 44 (see FIG. 5). On the counter substrate 20 side, a passivation film 112 is formed on the entire surface of the counter electrode 21.
[0126]
The passivation film 111 is formed by an evaporation method, a sputtering method, or the like. For example, when the passivation film 111 is formed by a vapor deposition method, a passivation film 111 having a predetermined resistance value is formed by using a conductive material such as carbon as an evaporation source and controlling the applied voltage of the evaporation source over time. In the present embodiment, the resistance value of the passivation film is set to 10 ¹¹ Ω or more. The passivation film 112 on the counter substrate 20 side is formed in the same manner.
[0127]
When the passivation films 111 and 112 are formed by a sputtering method, sputtering conditions for the flow rate of gas (O2, N2, etc.) at the time of sputtering are appropriately set, and a conductive material such as carbon is introduced. Further, since the resistance value of the passivation film 111 is set to 10 ¹¹ Ω or more, even when the passivation film 111 contacts the adjacent pixel electrodes 9a, a short circuit between the pixel electrodes 9a does not occur.
[0128]
In addition, since the resistance of the passivation films 111 and 112 is reduced so long as the pixel electrodes 9a are not short-circuited, charge mobility can be improved and ions can be prevented from staying at the interface of the alignment film. .
[0129]
As described above, also in the present embodiment, the same effect as that of the first embodiment can be obtained. Further, in the present embodiment, it is not necessary to pattern the passivation film 111, and the manufacturing process can be simplified.
[0130]
Also in this embodiment, the resistance values of the passivation film between the pixel electrode on the TFT substrate side and the alignment film and the passivation film between the counter electrode on the counter substrate side and the alignment film are set to different values. Obviously, it may be.
[0131]
(Electronics)
Next, an overall configuration, particularly an optical configuration, of an embodiment of a projection type color display device as an example of an electronic apparatus using the electro-optical device described above in detail as a light valve will be described. FIG. 8 is an explanatory diagram of the projection type color display device.
[0132]
8, a liquid crystal projector 1100, which is an example of a projection type color display device in the present embodiment, prepares three liquid crystal modules each including a liquid crystal device in which a driving circuit is mounted on a TFT array substrate, and each of the light bulbs 100R for RGB. , 100G and 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, three mirrors 1106 and two dichroic mirrors 1108 emit light components R, G and R corresponding to the three primary colors RGB. B, and are led to light valves 100R, 100G, and 100B corresponding to each color. In this case, in particular, the B light is guided through a relay lens system 1121 including an entrance lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are combined again by the dichroic prism 1112, and then projected as a color image on the screen 1120 via the projection lens 1114.
[0133]
The present invention is not limited to the above-described embodiment, and can be appropriately changed within the scope of the invention or the idea that can be read from the entirety of the claims and the specification, and an electro-optical device with such a change. Are also included in the technical scope of the present invention.
[0134]
The present invention is not limited to a TFT liquid crystal device, but is also applicable to a TFD liquid crystal device or a passive liquid crystal device.
[Brief description of the drawings]
FIG. 1 is a plan view showing a liquid crystal device according to a first embodiment of the present invention.
FIG. 2 is a plan view of a TFT substrate (element substrate) constituting the liquid crystal device together with components formed thereon as viewed from the counter substrate side.
FIG. 3 is a cross-sectional view showing the liquid crystal device after the assembly step of bonding a liquid crystal by bonding a TFT substrate and a counter substrate together, cut along a line HH ′ in FIG. 2;
FIG. 4 is an equivalent circuit diagram of various elements, wiring, and the like in a plurality of pixels forming a pixel region of a liquid crystal device.
FIG. 5 is a cross-sectional view illustrating a pixel structure of a liquid crystal device in detail.
FIG. 6 is a flowchart showing a method of manufacturing the element substrate of the liquid crystal device of FIG.
FIG. 7 is a plan view showing a second embodiment of the present invention.
FIG. 8 is an explanatory diagram of a projection type color display device.
[Explanation of symbols]
10: TFT substrate, 20: counter substrate, 9a: pixel electrode, 16, 22: alignment film, 91, 92: passivation film.

Claims (6)

A first electrode formed on the first transparent substrate out of the first and second transparent substrates which are disposed to face each other and in which liquid crystal is sealed;
A second electrode formed on the second transparent substrate;
A first passivation film formed on the first electrode;
A second passivation film formed on the second electrode;
A first alignment film formed on the first passivation film;
A second alignment film formed on the second passivation film,
At least one of the first passivation film and the second passivation film contains a conductive material, and the passivation film containing the conductive material has a specific resistance of 10 ⁶ to 10 ¹⁴ [Ω · cm]. Liquid crystal device. The first electrode is a pixel electrode provided on a first transparent substrate corresponding to pixels arranged in a matrix,
The second electrode is a common electrode provided on the entire surface of the second transparent substrate,
The liquid crystal device according to claim 1, wherein the second passivation film has a specific resistance lower than that of the first passivation film. The first electrode is a pixel electrode provided on a first transparent substrate corresponding to pixels arranged in a matrix,
The second electrode is a common electrode provided on the second transparent substrate,
The liquid crystal device according to claim 1, wherein the first passivation film is patterned corresponding to each pixel electrode without straddling a plurality of adjacent pixel electrodes. 4. The liquid crystal device according to claim 3, wherein the first and second passivation films have a specific resistance smaller than 10 ¹¹ [Ω · cm]. 5. Forming a first electrode on the first transparent substrate of the first and second transparent substrates which are arranged to face each other and in which liquid crystal is sealed;
Forming a second electrode on the second transparent substrate;
Forming a first passivation film on the first electrode;
Forming a second passivation film on the second electrode;
Forming a first alignment film on the first passivation film;
Forming a second alignment film on the second passivation film,
At least one of the first passivation film and the second passivation film contains a conductive material, and the passivation film containing the conductive material has a specific resistance of 10 ⁶ to 10 ¹⁴ [Ω · cm]. Of manufacturing a liquid crystal device. An electronic apparatus, comprising: the liquid crystal device according to claim 1.

Images