JP2004191930A - Electrooptical device and method of manufacturing the same, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make suitably realizable electric connection of a pixel potential capacitor electrode constructing a storage capacitor, respectively with a TFT (thin film transistor) and with a pixel electrode in an electrooptical apparatus and to miniaturize it and to make it high definition by having a suitable stacked layer structure including a storage capacitor. <P>SOLUTION: The electrooptical apparatus is equipped with the TFT (30) on a substrate (10), and a storage capacitor (70) and a pixel electrode (9a) on the TFT. Further the electrooptical device is equipped with an intermediary electrode (719) as a film identical to a scanning line (3a) including a gate electrode of the TFT(30). The junction electrode and a lower electrode (71) functioning as the pixel potential capacitor electrode of the storage capacitor are electrically connected via a contact hole (881) and the junction electrode and the pixel electrode are electrically connected via a contact hole (882) and so on. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention belongs to the technical field of an electro-optical device such as a liquid crystal device and an electronic apparatus including the electro-optical device. The present invention also belongs to the technical fields such as electrophoresis devices such as electronic paper, EL (electroluminescence) devices, and devices using electron-emitting devices (Field Emission Display and Surface-Conduction Electron-Emitter Display).

  Conventionally, an electro-optical device such as a liquid crystal device in which an image can be displayed by interposing an electro-optical material such as a liquid crystal between a pair of substrates and transmitting light so as to penetrate them is known. I have. Here, “displaying an image” refers to, for example, changing the state of an electro-optical material for each pixel, thereby changing the light transmittance, and making light having different gradations visible for each pixel. Is achieved.

  Such an electro-optical device includes, on one of the pair of substrates, pixel electrodes arranged in a matrix, scanning lines and data lines provided so as to sew between the pixel electrodes, and pixel switching. A device that can be driven in an active matrix by providing a TFT (Thin Film Transistor) or the like as an element for use is provided. In the electro-optical device capable of active matrix driving, the TFT is provided between the pixel electrode and the data line and controls conduction between the two. The TFT is electrically connected to a scanning line and a data line. According to this, ON / OFF of the TFT is controlled through the scanning line, and when the TFT is ON, the image signal supplied through the data line is applied to the pixel electrode, that is, light transmission is performed for each pixel. It is possible to change the rate.

  In the electro-optical device as described above, the various configurations as described above are formed on one substrate, but when these are developed in a plane, a large area is required, and the pixel aperture ratio, that is, In addition, there is a possibility that the ratio of the region through which light should pass through to the entire region of the substrate may be reduced. Therefore, in the related art, a method of three-dimensionally configuring the above-described various elements, that is, a method of laminating and configuring the various elements via an interlayer insulating film has been adopted. More specifically, a TFT and a scanning line having a function as a gate electrode film of the TFT are first formed on a substrate, a data line is formed thereon, and a pixel electrode is formed thereon. In this way, the size of the device can be reduced, and the aperture ratio of the pixels can be improved by appropriately setting the arrangement of various elements.

However, the conventional electro-optical device has the following problems.
The problem was that the life of the TFT was relatively short. This is because when moisture enters a semiconductor layer or a gate insulating film constituting a TFT, water molecules diffuse into an interface between the gate insulating film and the semiconductor layer to generate positive charges, and the threshold voltage is relatively short. This is because Vth rises. Such a phenomenon is more appropriate in a P-channel TFT. When the TFT has such a relatively short life, the entire electro-optical device is naturally affected, and a deterioration in image quality is observed from a relatively early stage, and the device itself eventually stops operating. There is even fear.

  The present invention has been made in view of the above problems, and has as its object to provide an electro-optical device capable of displaying a higher quality image by extending the life of a TFT. Another object of the present invention is to provide an electronic apparatus including such an electro-optical device.

  In order to solve the above problem, an electro-optical device according to the present invention has a data line extending in a first direction on a substrate, a scanning line extending in a second direction intersecting the data line, and the data line. And an electro-optical device provided with a pixel electrode and a thin film transistor arranged so as to correspond to an intersecting region of the scanning line, forming a part of a laminated structure, further comprising a layer below the data line on the substrate. A storage capacitor electrically connected to the thin film transistor and the pixel electrode; a capacitor line formed above the data line; and a pixel potential side capacitor electrode of the storage capacitor and the pixel electrode. And a first relay electrode formed in the same layer as the data line, and a fixed potential side capacitance of the storage capacitor and the capacitance line, and electrically connected to the data line. The first formed by one layer And a relay electrode, the data line, the first relay layer, the second relay layer, characterized in that it contains nitride.

  According to this electro-optical device, first, since the scanning lines and the data lines, the pixel electrodes, and the thin film transistors are provided, active matrix driving can be performed. Further, in the electro-optical device, since the above-mentioned various components form a part of a laminated structure, miniaturization of the entire device can be achieved, and an appropriate arrangement of the various components is realized. By doing so, the pixel aperture ratio can be improved.

  In particular, the data line, the first relay film, and the second relay film each include a nitride film, and since the nitride film has an excellent effect of blocking the intrusion or diffusion of moisture, the infiltration of moisture into the semiconductor layer of the thin film transistor is performed. Can be prevented as much as possible. Accordingly, it is possible to prevent the occurrence of a problem that the threshold voltage of the thin film transistor is increased as much as possible, and it is possible to maintain the operating life of the electro-optical device for a long time.

  In the electro-optical device according to the aspect of the invention, it is preferable that the data line, the first relay layer, and the second relay layer include a nitride film on a conductive layer. In particular, the data line, the first relay layer, and the second relay layer preferably have a three-layer structure of aluminum, a titanium nitride film, and a silicon nitride film.

  According to this aspect, since the data line includes aluminum, which is a relatively low-resistance material, supply of an image signal to the thin film transistor and the pixel electrode can be realized without interruption. On the other hand, the formation of the silicon nitride film having a relatively excellent effect of damping the entry of moisture on the data line can improve the moisture resistance of the thin film transistor and can prolong its life. Note that the silicon nitride film is preferably a plasma silicon nitride film.

  Further, the titanium nitride films of the first relay layer and the second relay layer function as barrier metals for preventing contact holes formed in the first relay layer and the second relay layer from being etched. In addition, together with the data line, the infiltration of moisture can be suppressed, the moisture resistance of the thin film transistor can be improved, and the life of the thin film transistor can be extended.

  In the electro-optical device according to the aspect of the invention, it is preferable that the first relay layer is electrically connected to the pixel electrode via a third relay film formed of the same layer as the capacitor line. Further, the capacitance line and the third relay film may include a nitride film on a conductive layer. Further, it is preferable that the capacitance line and the third relay film have a three-layer structure of aluminum, a titanium nitride film, and a silicon nitride film.

  According to this aspect, by providing between the data line and the pixel electrode, it is possible to prevent the occurrence of capacitive coupling between the two. That is, it is possible to reduce the possibility of the potential fluctuation or the like occurring in the pixel electrode due to the energization of the data line, and it is possible to display a higher quality image.

  In the electro-optical device according to the aspect of the invention, the pixel-potential-side capacitance electrode may be electrically connected to the first relay film via a fourth relay film formed on an insulating film on which the thin film transistor is formed. It is good to be done.

According to this aspect, since the pixel potential side capacitance electrode and the pixel electrode are once electrically connected from the lower layer of the pixel potential side capacitance electrode, when patterning the storage capacitance, it is prevented by penetration during etching. be able to.
Further, as another aspect, the fourth relay film may be formed of the same film as a gate electrode of the thin film transistor.
According to this aspect, the manufacturing process can be simplified, the manufacturing cost can be reduced, and the like, as compared with the case where the fourth relay electrode is manufactured through a special process. In the case where the scanning line includes a gate electrode, at least the gate electrode portion in the scanning line is made of, for example, a conductive polysilicon film so that the function as the gate electrode can be sufficiently exhibited. It is good to be constituted as follows. In such a case, the fourth relay electrode is also made of a conductive polysilicon film or the like.

  Further, as will be apparent from the description of this embodiment, the “fourth relay electrode” of the present invention does not necessarily need to be formed as the same film as the gate electrode. In this case, as described above, since the relay electrode and the gate electrode are not made of the same material, the material of the relay electrode is basically freely selected as long as it has conductivity. Good.

  Particularly in this aspect, in the stacked structure, the scanning line and the gate electrode are formed in different layers.

  According to such a configuration, specifically, the stacked structure has a structure in which, for example, a scanning line is a lower layer (or an upper layer) and a gate electrode is an upper layer (or a lower layer). Thus, in the layer where the gate electrode is formed, it is not necessary to perform striping patterning as in the case of forming a scanning line, and if the thin film transistors are arranged in a matrix, the gate electrode is formed. For this purpose, island-shaped patterning corresponding to the matrix shape may be performed. That is, in the layer where the gate electrode is formed, a relatively large surplus area can be secured.

  Therefore, as described above, in the case where the gate electrode and the fourth relay electrode are formed as the same film, there is obtained an advantage that the formation of the relay electrode is easy.

  In this aspect, it is preferable that the scanning line further includes a protrusion protruding in the first direction.

  According to such a configuration, the scanning line is formed in a layer different from the gate electrode or the thin film transistor that is inseparably integrated with the gate electrode, and the scanning line has a protrusion protruding in the first direction. Thus, the scanning line can function as a lower light-shielding film for the thin film transistor. That is, by preventing the incidence of light on the semiconductor layer of the thin film transistor and suppressing the occurrence of light leakage current, it is possible to display a high-quality image without flicker or the like.

In this case, it is preferable that the scanning line be made of conductive polysilicon or tungsten silicide (WSi) having relatively excellent light absorption.
In the electro-optical device according to the aspect of the invention, between the pixel potential-side capacitance electrode and the fixed potential-side capacitance electrode of the storage capacitor, a plurality of layers including different materials may be formed, and one of the layers may be formed. The layer may be a dielectric film including a layer made of a material having a higher dielectric constant than other layers. Further, the dielectric film may be composed of a silicon oxide film and a silicon nitride film.
According to this aspect, the charge storage characteristics are more excellent than in the related art, so that the potential holding characteristics of the pixel electrodes can be further improved, and a higher quality image can be displayed. . As the “high dielectric constant material” in the present invention, in addition to silicon nitride described later, TaOx (tantalum oxide), BST (strontium barium titanate), PZT (zirconate titanate), TiO ₂ (titanium oxide) ), ZiO ₂ (zirconium oxide), HfO ₂ (hafnium oxide), and an insulating material containing at least one of SiON (silicon oxynitride) and SiN (silicon nitride). In particular, it increases TaOx, BST, _PZT, if using a high dielectric constant material such as TiO 2, ZiO ₂ and HfO _2, the capacitance value on a limited substrate region. Alternatively, when a material containing silicon such as SiO ₂ (silicon oxide), SiON (silicon oxynitride), and SiN is used, generation of stress in an interlayer insulating film or the like can be reduced.

  In addition, in the present invention, the pixel-potential-side capacitance electrode forming the storage capacitor and the pixel electrode are electrically connected to each other through a relay electrode located below each of these in the laminated structure. That is, the arrangement relationship between the pixel potential side capacitor electrode and the relay electrode is such that the former is in the upper layer and the latter is in the lower layer, and the arrangement relationship between the pixel electrode and the relay electrode is also the upper layer and the latter is in the lower layer. It becomes. In short, the relay electrode is located at the lowermost layer among these three members. Then, the electrical connection between the pixel potential side capacitor electrode and the pixel electrode is performed via the above-mentioned relay electrode, and thus, in the structure, an electrical connection point is provided below each of the pixel potential side capacitor electrode and the pixel electrode. And it is possible not to provide an electrical connection point on the upper side.

  Here, the fact that the pixel potential side capacitor electrode does not have an electrical connection point on the upper side means that the connection between the pixel potential side capacitor electrode and the pixel electrode is made from above the stacked structure as in the related art. This means that there is no need to perform any processing or processing so that the surface of the pixel potential side capacitance electrode can be seen. For example, in the case where the arrangement relationship between the pixel potential side capacitor electrode and the fixed potential side capacitor electrode is such that the former is located in the lower layer and the latter is located in the upper layer, if the surface of the pixel potential side capacitor electrode is visible, processing is performed. Then, it is necessary to pattern the fixed-potential-side capacitance electrode located thereabove so as to have a predetermined shape. That is, the area of the fixed potential side capacitor electrode is smaller than the area of the pixel potential side capacitor electrode, in other words, the edge of the pixel potential side capacitor electrode is protruded from the edge of the fixed potential side capacitor electrode. It becomes necessary to pattern the fixed potential side capacitance electrode.

  However, such patterning involves difficulties. This is because, generally, the etching condition of the fixed potential side capacitance electrode is selected such that the etching rate of the dielectric film is lower than that of the fixed potential side capacitance electrode so that the etching stops in the middle of the dielectric film. However, the dielectric film is usually formed so as to be thinner, and in the present invention, particularly, the dielectric film is made of a high dielectric material such as SiN or TaOx. For example, etching may not stop in the middle of the dielectric film, and depending on the material of the dielectric film, the etching condition cannot be selected so that the etching rate of the dielectric film is lower than the etching rate of the fixed potential side capacitor electrode. Therefore, when the above-described patterning is performed, there is a large possibility that so-called “penetration” or the like is caused in the pixel potential side capacitor electrode. If such an event occurs, in a bad case, a short circuit may occur between a pair of electrodes constituting the storage capacitor, so that the storage capacitor can no longer be used as a capacitor. .

However, in the present invention, since the electrical connection point in the pixel potential side capacitance electrode is located below the pixel potential side capacitance electrode as described above, the fixed potential side capacitance electrode is Therefore, it is not necessary to perform a difficult patterning process or the like.
As described above, according to the present invention, the electrical connection between the pixel potential side capacitor electrode and the pixel electrode can be satisfactorily realized, and unnecessary defects in the storage capacitor (for example, the pixel potential side capacitor electrode as described above) ), It is possible to provide an electro-optical device that can operate more favorably. The electro-optical device having the above-described arrangement of the relay electrode, the storage capacitor, and the like provides a suitable laminated structure, so that further miniaturization and higher definition can be realized relatively easily. It is.
In the present invention, the capacitance line may be formed of a light-shielding film, and may be formed along the data line and wider than the data line.
In addition, according to the present invention, at least a surface of the first insulating film among a first insulating film disposed as a base of the pixel electrode and a second insulating film disposed as a base of the capacitance line is planarized. It may be applied.
According to this aspect, the interlayer insulating film is provided below the pixel electrode, and the surface of the interlayer insulating film is subjected to a flattening process such as a CMP (Chemical Mechanical Polishing) process, so that the liquid crystal or the like is formed. Thus, the possibility that the orientation state of the electro-optical material is disturbed can be reduced, and a higher quality image can be displayed. This is because, in the present invention, in consideration of the fact that the degree of unevenness on the surface of the interlayer insulating film below the pixel electrode may be increased due to the provision of the relay electrode, an electric device that performs a more accurate operation is considered. This is advantageous in providing an optical device.

  Further, in the aspect of the electro-optical device having the shield layer as described above, another electro-optical device is further provided as an underlayer of the shield layer, and the surface of the another inter-layer insulating film is planarized. It is preferable that the processing is performed.

  According to such a configuration, another interlayer insulating film is provided as a base of the shield layer, and the surface of the another interlayer insulating film is subjected to a planarization process such as a CMP process. This can reduce the possibility that the alignment state of the electro-optical material such as a liquid crystal may be disturbed, thereby enabling a higher quality image to be displayed.

  Further, in this aspect, if the aspect in which the interlayer insulating film disposed below the pixel electrode is subjected to the flattening treatment as described above is combined with the aspect, the above-described operation and effect can be more effectively enjoyed.

  Alternatively, in the aspect of the electro-optical device including the shield layer, the scanning line including the gate electrode of the thin film transistor is provided on the substrate, and the storage capacitor is provided as an upper layer of the scanning line. The data line is provided as an upper layer of the storage capacitor, the shield layer is provided as an upper layer of the data line, and the pixel electrode is provided as an upper layer of the shield layer. The storage capacitor includes, from the lower layer side, an arrangement of the pixel potential side capacitance electrode, the dielectric film, and the fixed potential side capacitance electrode, and the relay electrode is formed as the same film as the gate electrode. Good to do.

  According to such a configuration, an embodiment having an optimal arrangement or layout is provided as a laminated structure built on a substrate.

  In order to solve the above problems, a method of manufacturing an electro-optical device according to the present invention includes the steps of: forming a thin film transistor on a substrate; forming a first interlayer insulating film on a gate electrode of the thin film transistor; Forming a pixel potential side capacitor electrode, a dielectric film, and a fixed potential side capacitor electrode in order from the bottom above one interlayer insulating film to form a storage capacitor; and forming a second interlayer insulating film above the storage capacitor. And forming a data line electrically connected to a semiconductor layer of the thin film transistor with a conductive material including a nitride film on the upper side of the second interlayer insulating film, and electrically connected to the pixel potential side capacitance electrode. Forming a first relay film to be connected, and a second relay film electrically connected to the fixed potential side capacitance electrode; and forming the second relay film on the data line, the first relay film, and the second relay film. Form a third interlayer insulating film Forming a third relay film electrically connected to the first relay film and a capacitor line electrically connected to the second relay film on the third interlayer insulating film. Forming a fourth interlayer insulating film above the third relay film and the capacitor line; and forming a pixel electrode electrically connected to the third relay film above the fourth interlayer insulating film. Forming step.

  According to such a manufacturing method, the above-described electro-optical device can be formed relatively easily.

  In one aspect of the method of manufacturing an electro-optical device according to the aspect of the invention, the step of forming the storage capacitor includes a step of forming a first precursor film of the pixel potential side capacitor electrode, and the step of: Forming a second precursor film of a dielectric film, forming a third precursor film of the fixed potential side capacitor electrode above the second precursor film, forming the first precursor film, the second precursor film, Patterning the film and the third precursor film at a time to form the pixel potential side capacitance electrode, the dielectric film, and the fixed potential side capacitance electrode.

  According to this aspect, the step of forming the storage capacitor includes forming the first, second, and third precursor films of the pixel potential side capacitor electrode, the dielectric film, and the fixed potential side capacitor electrode once, and then forming them at once. Patterning step. That is, according to this aspect, typically, the three-dimensional configuration of the three elements constituting the storage capacitor is the same. As a result, a storage capacitor having a relatively large capacitance value can be manufactured without having a useless planar spread, that is, without lowering the pixel aperture ratio. According to this aspect, since the above-described three elements are simultaneously patterned, only the fixed-potential-side capacitance electrode is etched and the dielectric film and the pixel-potential-side capacitance electrode are left as they are, as in the related art. There are no difficult tasks. As a result, according to the present invention, it is possible to easily and reliably manufacture the accumulated volume.

  In another aspect of the method for manufacturing an electro-optical device according to the present invention, the step of forming the storage capacitor includes forming a first precursor film of the pixel potential side capacitor electrode, and patterning the first precursor film. Forming the pixel potential side capacitor electrode; forming a second precursor film of the dielectric film on the first precursor film; and forming the fixed potential side capacitor on the second precursor film. Forming a third precursor film of an electrode; and patterning the third precursor film to form the dielectric film and the fixed potential side capacitance electrode, wherein the fixed potential side capacitance electrode and the dielectric The body film is formed such that its area is larger than the areas of the pixel potential side capacitor electrode and the dielectric film.

  According to this aspect, unlike the above, the first precursor film is once patterned to form the pixel potential side capacitance electrode, and thereafter, the dielectric film and the fixed potential side capacitance electrode are formed. Further, in this aspect, the area of the fixed potential side capacitance electrode is made larger than the areas of the pixel potential side capacitance electrode and the dielectric film.

  According to the above, a storage capacitor having a structure in which the fixed potential side capacitance electrode and the dielectric film cover the pixel potential side capacitance electrode can be formed. Therefore, it is possible to sandwich the dielectric film with a wider electrode area, and a storage capacitor having a larger capacitance value is configured. Specifically, for example, in this embodiment, the side surfaces of the three elements can be used as a capacitor, and an increase in the capacitance value due to this can be expected. Further, from such a viewpoint, for example, if the pixel potential side capacitance electrode is formed to be thick, the area of the side surface is increased, and the capacitance value can be efficiently obtained. Furthermore, according to such an embodiment, it can be said that it is difficult to cause a short circuit between the pixel potential side capacitor electrode and the fixed potential side capacitor electrode.

  In this embodiment, when patterning the third precursor film, patterning of the second precursor film may be performed at the same time.

  An electronic apparatus of the present invention includes the above-described electro-optical device of the present invention. However, the various aspects are included.

  According to the electronic apparatus of the present invention, since the electronic apparatus includes the above-described electro-optical device of the present invention, the electrical connection between the storage capacitor and the pixel electrode can be satisfactorily realized. A projection-type display device and a liquid crystal television, which can display a higher quality image by being able to expect an accurate operation, and are equipped with a highly reliable electro-optical device such as a liquid crystal device. Various electronic devices such as a mobile phone, an electronic organizer, a word processor, a view finder type or a monitor direct view type video tape recorder, a workstation, a video phone, a POS terminal, and a touch panel can be realized.

  The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the electro-optical device of the present invention is applied to a liquid crystal device.

(Configuration in the pixel section)
First, the configuration of the pixel portion of the electro-optical device according to the embodiment of the present invention will be described with reference to FIGS. Here, FIG. 1 is an equivalent circuit of various elements, wiring, and the like in a plurality of pixels formed in a matrix forming an image display area of the electro-optical device. FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. FIG. 3 is a plan view mainly showing only main components of FIG. 2, specifically, only the data lines, the shield layer, and the pixel electrodes in order to show the positional relationship between the pixel electrodes. FIG. 4 is a sectional view taken along line AA ′ of FIG. In FIG. 4, the scale of each layer / member is made different so that each layer / member has a size recognizable in the drawing.

  In FIG. 1, a plurality of pixels formed in a matrix forming an image display area of the electro-optical device according to the present embodiment are each formed with a pixel electrode 9a and a TFT 30 for controlling switching of the pixel electrode 9a. The data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. Good.

  Further, a gate electrode is electrically connected to the gate of the TFT 30, and scan signals G1, G2,..., Gm are applied in a pulsed manner to the scan line 11a and the gate electrode in this order at a predetermined timing. It is configured as follows. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and by closing the switch of the TFT 30 as a switching element for a certain period, the image signals S1, S2,... Write at a predetermined timing.

  The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal as an example of the electro-optical material via the pixel electrodes 9a are held for a certain period between the pixel electrodes 9a and the counter electrode formed on the counter substrate. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode, the transmittance for the incident light decreases according to the voltage applied in each pixel unit, and in the normally black mode, the light enters according to the voltage applied in each pixel unit Light transmittance is increased, and light having a contrast corresponding to an image signal is emitted from the electro-optical device as a whole.

  In order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacitor 70 is provided alongside the scanning line 11a, includes a fixed-potential-side capacitor electrode, and includes a capacitor electrode 300 fixed to a constant potential.

  Hereinafter, the actual configuration of the electro-optical device that realizes the above-described circuit operation using the data line 6a, the scanning line 11a, the gate electrode, the TFT 30, and the like will be described with reference to FIGS. .

  First, in FIG. 2, a plurality of pixel electrodes 9 a are provided in a matrix on the TFT array substrate 10 (the outline is indicated by a dotted line), and data are respectively provided along the vertical and horizontal boundaries of the pixel electrode 9 a. A line 6a and a scanning line 11a are provided. The data line 6a has a laminated structure including an aluminum film or the like as described later, and the scanning line 11a is formed of, for example, a conductive polysilicon film. Further, the scanning line 11a is electrically connected to the gate electrode 3a facing the channel region 1a 'indicated by a hatched region in the semiconductor layer 1a, which rises to the right in the figure, and the gate electrode 3a is connected to the scanning line 11a. It is included in the form. That is, at the intersections of the gate electrodes 3a and the data lines 6a, the pixel switching TFTs 30 in which the gate electrodes 3a included in the scanning lines 11a are opposed to each other in the channel region 1a 'are provided. In other words, the TFT 30 (excluding the gate electrode) has a form that exists between the gate electrode 3a and the scanning line 11a.

  Next, as shown in FIG. 4, which is a cross-sectional view taken along the line AA ′ of FIG. 2, the electro-optical device is disposed to face the TFT array substrate 10 made of, for example, a quartz substrate, a glass substrate, or a silicon substrate. And a counter substrate 20 made of, for example, a glass substrate or a quartz substrate.

  As shown in FIG. 4, the pixel electrode 9a is provided on the side of the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. ing. The pixel electrode 9a is made of, for example, a transparent conductive film such as an ITO film. On the other hand, a counter electrode 21 is provided over the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode 21. . The counter electrode 21 is made of a transparent conductive film such as an ITO film, like the pixel electrode 9a, and the alignment films 16 and 22 are made of a transparent organic film such as a polyimide film.

  An electro-optical material such as a liquid crystal is sealed in a space surrounded by a sealing material (see FIGS. 8 and 9) described later between the TFT array substrate 10 and the counter substrate 20 which are arranged so as to face each other. Is formed. The liquid crystal layer 50 assumes a predetermined alignment state by the alignment films 16 and 22 when no electric field is applied from the pixel electrode 9a. The liquid crystal layer 50 is made of, for example, an electro-optical material in which one or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the TFT substrate 10 and the counter substrate 20 around the periphery thereof, and is used for setting a distance between the two substrates to a predetermined value. Spacers such as glass fibers or glass beads are mixed.

  On the other hand, on the TFT array substrate 10, in addition to the pixel electrode 9a and the alignment film 16, various configurations including these are provided in a laminated structure. As shown in FIG. 4, this laminated structure includes, in order from the bottom, a first layer including the scanning line 11a, a second layer including the TFT 30 including the gate electrode 3a, a third layer including the storage capacitor 70, and the data line 6a. And the like, a fifth layer including the shield layer 400 and the like, and a sixth layer (uppermost layer) including the pixel electrode 9a and the alignment film 16 and the like. A base insulating film 12 is provided between the first and second layers, a first interlayer insulating film 41 is provided between the second and third layers, and a second interlayer insulating film 42 is provided between the third and fourth layers. , A third interlayer insulating film 43 is provided between the fourth and fifth layers, and a fourth interlayer insulating film 44 is provided between the fifth and sixth layers, respectively. Has been prevented. In addition, the various insulating films 12, 41, 42, 43, and 44 are also provided with, for example, contact holes for electrically connecting the high-concentration source region 1d in the semiconductor layer 1a of the TFT 30 and the data line 6a. Has been. Hereinafter, each of these elements will be described in order from the bottom.

  First, the first layer includes, for example, a simple metal containing at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). , An alloy, a metal silicide, a polysilicide, a laminate thereof, or a scanning line 11a made of conductive polysilicon or the like. The scanning lines 11a are patterned in stripes along the X direction in FIG. 2 when viewed in plan. More specifically, the stripe-shaped scanning line 11a includes a main line portion extending along the X direction in FIG. 2 and a protrusion extending in the Y direction in FIG. 2 where the data line 6a or the shield layer 400 extends. ing. The protruding portions extending from the adjacent scanning lines 11a are not connected to each other, and therefore, the scanning lines 11a are separated one by one.

  Thus, the scanning line 11a has a function of simultaneously controlling ON / OFF of the TFTs 30 existing in the same row. Further, since the scanning line 11a is formed so as to substantially fill a region where the pixel electrode 9a is not formed, the scanning line 11a also has a function of blocking light from entering the TFT 30 from below. This suppresses the occurrence of light leakage current in the semiconductor layer 1a of the TFT 30, and enables high-quality image display without flicker or the like. Note that the conductive polysilicon has a light absorbing function.

  Next, a TFT 30 including the gate electrode 3a is provided as a second layer. As shown in FIG. 4, the TFT 30 has an LDD (Lightly Doped Drain) structure, and includes a gate electrode 3a, for example, a polysilicon film as described above, and a channel formed by an electric field from the gate electrode 3a. A channel region 1a 'of the semiconductor layer 1a to be formed, an insulating film 2 including a gate insulating film for insulating the gate electrode 3a from the semiconductor layer 1a, a low-concentration source region 1b and a low-concentration drain region 1c in the semiconductor layer 1a, and a high-concentration region A source region 1d and a high-concentration drain region 1e are provided.

  In the present embodiment, in particular, a relay electrode 719 is formed on the second layer as the same film as the gate electrode 3a. As shown in FIG. 2, the relay electrode 719 is formed in an island shape so as to be located substantially at the center of one side of each pixel electrode 9a as shown in FIG. Since the relay electrode 719 and the gate electrode 3a are formed as the same film, when the latter is made of, for example, a conductive polysilicon film, the former is also made of a conductive polysilicon film.

The above-described TFT 30 preferably has an LDD structure as shown in FIG. 4, but may have an offset structure in which impurities are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c. A self-aligned TFT in which impurities are implanted at a high concentration as a mask to form a high-concentration source region and a high-concentration drain region in a self-aligned manner may be used. Further, in the present embodiment, a single gate structure in which only one gate electrode of the pixel switching TFT 30 is disposed between the high-concentration source region 1d and the high-concentration drain region 1e has been described. Electrodes may be arranged. When a TFT is formed with a dual gate or triple gate or more as described above, a leak current at a junction between a channel and a source / drain region can be prevented, and a current in an off state can be reduced.
Further, the semiconductor layer 1a constituting the TFT 30 may be a non-single-crystal layer or a single-crystal layer. For forming the single crystal layer, a known method such as a bonding method can be used. By using the semiconductor layer 1a as a single crystal layer, the performance of peripheral circuits in particular can be improved.

  Above the scanning line 11a and below the TFT 30, the underlying insulating film 12 made of, for example, a silicon oxide film is provided. The base insulating film 12 has a function of interlayer insulating the TFT 30 from the scanning line 11a, and is formed on the entire surface of the TFT array substrate 10 so that the base insulating film 12 may be roughened when the surface of the TFT array substrate 10 is polished or stains remaining after cleaning. It has a function of preventing a characteristic change of the TFT 30 for pixel switching.

  The base insulating film 12 has grooves (contact holes having the same width as or longer than the channel length of the semiconductor layer 1a extending along the data lines 6a described later) on both sides of the semiconductor layer 1a in plan view. A trench 12cv is formed, and the gate electrode 3a stacked thereover includes a portion formed in a concave shape on the lower side corresponding to the trench 12cv. Further, since the gate electrode 3a is formed so as to fill the entire groove 12cv, a side wall 3b integrally formed with the gate electrode 3a is extended. I have. As a result, the semiconductor layer 1a of the TFT 30 is covered from the side as viewed in plan, as is well shown in FIG. 2, so that at least the incidence of light from this portion is suppressed. Has become.

  The side wall 3b is formed so as to fill the groove 12cv, and the lower end thereof is in contact with the scanning line 11a. Here, since the scanning line 11a is formed in a stripe shape as described above, the gate electrode 3a and the scanning line 11a existing in a certain row always have the same potential as far as the row is concerned.

Here, in the present invention, a structure in which another scanning line including the gate electrode 3a is formed so as to be parallel to the scanning line 11a may be employed. In this case, the scanning line 11a and the another scanning line have a redundant wiring structure.
Thereby, for example, even when a part of the scanning line 11a has some defect and normal energization becomes impossible, another scanning line existing in the same row as the scanning line 11a is not used. As long as it is sound, the operation control of the TFT 30 can still be performed normally through it.

  Now, a storage capacitor 70 is provided in the third layer following the second layer. The storage capacitor 70 includes a lower electrode 71 serving as a pixel potential-side capacitor electrode connected to the high-concentration drain region 1 e and the pixel electrode 9 a of the TFT 30, and a capacitor electrode 300 serving as a fixed-potential-side capacitor electrode. It is formed by being arranged to face through. According to the storage capacitor 70, the potential holding characteristic of the pixel electrode 9a can be significantly improved. In addition, as can be seen from the plan view of FIG. 2, the storage capacitor 70 according to the present embodiment is formed so as not to reach the light transmission region substantially corresponding to the formation region of the pixel electrode 9a. If so, the pixel aperture ratio of the entire electro-optical device is maintained relatively large because the pixel aperture ratio is formed so as to be contained in the light-shielding region, and thereby a brighter image can be displayed.

  More specifically, the lower electrode 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitance electrode. However, the lower electrode 71 may be formed of a single-layer film or a multilayer film containing a metal or an alloy. The lower electrode 71 has a function of relay connection between the pixel electrode 9a and the high-concentration drain region 1e of the TFT 30, in addition to a function as a pixel potential side capacitor electrode. The present embodiment is particularly characterized in that the relay connection here is performed via the relay electrode 719. This point will be mentioned later.

  The capacitance electrode 300 functions as a fixed potential side capacitance electrode of the storage capacitor 70. In the present embodiment, in order to set the capacitor electrode 300 to a fixed potential, the capacitor electrode 300 is electrically connected to the shield layer 400 set to the fixed potential.

In the present embodiment, particularly, the capacitance electrode 300 is formed in an island shape on the TFT array substrate 10 so as to correspond to each pixel, and the lower electrode 71 is substantially the same as the capacitance electrode 300. It is formed to have a shape.
As a result, the storage capacitor 70 according to the present embodiment does not have a useless spread in a plane, that is, can realize the maximum capacitance value without lowering the pixel aperture ratio and under such circumstances. become. That is, in the present embodiment, the storage capacitor 70 has a smaller area and a larger capacitance value.

  More specifically, in FIG. 4, it can be seen that the area of the capacitor electrode 300 is slightly larger than the area of the lower electrode 71, that is, the former is formed so as to cover the latter. According to such an embodiment, as can be read from the figure, the side surfaces of the capacitor electrode 300 and the lower electrode 71 can also be used as capacitors (see the left side of the storage capacitor 70 in FIG. 4). The capacitance value can be increased. In addition, a short circuit between the two is unlikely to occur. From such a viewpoint, it is also effective to previously form, for example, the lower electrode 71 to be relatively thick in order to increase the area of the side surface.

  As shown in FIG. 4, the dielectric film 75 is, for example, a relatively thin silicon oxide film such as an HTO (High Temperature Oxide) film or an LTO (Low Temperature Oxide) film having a thickness of about 5 to 200 nm, or a silicon nitride film. Consists of From the viewpoint of increasing the storage capacitance 70, the thinner the dielectric film 75 is, the better the reliability of the film can be obtained. In the present embodiment, particularly, the dielectric film 75 has a two-layer structure such as a silicon oxide film 75a as a lower layer and a silicon nitride film 75b as an upper layer as shown in FIG. The upper silicon nitride film 75b is patterned so as to be slightly larger in size than the lower electrode 71 of the pixel potential side capacitor electrode, and is formed so as to fit within the light shielding region (non-opening region). Thus, the presence of the silicon nitride film 75b having a relatively large dielectric constant allows the capacitance value of the storage capacitor 70 to be increased, and nevertheless, the presence of the silicon oxide film 75a The breakdown voltage of the storage capacitor 70 is not reduced. Thus, by making the dielectric film 75 have a two-layer structure, it is possible to enjoy two opposing effects. The colored silicon nitride 75b is patterned into a slightly larger size than the lower electrode 71, and is not formed in a portion where light is transmitted. That is, since it is located in the light shielding region, it is possible to prevent the transmittance from being lowered. Further, the presence of the silicon nitride film 75b makes it possible to prevent water from entering the TFT 30 before it occurs. As a result, in the present embodiment, a situation in which the threshold voltage of the TFT 30 rises does not occur, and the device can be operated for a relatively long time. In the present embodiment, the dielectric film 75 has a two-layer structure. In some cases, for example, a three-layer structure such as a silicon oxide film, a silicon nitride film, and a silicon oxide film, Or you may comprise so that it may have more laminated structures.

  Above the TFT 30 or the gate electrode 3a and the relay electrode 719 described above and below the storage capacitor 70, for example, NSG (non-silicate glass), PSG (phosphorous silicate glass), BSG (boron silicate glass), BPSG ( A silicate glass film such as boron phosphorus silicate glass, a silicon nitride film, a silicon oxide film, or the like, or a first interlayer insulating film 41 preferably made of NSG is formed. In the first interlayer insulating film 41, a contact hole 81 for electrically connecting the high-concentration source region 1d of the TFT 30 and a data line 6a described later is opened while penetrating a second interlayer insulating film 42 described later. Have been. In the first interlayer insulating film 41, a contact hole 83 for electrically connecting the high-concentration drain region 1e of the TFT 30 and the lower electrode 71 constituting the storage capacitor 70 is formed.

  Further, the first interlayer insulating film 41 is provided with a contact hole 881 for electrically connecting the lower electrode 71 as a pixel potential side capacitor electrode constituting the storage capacitor 70 and the relay electrode 719. . In addition, a contact hole 882 for electrically connecting the relay electrode 719 to a second relay electrode 6a2 described below is formed in the first interlayer insulating film 41 while penetrating the second interlayer insulating film described later. I have.

  Note that, of these four contact holes, in the portions where the contact holes 81 and 882 are formed, the aforementioned dielectric film 75 is not formed, in other words, the opening is formed in the dielectric film 75. Has become. This is because it is necessary to establish electrical continuity between the high-concentration source region 1d and the data line 6a in the contact hole 81. In the contact hole 882, the contact hole 882 is separated from the first and second interlayer insulating layers. This is for allowing the films 41 and 42 to penetrate. Incidentally, if such an opening is provided in the dielectric film 75, when hydrogenation processing is performed on the semiconductor layer 1a of the TFT 30, hydrogen used for the processing is supplied to the semiconductor layer 1a through the opening. It is also possible to obtain the effect of being able to easily reach.

  In the present embodiment, the first interlayer insulating film 41 is baked at about 1000 ° C. to activate the ions implanted into the polysilicon film forming the semiconductor layer 1a and the gate electrode 3a. May be.

  Now, a data line 6a is provided in the fourth layer following the third layer. The data line 6a is formed in a stripe shape so as to coincide with the direction in which the semiconductor layer 1a of the TFT 30 extends, that is, to overlap in the Y direction in FIG. As shown in FIG. 4, the data line 6a is formed of a layer made of aluminum (reference numeral 41A in FIG. 4), a layer made of titanium nitride (see reference numeral 41TN in FIG. 4), and a layer made of a silicon nitride film (see FIG. 4). It is formed as a film having a three-layer structure denoted by reference numeral 401) in FIG. The silicon nitride film is patterned to have a slightly larger size so as to cover the underlying aluminum layer and titanium nitride layer. Since the data line 6a contains aluminum, which is a relatively low-resistance material, supply of image signals to the TFT 30 and the pixel electrode 9a can be realized without interruption. On the other hand, the formation of the silicon nitride film having a relatively excellent effect of blocking the intrusion of moisture on the data line 6a can improve the moisture resistance of the TFT 30 and can prolong its life. The silicon nitride film is preferably a plasma silicon nitride film.

In the fourth layer, a relay layer 6a1 for a shield layer and a second relay electrode 6a2 are formed as the same film as the data line 6a. As shown in FIG. 2, these are not formed so as to have a planar shape that is continuous with the data line 6a when viewed two-dimensionally, but are formed so as to be separated from each other by patterning. I have. That is, paying attention to the data line 6a located on the leftmost side in FIG. 2, the relay layer 6a1 for a shield layer having a substantially quadrangular shape rightward of the data line 6a is slightly larger than the relay layer 6a1 for the shield layer on the right side. A second relay electrode 6a2 having a substantially quadrangular shape having an area of? The shield layer relay layer 6a1 and the second relay electrode 6a2 are formed in the same process as the data line 6a, and have a three-layer structure of a layer made of aluminum, a layer made of titanium nitride, and a layer made of a plasma nitride film in order from the lower layer. It is formed as.
The plasma nitride film is patterned to have a slightly larger size so as to cover the underlying aluminum layer and titanium nitride layer. The titanium nitride layer functions as a barrier metal for preventing penetration of etching of the contact holes 803 and 804 formed with respect to the shield layer relay layer 6a1 and the second relay electrode 6a2.
Further, by forming a silicon nitride film having a relatively excellent effect of blocking moisture intrusion on the shield layer relay layer 6a1 and the second relay electrode 6a2, the moisture resistance of the TFT 30 can be improved. A longer life can be achieved. Note that the silicon nitride film is preferably a plasma silicon nitride film.

  A silicate glass film such as NSG, PSG, BSG or BPSG, a silicon nitride film or a silicon oxide film, or a TEOS gas is preferably used above the storage capacitor 70 and below the data line 6a. A second interlayer insulating film 42 formed by a plasma CVD method is formed. The second interlayer insulating film 42 is provided with the contact hole 81 for electrically connecting the high-concentration source region 1d of the TFT 30 and the data line 6a, and is provided with the shield layer relay layer 6a1. A contact hole 801 for electrically connecting the storage capacitor 70 to the capacitor electrode 300 as an upper electrode is opened. Further, the above-mentioned contact hole 882 for electrically connecting the second relay electrode 6a2 and the relay electrode 719 is formed in the second interlayer insulating film.

  The shield layer 400 is formed on the fifth layer following the fourth layer. The shield layer 400 is formed in a lattice shape so as to extend in the X direction and the Y direction in the drawing as shown in FIGS. Particularly, a portion of the shield layer 400 extending in the Y direction in the drawing is formed so as to cover the data line 6a and to be wider than the data line 6a. In addition, the portion extending in the X direction in the drawing has a cutout near the center of one side of each pixel electrode 9a in order to secure a region for forming a third relay electrode 402 described later.

  Further, in FIG. 2 or FIG. 3, substantially triangular portions are provided at the corners of the intersections of the shield layers 400 extending in the XY directions so as to fill the corners. By providing the substantially triangular portion in the shield layer 400, light can be effectively shielded from the semiconductor layer 1a of the TFT 30. That is, light that is about to enter the semiconductor layer 1a obliquely from above is reflected or absorbed by this triangular portion, and does not reach the semiconductor layer 1a. Therefore, it is possible to suppress the occurrence of light leakage current and display a high-quality image without flicker or the like.

  The shield layer 400 extends from the image display area 10a in which the pixel electrode 9a is arranged to the periphery thereof, and is electrically connected to a constant potential source to have a fixed potential. The “constant potential source” described here may be a constant potential source of a positive power supply or a negative power supply supplied to the data line driving circuit 101 or a constant potential source supplied to the counter electrode 21 of the counter substrate 20. But it doesn't matter.

  As described above, the capacitance formed between the data line 6a and the pixel electrode 9a is formed so as to cover the entire data line 6a (see FIG. 3). It is possible to eliminate the influence of the coupling. That is, it is possible to avoid a situation in which the potential of the pixel electrode 9a fluctuates in accordance with the energization of the data line 6a, which may cause display unevenness or the like along the data line 6a on an image. Can be reduced. In particular, in the present embodiment, since the shield layer 400 is formed in a lattice shape, it is possible to suppress unnecessary capacitive coupling even at a portion where the scanning line 11a extends, so that unnecessary capacitive coupling does not occur. ing.

  In the fourth layer, a third relay electrode 402, which is an example of the “relay layer” according to the present invention, is formed as the same film as the shield layer 400. The third relay electrode 402 has a function of relaying an electrical connection between the second relay electrode 6a2 and the pixel electrode 9a via a contact hole 89 described later. The shield layer 400 and the third relay electrode 402 are not formed continuously in a planar shape, but are formed so as to be separated on patterning.

  On the other hand, the above-described shield layer 400 and third relay electrode 402 have a two-layer structure of a lower layer made of aluminum and an upper layer made of titanium nitride. In the third relay electrode 402, the lower layer made of aluminum is connected to the second relay electrode 6a2, and the upper layer made of titanium nitride is connected to the pixel electrode 9a made of ITO or the like. I have. In this case, in particular, the latter connection will be performed well. In this regard, if the form in which aluminum and ITO are directly connected to each other is taken, electrolytic corrosion occurs between the two, and disconnection of aluminum or insulation due to formation of alumina, etc., makes a preferable electrical connection. In contrast to not being realized. As described above, in the present embodiment, since the electrical connection between the third relay electrode 402 and the pixel electrode 9a can be satisfactorily realized, a voltage is applied to the pixel electrode 9a or a potential holding characteristic of the pixel electrode 9a. Can be maintained satisfactorily.

  Further, since the shield layer 400 and the third relay electrode 402 include aluminum having relatively excellent light reflection performance and titanium nitride having relatively excellent light absorption performance, they can function as a light shielding layer. That is, according to these, it is possible to block the progress of the incident light (see FIG. 4) on the semiconductor layer 1a of the TFT 30 on the upper side. As described above, the same can be said for the above-described capacitance electrode 300 and data line 6a. In the present embodiment, the shield layer 400, the third relay electrode 402, the capacitor electrode 300, and the data line 6a form a part of a laminated structure built on the TFT array substrate 10 and emit light from above to the TFT 30. It can function as an upper light-shielding film (or a "built-in light-shielding film" if attention is paid to the fact that the light-shielding film constitutes a part of the laminated structure). According to the concept of "upper light-shielding film" or "built-in light-shielding film", the gate electrode 3a, the lower electrode 71, and the like can be considered as being included in the above-described structure. In short, under the premise that it is understood in the broadest sense, any structure made of an opaque material constructed on the TFT array substrate 10 can be called an “upper light-shielding film” or an “internal light-shielding film”.

  A silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably, a TEOS gas is provided above the above-described data line 6a and below the shield layer 400. A third interlayer insulating film 43 formed by the used plasma CVD method is formed. The third interlayer insulating film 43 includes a contact hole 803 for electrically connecting the shield layer 400 and the relay layer 6a1 for a shield layer, and a third relay electrode 402 and a second relay electrode 6a2. Contact holes 804 for electrical connection are opened.

  In addition, the stress generated near the interface of the capacitor electrode 300 may be reduced by not performing the above-described firing on the first interlayer insulating film 41 on the second interlayer insulating film 42.

  Finally, on the sixth layer, the pixel electrodes 9a are formed in a matrix as described above, and the alignment film 16 is formed on the pixel electrodes 9a. Under the pixel electrode 9a, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or a fourth interlayer insulating film 44 preferably made of BPSG is formed. In the fourth interlayer insulating film 44, a contact hole 89 for electrically connecting the pixel electrode 9a and the third relay electrode 402 is formed. In the present embodiment, particularly, the surface of the fourth interlayer insulating film 44 is planarized by a CMP (Chemical Mechanical Polishing) process or the like, and a liquid crystal layer caused by a step due to various wirings, elements, and the like present below the surface. 50 misalignment is reduced. However, instead of or in addition to performing the flattening process on the fourth interlayer insulating film 44, the TFT array substrate 10, the base insulating film 12, the first interlayer insulating film 41, the second interlayer insulating film 42, A flattening process may be performed by digging a groove in at least one of the third interlayer insulating films 43 and embedding the wiring such as the data line 6a or the TFT 30 or the like.

In the electro-optical device according to the present embodiment having such a configuration, in particular, the relay electrode 719 formed as the same film as the gate electrode 3a exists as the second layer, and the storage capacitor 70 located in the third layer exists. Is characterized in that the lower electrode 71 and the pixel electrode 9a located in the sixth layer are electrically connected via the relay electrode 719.
As described above, since the lower electrode 71 and the pixel electrode 9a are connected via the relay electrode 719 located at a lower layer when viewed from each of them, an electrical connection point between the relay electrode 719 and the lower electrode 71 is formed. In particular, the electrical connection point focusing on the lower electrode 71 is located below the lower electrode 71 (see the contact hole 881 in FIG. 4).

  With such a structure, in the electro-optical device according to the present embodiment, the following operation and effect can be obtained. This point becomes clearer by assuming an electro-optical device that does not adopt the above-described structure and comparing it. Hereinafter, this will be described with reference to FIG. Here, FIG. 5 is a sectional view of the same viewpoint showing a structure for making a comparison with FIG. For convenience of description, between FIGS. 4 and 5, when substantially the same elements are designated, the description will be made using the same reference numerals. Note that this comparison is merely a comparison in the above embodiment, and this configuration is also included in the present invention.

  First, in FIG. 4, as described above, the lower electrode 71 and the relay electrode 719 are electrically connected via the contact hole 881 formed in the first interlayer insulating film 41 formed therebetween. Have been. Therefore, it can be said that the electrical connection point of the lower electrode 71 to the relay electrode 719 is located “below” the lower electrode 71.

  On the other hand, in FIG. 5, the relay electrode 719 does not exist, and therefore, the electrical connection between the lower electrode 71 'and the pixel electrode 9a is made by a contact having an electrical connection point above the lower electrode 71'. This is realized through a hole 8821. More specifically, the contact hole 8821 is opened in the second interlayer insulating film 42 and the dielectric films 75a and 75b, and the second relay electrode 6a21 is formed on the surface of the second interlayer insulating film 42 and the contact hole 8821. It can be seen that it is formed to fill. The subsequent upper layer structure is substantially the same as that of FIG.

  Then, in such a structure, in order to realize the electrical connection between the lower electrode 71 'and the pixel electrode 9a, the "upper side" of the lower electrode 71' must be used, as is apparent in FIG. It is. Accordingly, in this case, it is necessary to perform an etching process on only the dielectric film 75 and the capacitor electrode 300 constituting the storage capacitor 70 ′ (see the broken line in the figure). This is because, in order to establish electrical connection with the upper side of the lower electrode 71 ', it is necessary to bring about a state where the surface of the lower electrode 71' can be seen from above.

  However, difficulties are involved in the above-described etching process. This is because the lower electrode 71 'and the dielectric film 75 are usually formed to be as thin as possible. Further, in the present embodiment, particularly, the dielectric film 75 includes the silicon nitride film and the like as described above, and the silicon oxide film is correspondingly thinner. When the capacitor electrode 300 is formed of, for example, polysilicon, tungsten silicide, or a laminated film thereof, the etching of the capacitor electrode 300 is performed by setting the etching rate of the silicon oxide film, which is a dielectric film, to be higher than that of the capacitor electrode 300 In addition, it is possible to select an etching condition that considerably slows down the etching so that the etching of the capacitor electrode 300 stops at the dielectric film. However, when the silicon oxide film in the dielectric film becomes thinner, the etching penetrates the dielectric film, and furthermore, the pixel electrode side capacitor electrode is also easily etched. Therefore, in such a case, there is a high possibility that so-called “penetration” or the like may occur in the lower electrode 71 ′. In such a case, in the worst case, there is a possibility that a short circuit may occur between the capacitor electrode 300 and the lower electrode 71 ′ constituting the storage capacitor 70.

  However, in the present embodiment, as shown in FIG. 5, there is no need to go through such a difficult etching step, so that the electrical connection between the lower electrode 71 and the pixel electrode 9a can be satisfactorily realized. It is. This is because electrical connection between the two is realized via the relay electrode 719. Furthermore, for the same reason, according to this embodiment, the possibility that a short circuit occurs between the capacitor electrode 300 and the lower electrode 71 is extremely small. That is, it is possible to preferably form the storage capacitor 70 without defects.

  As described above, in the present embodiment, the electrical connection between the storage capacitor 70 and the pixel electrode 9a can be satisfactorily realized, and the possibility of causing unnecessary defects in the storage capacitor 70 is extremely reduced. Accordingly, it is possible to provide an electro-optical device that can perform better operations.

  In the above embodiment, the relay electrode 719 is formed as the same film as the gate electrode 3a, but the present invention is not limited to such an embodiment. For example, in the above embodiment, the storage capacitor 70 formed in the third layer may be formed in an upper layer for various reasons. In this case, the relay electrode is formed in a layer higher than the gate electrode 3a. Can also be assumed. In addition, the present invention is not limited to the above embodiment as to the three-dimensional and two-dimensional layout of each component. Various forms different from those in FIGS. 1 to 4 and the like can be considered.

  Further, in the above description, the storage capacitor 70 has a three-layer structure of a pixel potential side capacitor electrode, a dielectric film, and a fixed potential side capacitor electrode in order from the bottom. May be configured. In this case, for example, the pixel potential side capacitor electrode serving as the upper electrode has an area larger than the area of the fixed potential side capacitor electrode, that is, the former has a plane surplus surface with respect to the latter. In addition, the surplus surface may be formed so as to correspond to a position where a contact hole leading to the relay electrode 719 is formed. According to this, the electrical connection between the relay electrode 719 and the capacitor electrode on the pixel potential side can be easily realized through the contact hole.

  As described above, the “pixel potential side capacitor electrode” according to the present invention may not constitute the “lower” electrode 71 of the storage capacitor 70 (see the above embodiment), but may constitute the upper electrode thereof. .

(Manufacturing process)
Hereinafter, a method of manufacturing an electro-optical device similar to the above-described embodiment will be described with reference to FIGS. Here, FIGS. 6 and 7 are process cross-sectional views sequentially showing a method of manufacturing the electro-optical device according to the present embodiment.

First, as shown in step (1) of FIG. 6, a TFT array substrate 10 such as a quartz substrate, hard glass, or a silicon substrate is prepared. Here, annealing is preferably performed at a high temperature of about 900 to 1300 ° C. in an inert gas atmosphere such as N ₂ (nitrogen), and pre-processing is performed so that distortion generated in the TFT array substrate 10 in a high-temperature process performed later is reduced. Keep it.

  Subsequently, a metal alloy film such as a metal such as Ti, Cr, W, Ta, or Mo or a metal silicide is formed on the entire surface of the TFT array substrate 10 thus processed by sputtering to a thickness of about 100 to 500 nm. Preferably, a precursor film having a thickness of 200 nm is formed. Then, a scanning line 11a having a planar shape of a stripe is formed by photolithography and etching. Next, a TEOS (tetra-ethyl-ortho-silicate) gas, a TEB (tetra-ethyl-borate) gas, and a TMOP (tetra-methyl-oxy) gas are formed on the scanning line 11a by, for example, normal pressure or reduced pressure CVD. A silicate glass film such as NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), a silicon nitride film or a silicon oxide film using a fossate (gas) gas or the like. Then, a base insulating film 12 made of, for example, is formed. The thickness of the base insulating film 12 is, for example, about 500 to 2000 nm.

  Subsequently, under a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C., a low pressure CVD using monosilane gas, disilane gas or the like at a flow rate of about 400 to 600 cc / min (for example, pressure An amorphous silicon film is formed by CVD (about 20 to 40 Pa). Thereafter, by performing a heat treatment in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably for 4 to 6 hours, the p-Si (polysilicon) film has a thickness of about 50 to 200 nm, Preferably, the solid phase is grown to a thickness of about 100 nm. As a method for solid phase growth, annealing using RTA or laser annealing using an excimer laser or the like may be used. At this time, depending on whether the pixel switching TFT 30 is an n-channel type or a p-channel type, a dopant of a group V element or a group III element may be slightly doped by ion implantation or the like. Then, a semiconductor layer 1a having a predetermined pattern is formed by photolithography and etching.

  Next, as shown in step (2) of FIG. 6, the semiconductor layer 1a constituting the TFT 30 is thermally oxidized at a temperature of about 900 to 1300 ° C., preferably at a temperature of about 1000 ° C. to form a lower gate insulating film. In some cases, an upper gate insulating film is formed subsequently by a low pressure CVD method or the like, thereby forming an insulating film (including a gate insulating film) made of a single or multilayer high-temperature silicon oxide film (HTO film) or a silicon nitride film. Form 2 As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating film 2 has a thickness of about 20 to 150 nm, preferably about 30 to 100 nm. It will be thick.

  Subsequently, in order to control the threshold voltage Vth of the TFT 30 for pixel switching, a predetermined amount of a dopant such as boron is doped into the n-channel region or the p-channel region of the semiconductor layer 1a by ion implantation or the like. I do.

  Subsequently, a groove 12cv communicating with the scanning line 11a is formed in the base insulating film 12 described above. The groove 12cv is formed by dry etching such as reactive ion etching and reactive ion beam etching.

  Next, as shown in step (3) of FIG. 6, a polysilicon film is deposited by a low pressure CVD method or the like, and phosphorus (P) is thermally diffused to make the polysilicon film conductive. Instead of the thermal diffusion, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The thickness of the polysilicon film is about 100 to 500 nm, preferably about 350 nm. Then, a gate electrode 3a having a predetermined pattern including the gate electrode portion of the TFT 30 is formed by photolithography and etching. In the present manufacturing method, when the gate electrode 3a is formed, the side wall 3b extending therefrom is also formed at the same time. The side wall 3b is formed by depositing the above-described polysilicon film also on the inside of the trench 12cv. At this time, since the bottom of the groove 12cv is in contact with the scanning line 11a, the side wall 3b and the scanning line 11a are electrically connected. Further, in the present manufacturing method, particularly, when patterning the gate electrode 3a, the relay electrode 719 is also formed at the same time. By this patterning, the relay electrode 719 is formed to have a planar shape as shown in FIG.

  Subsequently, a low-concentration source region 1b and a low-concentration drain region 1c, and a high-concentration source region 1d and a high-concentration drain region 1e are formed on the semiconductor layer 1a.

Here, a case where the TFT 30 is an n-channel TFT having an LDD structure will be described. Specifically, first, in order to form the low-concentration source region 1b and the low-concentration drain region 1c, the gate electrode 3a is used as a mask. Dopan of a group V element such as P is doped at a low concentration (for example, P ions at a dose of 1 to 3 × 10 ¹³ cm ² ). Thereby, the semiconductor layer 1a under the gate electrode 3a becomes the channel region 1a '. At this time, the low concentration source region 1b and the low concentration drain region 1c are formed in a self-aligned manner by the gate electrode 3a serving as a mask.
Next, a resist layer having a plane pattern wider than the gate electrode 3a is formed on the gate electrode 3a in order to form the high-concentration source region 1d and the high-concentration drain region 1e. Thereafter, a dopant of a V continuation element such as P is doped at a high concentration (for example, P ions are doped at a dose of 1 to 3 × 10 ¹⁵ / cm ² ).

  Note that doping may not be performed in two stages of low concentration and high concentration. For example, a TFT having an offset structure may be used without performing low-concentration doping, and a self-aligned TFT may be formed using a gate electrode 3a (gate electrode) as a mask and an ion implantation technique using P ions, B ions, or the like. Good. The resistance of the gate electrode 3a is further reduced by the doping of the impurity.

  Next, as shown in step (4) of FIG. 6, NSG, PSG, BSG, NSG, PSG, and the like are formed on the gate electrode 3a by, for example, normal pressure or reduced pressure CVD using TEOS gas, TEB gas, TMOP gas, or the like. A first interlayer insulating film 41 made of a silicate glass film such as BPSG, a silicon nitride film, or a silicon oxide film is formed. The thickness of the first interlayer insulating film 41 is, for example, about 500 to 2000 nm. Here, preferably, annealing is performed at a high temperature of about 800 ° C. to improve the film quality of the first interlayer insulating film 41.

  Subsequently, the contact holes 83 and 881 are opened by dry etching such as reactive ion etching and reactive ion beam etching on the first interlayer insulating film 41. At this time, the former is formed so as to communicate with the high-concentration drain region 1e of the semiconductor layer 1a, and the latter is formed so as to communicate with the relay electrode 719.

  Next, as shown in step (5) of FIG. 6, a metal film such as Pt is formed on the first interlayer insulating film 41 to a thickness of about 100 to 500 nm by sputtering, and a predetermined pattern is formed. A precursor film for the lower electrode 71 is formed. At this time, the formation of the above-described metal film is performed so that both the contact hole 83 and the contact hole 881 are buried, whereby the electrical connection between the high-concentration drain region 1 e and the relay electrode 719 and the lower electrode 71 is performed. Is achieved. Subsequently, the lower electrode 71 is formed by performing a patterning process on the precursor film of the lower electrode 71.

  Subsequently, a dielectric film 75 is formed on the lower electrode 71. This dielectric film 75 can be formed by various known techniques generally used for forming a TFT gate insulating film, similarly to the case of the insulating film 2. In this embodiment, in particular, first, the silicon oxide film 75a is formed by the above-described thermal oxidation or the CVD method, and thereafter, the silicon nitride film 75b is formed by the plasma CVD method or the like. As the dielectric film 75 becomes thinner, the storage capacitance 70 becomes larger. Therefore, it is advantageous to form the dielectric film 75 into a very thin insulating film having a thickness of 50 nm or less on condition that defects such as film breakage do not occur. It is. Subsequently, a metal film of Al or the like is formed on the dielectric film 75 to a thickness of about 100 to 500 nm by sputtering to form a precursor film of the capacitor electrode 300.

    Next, as shown in step (6) of FIG. 6, without patterning the precursor film of the silicon oxide film 75a of the dielectric film 75, the precursor film of the silicon nitride film 75b is placed under the pixel potential side capacitor electrode. Patterning may be performed to a size slightly larger than the electrode 71, and only the patterning of the precursor film of the capacitor electrode 300 to be substantially the same size as the lower electrode 71 may be performed. In this case, with the formation of the capacitor electrode 300, the portion sandwiched between the capacitor electrode 300 and the above-described lower electrode 71 substantially corresponds to the dielectric film 75 (see FIG. 4). ).

  In step (6) of FIG. 7, the precursor film of the dielectric film 75 and the precursor film of the capacitor electrode 300 are patterned at a time to form the dielectric film 75 and the capacitor electrode 300, and accumulate. The capacity 70 may be completed.

  As described above, in the present embodiment, the area of the capacitor electrode 300 as the fixed potential side capacitor electrode is formed so as to be larger than the area of the lower electrode 71 and the dielectric film 75 as the pixel potential side capacitor electrode. Since the storage capacitor 70 is formed, it is possible to sandwich the dielectric film with a wider electrode area, and more specifically, it is possible to use the side surfaces of the three elements constituting the storage capacitor 70 as a capacitor. Can be expected to increase the capacitance value. That is, according to the present embodiment, it is possible to manufacture a storage capacitor having a relatively large capacitance value without having a useless planar spread, that is, without lowering the pixel aperture ratio. From such a viewpoint, if the lower electrode 71 is formed to be relatively thick, for example, the area of the side surface is increased, and the capacitance value can be efficiently obtained. In addition, as can be seen from the drawing, if such a configuration is employed, since the dielectric film 75 is formed so as to cover the lower electrode 71, a short circuit may occur between the capacitor electrode 300 and the lower electrode 71. Can also be reduced.

  Further, according to this aspect, since the patterning as described above is performed, only the fixed potential side capacitor electrode and the dielectric film are etched as in the related art, and the pixel potential side capacitor electrode located thereunder is left as it is. It does not have the difficult task of leaving it behind. As a result, according to the present invention, it is possible to easily and reliably manufacture the accumulated volume.

  Next, as shown in a step (7) of FIG. 7, for example, a silicate glass film such as NSG, PSG, BSG, BPSG, or the like by normal pressure or reduced pressure CVD using TEOS gas or the like, preferably by plasma CVD. Then, a second interlayer insulating film 42 made of a silicon nitride film, a silicon oxide film, or the like is formed. When aluminum is used for the capacitor electrode 300, it is necessary to form a film at a low temperature by plasma CVD. The thickness of the second interlayer insulating film 42 is, for example, about 500 to 1500 nm. Subsequently, contact holes 81, 801 and 882 are formed by dry etching such as reactive ion etching and reactive ion beam etching on the second interlayer insulating film. At this time, the contact hole 81 is formed so as to communicate with the high-concentration source region 1d of the semiconductor layer 1a, the contact hole 801 is formed so as to communicate with the capacitor electrode 300, and the contact hole 882 is formed so as to communicate with the relay electrode 719. You.

  Subsequently, as shown in step (8) of FIG. 7, a low-resistance metal such as Al or a metal silicide having a light-shielding property is formed on the entire surface of the second interlayer insulating Deposit to a thickness of about 500 nm, preferably about 300 nm. Then, a data line 6a having a predetermined pattern is formed by photolithography and etching. At this time, at the time of the patterning, the shield layer relay layer 6a1 and the second relay layer 6a2 are also formed at the same time. The relay layer 6a1 for the shield layer is formed so as to cover the contact hole 801 and the second relay layer 6a2 is formed so as to cover the contact hole 882. Subsequently, after a film made of titanium nitride is formed on the entire surface of the upper layer by a plasma CVD method or the like, a patterning process is performed so that this film remains only on the data line 6a (reference numeral in step (8) in FIG. 7). 41TN). However, the layer made of titanium nitride may be formed so as to remain on the relay layer 6a1 for the shield layer and the second relay layer 6a2, or may be formed so as to remain on the entire surface of the TFT array substrate 10 in some cases. May be. Alternatively, a film may be formed at the same time as the aluminum film is formed, and may be etched at a time (in this regard, the structure is slightly different from that in FIG. 4).

  Next, as shown in a step (9) of FIG. 7, a plasma CVD method capable of forming a film at a low temperature, preferably a normal pressure or reduced pressure CVD method using TEOS gas or the like, so as to cover the data lines 6a and the like. Thereby, a third interlayer insulating film 43 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the third interlayer insulating film 43 is, for example, about 500 to 1500 nm. Subsequently, contact holes 803 and 804 are formed by dry etching such as reactive ion etching and reactive ion beam etching on the third interlayer insulating film 43. At this time, the contact hole 803 is formed so as to communicate with the relay layer 6a1 for the shield layer, and the contact hole 804 is formed so as to communicate with the second relay layer 6a2.

  Subsequently, a shield layer 400 is formed on the third interlayer insulating film 43 by a sputtering method, a plasma CVD method, or the like. Here, first, a first layer is formed immediately above the third interlayer insulating film 43 from a low-resistance material such as aluminum, and then, on the first layer, for example, a titanium electrode such as titanium nitride or another pixel electrode described later. A shield layer 400 having a two-layer structure is formed by forming a second layer from a material that does not cause electrolytic corrosion with ITO constituting 9a and finally patterning both the first layer and the second layer. become. At this time, the third relay electrode 402 is also formed together with the shield layer 400.

  Subsequently, a fourth interlayer insulating film 44 made of a silicate glass film such as NSG, PSG, BSG, BPSG, or the like, a silicon nitride film, a silicon oxide film, or the like is formed by, for example, normal pressure or low pressure CVD using TEOS gas or the like. . The thickness of the third interlayer insulating film 43 is, for example, about 500 to 1500 nm. Subsequently, a contact hole 89 is formed by dry etching such as reactive ion etching or reactive ion beam etching on the third interlayer insulating film 43. At this time, the contact hole 89 is formed so as to communicate with the third relay electrode 402.

  Subsequently, a transparent conductive film such as an ITO film is deposited on the fourth interlayer insulating film 44 by sputtering or the like to a thickness of about 50 to 200 nm. Then, the pixel electrode 9a is formed by photolithography and etching. When the electro-optical device is used as a reflection type, the pixel electrode 9a may be formed of an opaque material having a high reflectance such as Al. Subsequently, after applying a coating liquid for a polyimide-based alignment film on the pixel electrode 9a, the alignment film 16 is formed by performing a rubbing process or the like so as to have a predetermined pretilt angle and in a predetermined direction. You.

  On the other hand, as the counter substrate 20, a glass substrate or the like is first prepared, and a light-shielding film as a frame is formed by, for example, sputtering metal chromium and then performing photolithography and etching. Note that these light-shielding films need not be conductive, and may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist, in addition to a metal material such as Cr, Ni, or Al.

  Thereafter, a transparent conductive film such as ITO is deposited on the entire surface of the counter substrate 20 by sputtering or the like to a thickness of about 50 to 200 nm, thereby forming the counter electrode 21. Further, after applying a coating liquid for a polyimide-based alignment film to the entire surface of the counter electrode 21, a rubbing process is performed in a predetermined direction so as to have a predetermined pretilt angle, and the alignment film 22 is formed.

  Finally, as described above, the TFT array substrate 10 on which each layer is formed and the opposing substrate 20 are bonded together with a sealing material so that the alignment films 16 and 22 face each other, and the space between the two substrates is formed by vacuum suction or the like. Then, for example, a liquid crystal obtained by mixing a plurality of types of nematic liquid crystals is sucked, and a liquid crystal layer 50 having a predetermined thickness is formed.

  The electro-optical device of the above-described embodiment can be manufactured by the manufacturing process described above.

  In the above description, the storage capacitor 70 is manufactured such that the dielectric film 75 and the capacitor electrode 300 are first formed after the lower electrode 71 is formed. After forming the precursor films of the lower electrode 71, the dielectric film 75, and the capacitor electrode 300, these may be formed by a temporary patterning process.

(Overall configuration of electro-optical device)
Hereinafter, the overall configuration of the electro-optical device according to the present embodiment configured as described above will be described with reference to FIGS. FIG. 8 is a plan view of the TFT array substrate together with the components formed thereon as viewed from the counter substrate 20, and FIG. 9 is a cross-sectional view taken along the line HH 'of FIG.

  8 and 9, in the electro-optical device according to the present embodiment, the TFT array substrate 10 and the opposing substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the opposing substrate 20, and the TFT array substrate 10 and the opposing substrate 20 are separated from each other by a seal provided in a sealing area located around the image display area 10a. The members 52 are bonded to each other.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like, and is hardened by ultraviolet light, heating, or the like in order to bond the two substrates together. In addition, if the electro-optical device according to the present embodiment is applied to a liquid crystal device that performs a small-sized enlarged display such as a projector, the distance between the two substrates (the distance between the substrates) A gap material (spacer) such as glass fiber or glass beads for setting the gap to a predetermined value is dispersed. Alternatively, such a gap material may be included in the liquid crystal layer 50 if the electro-optical device is applied to a large-sized liquid crystal device such as a liquid crystal display or a liquid crystal television that displays images at the same magnification.

  In a region outside the sealing material 52, a data line driving circuit 101 for driving the data line 6 a by supplying an image signal to the data line 6 a at a predetermined timing and an external circuit connection terminal 102 are connected to one side of the TFT array substrate 10. By supplying a scanning signal to the scanning line 11a and the gate electrode 3a at a predetermined timing, the scanning line driving circuit 104 for driving the gate electrode 3a operates along two sides adjacent to this one side. It is provided.

  If the delay of the scanning signal supplied to the scanning line 11a and the gate electrode 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area 10a.

On one remaining side of the TFT array substrate 10, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area 10a are provided.
In at least one of the corners of the counter substrate 20, a conductive material 106 for electrically connecting the TFT array substrate 10 and the counter substrate 20 is provided.

  In FIG. 9, an alignment film is formed on a pixel array 9 after TFTs for pixel switching and wiring such as scanning lines and data lines are formed on a TFT array substrate 10. On the other hand, on the counter substrate 20, an alignment film is formed on the uppermost layer in addition to the counter electrode 21. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several kinds of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Note that, on the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, etc., a sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing, a plurality of data lines 6a, a precharge circuit for supplying a precharge signal of a predetermined voltage level prior to the image signal, an inspection circuit for inspecting the quality, defects, and the like of the electro-optical device during manufacturing or shipping are formed. Is also good.

  Further, in each of the above-described embodiments, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, a driving LSI mounted on a TAB (Tape Automated Bonding) substrate is used. The connection may be made electrically and mechanically via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. For example, a TN (Twisted Nematic) mode, a VA (Vertically Aligned) mode, and a PDLC (Polymer Dispersed Liquid Crystal) are provided on the side of the opposite substrate 20 where the projected light is incident and on the side where the emitted light of the TFT array substrate 10 is emitted, respectively. A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a) mode or a normally white mode or a normally black mode.

(Electronics)
Next, an overall configuration, particularly an optical configuration, of an embodiment of a projection color display device as an example of an electronic apparatus using the electro-optical device described above in detail as a light valve will be described. FIG. 10 is a schematic cross-sectional view of the projection type color display device.

  In FIG. 10, a liquid crystal projector 1100, which is an example of a projection type color display device according to the present embodiment, prepares three liquid crystal modules each including a liquid crystal device in which a driving circuit is mounted on a TFT array substrate, and each of them has a light valve for RGB. The projector is used as 100R, 100G, and 100B. In the liquid crystal projector 1100, when the projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, three mirrors 1106 and two dichroic mirrors 1108 light components R, G, and R corresponding to the three primary colors of RGB. B, and are led to light valves 100R, 100G, and 100B corresponding to each color. In this case, in particular, the B light is guided through a relay lens system 1121 including an entrance lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are combined again by the dichroic prism 1112, and then projected as a color image on the screen 1120 via the projection lens 1114.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed within the scope of the invention or the idea that can be read from the entirety of the claims and the specification, and an electro-optical device with such a change. Also, the manufacturing method thereof and the electronic device are also included in the technical scope of the present invention. The electro-optical device can be applied to an electrophoresis device, an EL (electroluminescence) device, a device using an electron-emitting device (Field Emission Display, Surface-Conduction Electron-Emitter Display), and the like.

FIG. 2 is a circuit diagram showing an equivalent circuit such as various elements and wiring provided in a plurality of pixels in a matrix forming an image display area in the electro-optical device according to the embodiment of the present invention. FIG. 3 is a plan view of a plurality of adjacent pixel groups on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device according to the embodiment of the present invention. It is the top view which extracted only the principal part in FIG. It is AA 'sectional drawing of FIG. FIG. 5 is a partial cross-sectional view illustrating a structure for comparison with FIG. 4. FIG. 6 is a process cross-sectional view (part 1) illustrating the method of manufacturing the electro-optical device according to the embodiment of the present invention in order. FIG. 9 is a process cross-sectional view (part 2) illustrating the method of manufacturing the electro-optical device according to the embodiment of the present invention in order. FIG. 2 is a plan view of the TFT array substrate in the electro-optical device according to the embodiment of the present invention, together with the components formed thereon, viewed from the counter substrate side. FIG. 9 is a sectional view taken along line HH ′ of FIG. 8. 1 is a schematic cross-sectional view illustrating a color liquid crystal projector as an example of a projection type color display device that is an embodiment of an electronic apparatus according to the invention.

Explanation of reference numerals

3a scanning line 6a data line 9a pixel electrode 10 TFT array substrate 30 TFT
70 storage capacitor 71 lower electrode 75 dielectric film 75a silicon oxide film 75b silicon nitride film 300 capacitor electrode 400 shield layer 719 relay electrode 43 third interlayer insulating film 44 fourth interlayer insulating film 881 ... Contact hole 882 (connects lower electrode and relay electrode) Contact hole 882 (connects pixel electrode and relay electrode)

Claims (17)

A data line extending in a first direction, a scanning line extending in a second direction intersecting the data line, and an intersection area of the data line and the scanning line are arranged on the substrate. An electro-optical device in which a pixel electrode and a thin film transistor are provided as part of a stacked structure,
Further on the substrate,
A storage capacitor formed below the data line and electrically connected to the thin film transistor and the pixel electrode;
A capacitance line formed above the data line;
A first relay electrode formed in the same layer as the data line, electrically connecting a pixel potential side capacitor electrode of the storage capacitor and the pixel electrode;
A second relay electrode formed in the same layer as the data line, electrically connecting between the fixed potential side capacitor of the storage capacitor and the capacitor line;
The data line, the first relay layer, and the second relay layer each include a nitride film.   The electro-optical device according to claim 1, wherein the data line, the first relay layer, and the second relay layer include a nitride film on a conductive layer.   The electro-optical device according to claim 2, wherein the data line, the first relay layer, and the second relay layer have a three-layer structure of aluminum, a titanium nitride film, and a silicon nitride film.   4. The device according to claim 1, wherein the first relay layer is electrically connected to the pixel electrode via a third relay film formed in the same layer as the capacitor line. 5. An electro-optical device according to claim 1.   The electro-optical device according to claim 4, wherein the capacitance line and the third relay film include a nitride film on a conductive layer.   The electro-optical device according to claim 5, wherein the capacitance line and the third relay film have a three-layer structure of aluminum, a titanium nitride film, and a silicon nitride film.   7. The pixel potential side capacitor electrode is electrically connected to the first relay film via a fourth relay film formed on an insulating film on which the thin film transistor is formed. The electro-optical device according to any one of the above.   The electro-optical device according to claim 7, wherein the fourth relay film is formed of the same film as a gate electrode of the thin film transistor.   9. The scanning line according to claim 1, wherein the scanning line is provided below the thin film transistor, and is connected to a gate electrode provided on a semiconductor layer of the thin film transistor via a contact hole. An electro-optical device according to the item.   Between the pixel potential side capacitance electrode and the fixed potential side capacitance electrode of the storage capacitor, there are a plurality of layers containing different materials, one of which has a higher dielectric constant material than the other layers. The electro-optical device according to any one of claims 1 to 9, wherein the electro-optical device is a dielectric film including a layer made of:   The electro-optical device according to claim 10, wherein the dielectric film comprises a silicon oxide film and a silicon nitride film.   12. The electric device according to claim 1, wherein the capacitance line is formed of a light-shielding film, and is formed along the data line and wider than the data line. Optical device.   At least a surface of the first insulating film among the first insulating film disposed as a base of the pixel electrode and the second insulating film disposed as a base of the capacitor line has been subjected to planarization. The electro-optical device according to claim 1, wherein:   An electronic apparatus comprising the electro-optical device according to claim 1. On the substrate,
Forming a thin film transistor;
Forming a first interlayer insulating film on a gate electrode of the thin film transistor;
Forming a pixel potential side capacitor electrode, a dielectric film, and a fixed potential side capacitor electrode in order from the bottom on the first interlayer insulating film, and forming a storage capacitor;
Forming a second interlayer insulating film above the storage capacitor;
A data line electrically connected to a semiconductor layer of the thin film transistor, and a first relay electrically connected to the pixel potential side capacitor electrode, using a conductive material including a nitride film on the second interlayer insulating film. Forming a second relay film electrically connected to the film and the fixed potential side capacitance electrode;
Forming a third interlayer insulating film above the data line, the first relay film, and the second relay film;
Forming a third relay film electrically connected to the first relay film and a capacitor line electrically connected to the second relay film on the upper side of the third interlayer insulating film;
Forming a fourth interlayer insulating film above the third relay film and the capacitor line;
Forming a pixel electrode electrically connected to the third relay film above the fourth interlayer insulating film. The step of forming the storage capacitor includes:
Forming a first precursor film of the pixel potential side capacitance electrode;
Forming a second precursor film of the dielectric film above the first precursor film;
Forming a third precursor film of the fixed potential side capacitor electrode on the upper side of the second precursor film;
Patterning the first precursor film, the second precursor film, and the third precursor film at a time to form the pixel potential side capacitor electrode, the dielectric film, and the fixed potential side capacitor electrode. The method for manufacturing an electro-optical device according to claim 15, wherein: The step of forming the storage capacitor includes:
Forming a first precursor film of the pixel potential side capacitance electrode;
Patterning the first precursor film to form the pixel potential side capacitance electrode; and forming a second precursor film of the dielectric film on the upper side of the first precursor film;
Forming a third precursor film of the fixed potential side capacitor electrode on the upper side of the second precursor film;
Patterning the third precursor film to form the dielectric film and the fixed potential side capacitor electrode,
16. The electric device according to claim 15, wherein the fixed potential side capacitance electrode and the dielectric film are formed so that their areas are larger than the area of the pixel potential side capacitance electrode and the dielectric film. A method for manufacturing an optical device.

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