JP2004333619A - Image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device for displaying a screen with high resolution by reducing the memory capacity, as compared with conventional frame buffer systems. <P>SOLUTION: Background image data of high resolution are alternately on Line buffers La and Lb, by synchronizing with horizontal scanning of the display device. In addition, sprite image data with low resolution are written alternately on frame buffers Fa and Fb, in synchronization with vertical scanning of the display device. The data of the line buffers La and Lb are synchronized with the horizontal scanning to be read alternately, the data of the frame buffers Fa and Fb are synchronized with the vertical scanning to be read alternately, and each read data performs priority processing with a screen priority control circuit 15, to be output to the display device. Reduction in the memory capacity and high resolution display are attained, by concurrently using the line buffers and the frame buffers. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image display apparatus capable of realizing image display on a high-resolution monitor using a frame buffer having a small capacity.
[0002]
[Prior art]
In a system that displays an image on a monitor by a CPU, it is necessary to change display data in accordance with the frame scanning of the monitor in order to obtain a moving image effect. As a method for realizing this, there are a method of changing image data itself for each frame, and a moving image effect by controlling a display position and the like for each frame of a small unit image (hereinafter referred to as a sprite) constituting a display image. There is a way to achieve it.
[0003]
In the former, the image data transfer speed is a problem because the image data for one frame is changed, and the resolution is measured by reducing the transfer amount by compressing the image data. However, the scale of the data expansion circuit increases. This is not suitable for low-cost systems.
[0004]
The latter is mainly used when a moving image is expressed by CG (computer graphics) such as a video game, and the moving image is expressed by changing sprite attributes such as color information for the sprite display position and color code. . Although this method is not suitable for moving images with natural images such as movies, the amount of data that the CPU updates for each frame is very large for moving images such as animation compared to the method of changing the entire frame. This is particularly effective in a low-cost system with poor CPU performance. Thus, the present invention is used in a system that displays a moving image by changing a parameter when a display screen is configured without basically changing a sprite pattern.
[0005]
The attribute values of the above-mentioned sprites include, for example, the display position, the storage location of the pattern data (pattern data), the format of the pattern data (simultaneous display color number), the size of the pattern data, etc. There may be control data for producing blending effects when multiple sprites overlap when displaying sprites, or control data for display after processing the original design data such as rotation, enlargement, reduction, etc. is there.
[0006]
These attributes are stored in a table called a sprite attribute table. In the sprite type image display device, as described above, attributes such as the sprite display position and color information are controlled by the CPU, and a display screen is created according to the attributes. Therefore, a buffer for configuring the display screen is necessary. Depending on how this buffer is held, there are a line buffer method and a frame buffer method. The features and advantages / disadvantages of these two methods are as follows.
[0007]
(A) Line buffer method.
This method is a method of configuring a display screen in line units in accordance with the scan timing of the display monitor. That is, the display position data of all sprites in the sprite attribute table is checked, and after determining the sprite to be displayed on the line next to the line being scanned, the pattern data of the sprite to be displayed on the next line is acquired, By storing the pattern data at a position according to the horizontal display position on the line buffer, a display screen for the next line is configured.
[0008]
In this method, since it is only necessary to secure two lines for buffer capacity for writing and reading, the circuit scale can be reduced, which is suitable for a low-cost system. However, in this method, since the screen is configured in units of lines in accordance with the scanning of the monitor, the time for configuring the screen for one line is limited to the time for scanning one line. Therefore, there is a problem that the number of sprite display dots is limited in line units. When the display position of sprites in one screen is biased to a specific line in the screen, there is a problem that the number of sprites that can be displayed is reduced compared to an image without bias in the display position. In addition, the time during which the monitor scan is in the vertical blanking period cannot be used for the processing to create the display screen, so there is a problem that the processing time cannot be used effectively (the number of sprite displays is reduced) There is a disadvantage that it is not suitable for the system to be realized.
[0009]
(B) Frame buffer method
In this method, while the display monitor completes scanning for one frame, the display screen of the next frame is configured in a buffer corresponding to the frame size. That is, according to the attribute data of the sprite attribute table, this method forms a display screen by drawing each sprite in the frame buffer one by one.
[0010]
Since this method can effectively use the time for one frame for sprite drawing, the number of sprites that can be displayed in one frame increases. In addition, since the screen is configured in units of frames, even when sprites are biased to specific lines, they can be displayed without any problem. However, since this method requires a buffer (for reading and writing) corresponding to twice the frame size, the capacity of the frame buffer becomes very large particularly when a high-resolution screen is configured. For this reason, a method in which the frame buffer is realized by an external SDRAM is generally used. However, in this case, the bus width cannot be widened because of the limitation on the number of terminals, etc., and the transfer bandwidth is limited as compared with the SDRAM built-in. And has the disadvantage of affecting the drawing speed. On the other hand, when the frame buffer is provided inside the LSI, the problem of drawing speed can be solved, but there is a problem that the cost of the LSI is increased because the buffer capacity is large.
In addition, what is described in Patent Document 1 is known as a conventional frame buffer type image display device.
[0011]
[Patent Document 1]
JP 2002-341859 A
[0012]
[Problems to be solved by the invention]
The present invention has been made in view of the above circumstances, and its purpose is to reduce the memory capacity as compared with the conventional frame buffer system, and to perform image display capable of performing high-resolution screen display. To provide an apparatus.
[0013]
[Means for Solving the Problems]
The present invention has been made to solve the above-described problems. The invention according to claim 1 is an image display apparatus that displays an image on a display unit based on high-resolution image data and low-resolution image data. The first and second line buffers to which the high-resolution image data is written, the first and second frame buffers to which the low-resolution image data is written, and the display means in synchronization with the horizontal scanning First writing means for alternately writing high-resolution image data to the first and second line buffers, and high-resolution images in the first and second line buffers in synchronization with horizontal scanning of the display means. First reading means for alternately reading image data, and second writing for alternately writing low-resolution image data to the first and second frame buffers in synchronization with the vertical scanning of the display means A second readout means for alternately reading out low-resolution image data in the first and second frame buffers in synchronism with the vertical scanning of the display means, and the first and second readout means. An image display device comprising: display data generating means for generating display data based on the read image data.
[0014]
According to a second aspect of the present invention, in the image display device according to the first aspect, the first storage means in which the high-resolution image data and the low-resolution image data are written, and the image data in the storage means are stored. Read out the instruction data from the second storage means in which the instruction data to be instructed is written, and read out the high resolution image data from the first storage means based on the read out instruction data And a control means for reading out the low-resolution image data from the first storage means and outputting it to the second writing means. .
[0015]
According to a third aspect of the present invention, in the image display device according to the first or second aspect, the high-resolution image data is background image data, and the low-resolution image data is a moving display image. Image data.
According to a fourth aspect of the present invention, in the image display device according to any one of the first to third aspects, the display data generating means outputs images output from the first and second reading means. Priority processing means for performing priority processing on data based on a predetermined priority order is provided.
[0016]
According to a fifth aspect of the present invention, in the image display device according to any one of the first to fourth aspects, the display data generating unit is configured to add predetermined data to the image data output from the second reading unit. And an interpolation means for converting the low resolution image data into the high resolution dot number image data by performing the above interpolation processing.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
First, the basic concept of the present invention will be described. The human eye is distracted by the movement of an image with a lot of movement and is insensitive to the beauty of the pattern affected by the resolution. On the other hand, attention is paid to the fineness of the pattern for a stationary pattern. Therefore, in the present invention, a background image with little motion is displayed at a high resolution by a line buffer method, and a sprite with a lot of motion is displayed at a low resolution using a frame buffer, thereby improving the display quality of the entire screen. In addition, the total capacity of the buffer memory is reduced.
[0018]
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of an image display apparatus according to an embodiment of the present invention. In this figure, when changing the display of the background plane, the CPU 1 sets the attribute value for the background plane in the attribute value register 2 for the background plane, and sets the attribute of the display sprite whose movement changes for each frame as the sprite attribute. Set in Table 3. Here, the attribute value for the background plane includes the storage start address of the character data used for the background plane, the character data format used for the background plane (the number of bits per dot, the format in dot units, the entire character data Size).
[0019]
The sprite attribute includes
1) Sprite data storage start address,
2) Sprite data format (number of bits per dot, dot unit format, overall character data size, etc.)
3) Sprite display coordinates
Etc. The sprite attribute table 3 stores sprite attributes respectively corresponding to the sprites displayed on the monitor. Then, when drawing the sprite into the frame buffers Fa and Fb, the attribute data of all the sprites in the sprite attribute table 3 are read in order, and the character data of the sprite read from the character data storage device 8 according to the attribute data. Are stored in the frame buffers Fa and Fb. The sprite attribute table 3 is configured by a register group or SRAM.
[0020]
The sprite attribute table read control circuit 4 generates a read address in order to read the sprite attribute data stored in the frame buffers Fa and Fb from the sprite attribute table 3. The sprite attribute table read control circuit 4 has a counter that is reset for each frame by a V-SYNC (vertical synchronization signal) output from a CRTC (CRT controller) 5, and the sprite attribute data being read is character data read control. When the use in the circuit 7 and the frame buffer write control circuit 12 is finished, the counter is counted up, and the attribute data storage address of the sprite to be drawn next is generated.
[0021]
The character data read control circuit 7 generates the read address of the character data stored in the character data storage device 8 according to the following equation according to the attribute data read from the background attribute value register 2 and the sprite attribute table 3.
Character data read address for background surface = character data storage start address + character X size × next line number currently scanned + number of dots written in line buffer
Character data read address for sprite = character data storage start address + character X size × number of lines drawn in frame buffer + number of dots drawn in frame buffer
[0022]
The character data read control circuit 7 generates timing for reading character data from the character data storage device 8 in a time-sharing manner in accordance with the generated background character data read address and sprite character data read address. Further, the character data read control circuit 7 generates a signal indicating whether the read data is the data for the background surface or the data for the sprite surface, and the line buffer write control circuit 10 and the frame buffer together with the read data. Output to the write control circuit 12.
[0023]
The character data storage device 8 is a memory in which character data is stored. Usually, a mask ROM or the like is used. Here, the character data includes sprite pattern data and background data.
The line buffer write control circuit 10 includes a circuit for alternately switching the line buffers La and Lb for writing and reading in synchronization with H-SYNC (horizontal synchronization signal) output from the CRTC 5, and a character data reading control circuit 7. A control circuit that sequentially writes the read character data of the background surface into the line buffers La and Lb, and a circuit that increments the storage addresses of the line buffers La and Lb for each writing unit.
[0024]
The frame buffer write control circuit 12 switches the frame buffers Fa and Fb for writing and reading in synchronization with V-SYNC (vertical synchronization signal) of the CRTC 5, and sprite display coordinates read from the sprite attribute table 3. The character data output from the character data read control circuit 7 is converted to the frame buffer Fa, based on the write address generated by incrementing each sprite character data write unit using the frame buffer storage address generated from And a control circuit for writing to Fb. In addition, when the attribute data instructing the rotation, enlargement, reduction, etc. of the sprite is read from the sprite attribute table 3, the frame buffer write control circuit 12 processes the address and character data based on the attribute data. Then, the processed character data is written into the frame buffers Fa and Fb.
[0025]
The line buffers La and Lb are buffers for storing character data on the background surface in units of dots, and are buffers for two lines for reading and writing. One is read in synchronization with one line scan (horizontal scan) by CRTC5, the other is written, and this is repeated alternately.
[0026]
The frame buffers Fa and Fb are buffers for storing sprite character data in units of dots, and are buffers for two frames for reading and writing. One is read in synchronization with one frame scan (vertical scan) by CRTC5, the other is written, and this is repeated alternately.
[0027]
The CRT 5 is provided with a dot clock corresponding to the scan timing of the high resolution image data. The CRTC 5 generates scan timing (H-SYNC, V-SYNC) that matches a display monitor (not shown) based on the dot clock. The CRT 5 also performs read control of the sprite attribute table 3, character data read control, line buffer La and Lb write control, frame buffer Fa and Fb write control, line buffer La and Lb read control, and frame buffer. A timing signal serving as a reference for reading control of Fa and Fb is generated. The CRTC5 counts up a given dot clock, generates a H-SYNC when the predetermined number is counted, and resets the horizontal dot counter, and counts up the predetermined number. A vertical line counter is provided that generates and resets V-SYNC. The CRTC 5 supplies the horizontal dot counter count value and the vertical line counter count value to the line buffer read control circuit 11 and the frame buffer read control circuit 13, respectively.
[0028]
The line buffer read control circuit 11 generates an address for reading dot data from the line buffers La and Lb in synchronization with the scan timing of the CRTC 5. At this time, since the dot clock corresponding to the high resolution scan timing is given from the CRTC 5, the horizontal dot counter value supplied from the CRTC 5 is used as an address as it is. Then, processing of the next line is started at the timing when the horizontal dot counter value supplied from the CRTC 5 is reset by H-SYNC.
[0029]
The frame buffer read control circuit 13 generates an address for reading dot data from the frame buffers Fa and Fb in synchronization with the scan timing of the CRTC 5. The frame buffer read control circuit 13 has a function of converting the horizontal dot counter value and the vertical line counter value generated by the CRTC 5 into low-resolution coordinates. When the low resolution and the high resolution are in a horizontal and vertical relationship of, for example, 2: 1 (high resolution is 640 × 480 VGA, low resolution is 320 × 240 QVGA), that is, as shown in FIG. When the 1-dot data of the frame buffers Fa and Fb is enlarged and displayed on the monitor to 4 dots, the horizontal dot counter value and the vertical line counter value are each bit-shifted to ½ are used as read addresses. . Eventually, the counter value of the horizontal dot counter of CRTC5 is multiplied by (the number of low resolution horizontal dots / the number of high resolution horizontal dots), and the counter value of the vertical line counter is multiplied by (the number of low resolution vertical lines / the number of high resolution vertical lines). Has a function to convert. Although the frame buffers Fa and Fb have only a capacity for the low resolution, the readout timing is synchronized with the scan timing for the high resolution. Therefore, when there is a relationship between VGA and QVGA, the same data is read out by overlapping 2 dots and 2 lines. Will be. Then, the processing of the next frame is started at the timing when the vertical line counter value supplied from the CRTC 5 is reset by V-SYNC.
[0030]
The screen priority control circuit 15 is a control circuit that selects dot data read from the line buffers La and Lb and the frame buffers Fa and Fb according to a predetermined rule. For example, the dot data read from the line buffers La and Lb is selected only when the dot data read from the frame buffers Fa and Fb is allO. Thus, by filling the frame buffers Fa and Fb with all O in advance and storing the character data of the sprite that is not all O, the area where the sprite is not drawn is read from the line buffers La and Lb. High-resolution dot data for the background is displayed.
[0031]
Next, the operation of the above-described image display apparatus will be described with reference to the timing chart shown in FIG. 3 and the flowchart shown in FIG.
When the signal V-SYNC (see FIG. 3A) output from the CRTC 5 rises, the character data read control circuit 7 receives the rise and first reads the attribute value of the background plane from the background plane attribute value register 2. . Next, the internal register L is set to “1” (step Sa1 in FIG. 4), and the first row of the background surface (monitor of the monitor) is read from the character data storage device 8 based on the attribute value read from the background surface attribute value register 2. The character data of the first dot line) is read (FIG. 4, step Sa2) and output to the line buffer write control circuit 10. The line buffer write control circuit 10 sequentially writes the character data on the first line of the background surface output from the character data read control circuit 7 to the line buffer La (see FIG. 3C).
[0032]
Next, when the character data read control circuit 7 finishes reading the character data on the first line of the background surface from the character data storage device 8 (FIG. 4, step Sa3), the character data read control circuit 7 sets the internal register L to “2” (FIG. 4. Step Sa4) Next, after setting the internal register N to “1” (FIG. 4, Step Sa5), the first sprite attribute data is read from the sprite attribute table 3, and character data is read based on the read attribute data. Character data of the first sprite is read from the storage device 8 (FIG. 4, step Sa6). Then, the read character data is output to the frame buffer write control circuit 12. The frame buffer write control circuit 12 writes the character data supplied from the character data read control circuit 7 into the frame buffer Fa (see FIG. 3 (e)).
[0033]
Next, the character data read control circuit 7 reads the second sprite attribute data from the sprite attribute table 3, and reads the character data of the second sprite from the character data storage device 8 based on the read attribute data. Then, the read character data is output to the frame buffer write control circuit 12. The frame buffer write control circuit 12 writes the character data supplied from the character data read control circuit 7 into the frame buffer Fa. Hereinafter, the above process is repeated until the period of the signal V-SYNC ends.
[0034]
Next, when the period of the signal V-SYNC ends and the signal H-SYNC rises, the line buffer read control circuit 10 sequentially reads the data in the line buffer La and outputs it to the screen priority control circuit 15, The frame buffer read control circuit 13 reads the display data for the first row from the frame buffer Fb (see FIG. 3F) and outputs it to the screen priority control circuit 15. As a result, the first line of the monitor is displayed.
[0035]
When the signal H-SYNC rises, the character data read control circuit 7 reads the character data of the second line on the background surface from the character data storage device 8 (step Sb1 in FIG. 4), and sends it to the line buffer write control circuit 10. Output. The line buffer write control circuit 10 sequentially writes the character data to the line buffer Lb (see FIG. 3D). Next, the character data read control circuit 7 increments the internal register L (FIG. 4, step Sb3) after reading the character data of the second row on the background surface (FIG. 4, step Sb2). The processing at the end of the signal V-SYNC period is continued.
[0036]
That is, the next sprite attribute data is read from the sprite attribute table 3, and the character data of the next sprite is read from the character data storage device 8 based on the read attribute data (step Sb4 in FIG. 4). Then, the read character data is output to the frame buffer write control circuit 12. The frame buffer write control circuit 12 writes the character data supplied from the character data read control circuit 7 into the frame buffer Fa (see FIG. 3 (e)). Hereinafter, the above-described processing is repeated until the period of the signal H-SYNC ends.
[0037]
Next, when the signal H-SYNC rises again, the line buffer read control circuit 11 sequentially reads the data in the line buffer Lb and outputs the data to the screen priority control circuit, and the frame buffer read control circuit 13 receives the frame buffer. The display data for the second row is read from Fb (see FIG. 3F) and output to the screen priority control circuit 15. As a result, the second line of the monitor is displayed.
[0038]
When the signal H-SYNC rises, the character data read control circuit 7 reads the character data on the third line of the background surface from the character data storage device 8 (step Sb1 in FIG. 4), and sends it to the line buffer write control circuit 10. Output. The line buffer write control circuit 10 sequentially writes the character data to the line buffer Lb (see FIG. 3D). Next, the character data read control circuit 7 continues the process at the end of the previous signal H-SYNC period. That is, the next sprite attribute data is read from the sprite attribute table 3, and the character data of the next sprite is read from the character data storage device 8 based on the read attribute data (step Sb4 in FIG. 4). Then, the read character data is output to the frame buffer write control circuit 12. The frame buffer write control circuit 12 writes the character data supplied from the character data read control circuit 7 into the frame buffer Fa (see FIG. 3 (e)). When the processing of all the sprite attribute data set in the sprite attribute table 3 is completed (step Sb5 in FIG. 4), the character data read control circuit 7 increments the internal register N (step Sb6).
[0039]
Thereafter, each process described above is repeated to display the monitor.
In the above-described embodiment, the frame buffer read control circuit 13 performs processing for adapting the low resolution data in the frame buffers Fa and Fb to the high resolution of the monitor. Instead, the frame buffer Fa , Fb and the screen priority control circuit 15 may be provided with a data interpolation circuit as indicated by a broken line 20 in FIG. In this case, in the data interpolation circuit 20, for example, as shown in FIG. 5, various interpolation processes such as interpolating a dot with no data by an average value of data of upper and lower or left and right dots can be considered.
[0040]
Note that the gist of the present invention is to realize a screen having different resolutions by using a frame buffer and a line buffer in combination, so that the high resolution surface formed by the line buffer does not have to be a still image. The video screen may be constructed after taking into account the disadvantages of the line buffer.
[0041]
【The invention's effect】
As described above, according to the present invention, by using the line buffer and the frame buffer together, the memory capacity can be reduced as compared with the conventional frame buffer system, and a high-resolution screen display is performed. The effect that can be obtained. In addition, since a large number of sprites can be displayed, a variety of moving image expressions are possible.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an image display device according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining a screen by dot display displayed by the image display device.
FIG. 3 is a timing chart for explaining the operation of the image display apparatus.
FIG. 4 is a flowchart for explaining the operation of the image display apparatus.
FIG. 5 is a diagram for explaining a screen by dot display displayed by the image display device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... Background attribute value register, 3 ... Sprite attribute table, 4 ... Sprite attribute table read control circuit, 5 ... CRTC, 7 ... Character data read control circuit, 8 ... Character data storage device, 10 ... Line buffer Write control circuit 11 ... Line buffer read control circuit 12 ... Frame buffer write control circuit 13 ... Frame buffer read control circuit 15 ... Screen priority control circuit 20 ... Interpolation circuit Fa, Fb ... Frame buffer La Lb: Line buffer.

Claims (5)

In an image display device that displays an image on a display unit based on high-resolution image data and low-resolution image data,
First and second line buffers in which the high-resolution image data is written;
First and second frame buffers in which the low-resolution image data is written;
First writing means for alternately writing high-resolution image data in the first and second line buffers in synchronization with horizontal scanning of the display means;
First reading means for alternately reading high-resolution image data in the first and second line buffers in synchronization with horizontal scanning of the display means;
Second writing means for alternately writing low-resolution image data in the first and second frame buffers in synchronization with the vertical scanning of the display means;
Second reading means for alternately reading low-resolution image data in the first and second frame buffers in synchronization with the vertical scanning of the display means;
Display data generating means for generating display data based on the image data read by the first and second reading means;
An image display device comprising: First storage means in which high-resolution image data and low-resolution image data are written;
Second storage means in which instruction data indicating image data in the storage means is written;
The instruction data is read from the second storage means, and based on the read instruction data, the high-resolution image data is read from the first storage means and output to the first writing means. Control means for reading out the low-resolution image data from the first storage means and outputting it to the second writing means;
The image display apparatus according to claim 1, further comprising: The image display apparatus according to claim 1, wherein the high-resolution image data is image data of a background surface, and the low-resolution image data is image data of a moving display image. The display data generation means includes priority processing means for performing priority processing based on a predetermined priority order for the image data output from the first and second reading means. Item 4. The image display device according to any one of Items 3. The display data generating means includes interpolation means for performing predetermined interpolation processing on the image data output from the second reading means to convert low resolution image data into high resolution dot number image data. The image display device according to any one of claims 1 to 4, wherein the image display device is characterized.

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