JP4350395B2 - Progressive scan conversion method - Google Patents

Description

[0001]
The present invention relates to a progressive scan conversion how.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, an interlace (interlace) scanning method and a progressive (sequential) scanning method are known as image data scanning methods. The interlaced scanning method is a scanning method in which scanning of image data is first performed for odd fields, and then scanning of even fields is performed so as to sew between scanning lines of odd fields. It repeats alternately with a period of 60 seconds. On the other hand, unlike the interlace scanning method, the progressive scanning method is a method in which image data is scanned in order from the top without skipping scanning lines, and such scanning is repeated at a period of about 1/60 second. Therefore, in the case of the interlace scanning method, since one frame is displayed every other line, there is a problem that flicker noise is likely to occur. However, since the number of lines scanned in one field is half that of the progressive scanning method, This method has been widely used in televisions and the like because it has the advantage that the horizontal synchronization frequency can be kept low, and a high-resolution display can be expected at a relatively low price.
[0003]
However, in recent years, CRT displays (CRT: Cathode Ray Tube) for personal computers and workstations, which have been remarkably popular, use a progressive method rather than a flickering interlace method because they handle fine characters and lines. Has been. Therefore, some conversion is required to display NTSC image data, which is an interlaced signal, on a CRT display of a personal computer in a standard screen display size (VGA: Video Graphics Array).
[0004]
Several methods have been proposed as this conversion method. The following two methods are considered as methods using a VDP (VDP: Video Display Processor) which is an element for processing and displaying image data. It is done. The first method uses a correlation between fields. This is shown in FIG. This method is a method in which image data of one field such as 262 or 263 lines composed of interlace signals is written in the same frame memory across two fields and then displayed on the CRT. As shown in FIG. 6, the second method uses a correlation within a field. Similarly, image data of one field 262 or 263 lines composed of an interlace signal is converted to each line data twice. By continuously reading from the field memory, it is enlarged and displayed twice. In this method, the display is switched at intervals of about 1/60 seconds.
[0005]
[Problems to be solved by the invention]
However, in the first method, line data is alternately read in order from the top across two fields and written in the same field memory. Therefore, in a moving image, an image between adjacent lines is displayed. There was a problem that this deviation occurred and this appeared as noise. In addition, the second method does not cause the problem as in the first method, but the display is performed by switching between the two field memories. Therefore, the switching causes flicker noise to appear on the screen. It was.
[0006]
Therefore, the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a progressive scan conversion method, program, and apparatus that do not generate noise when an interlace signal is converted into a progressive signal. .
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention proposes the following means.
The present invention includes a drawing unit that generates image data in accordance with a drawing instruction from a host CPU, and a video capture unit that captures an interlace signal supplied from a video device, and the image data generated by the drawing unit and the video capture The image processing device stores the image data generated by the unit as a plurality of image planes, reads the plurality of stored image planes, gives a predetermined weight by the α blending function, and then synthesizes and supplies them to the display device A progressive scan conversion method for converting the interlace signal into a progressive signal using VDP as a first step of writing image data of an odd field of the interlace signal into a first field memory; and The image data of the even field is the second A second step of writing to the field memory; a third step of reading each line of image data written to the first field memory twice as a first plane; and writing to the second field memory A fourth step of reading each line of the image data twice as a second plane, and each of the image data of the first plane and the image data of the second plane are subjected to the predetermined function by the α blending function . A progressive scan conversion method is proposed, which has a fifth step of adding and combining these image data after assigning 0.5 as a weight.
[0010]
According to these inventions, since the two field image data are taken into different areas of the field memory, it is possible to prevent noise from occurring even for an image that moves between fields. In addition, since the image data captured in the field memory is enlarged twice so that the image data of each line is displayed twice in succession, the standard of the CRT display can be used with little image misalignment. Data can be enlarged to the screen display size. Furthermore, since each field image data enlarged twice is synthesized, flicker noise generated in the case of switching display can be prevented.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a progressive scan conversion method, program, and apparatus according to an embodiment of the present invention will be described in detail with reference to FIGS.
As shown in FIG. 1, an apparatus according to a first embodiment for realizing a progressive scan conversion method according to the present invention includes a video capture unit (data writing unit) 1, field memories 2a and 2b, and data reading. The units 3a and 3b, the addition unit 4, and the calculation unit 5 are included.
[0012]
The video capture unit 1 inputs an interlaced scanning format digital video signal (hereinafter simply referred to as an interlace signal), and the input interlace signal is referred to as an odd field in the field memory 2a and an even field in the field memory 2b. Write alternately. This writing is performed based on an interlace dot clock synchronized with the interlace signal.
[0013]
The field memories 2a and 2b are storage devices for storing image data constituting odd fields and even fields, respectively. The data reading units 3a and 3b read image data stored in the field memories 2a and 2b, respectively, and the reading is performed asynchronously with the writing. Further, the reading is performed by repeatedly reading image data of the same line twice. Further, in the data reading units 3a and 3b, the reading position is shifted by one line time (one line time in the output progressive signal), and the field memory 2a is read ahead of the field memory 2b by one line time. Note that this reading is performed based on a progressive dot clock.
[0014]
Here, the writing to the field memories 2a and 2b is performed by the video capture unit 1 taking about 1/60 second per field, and the reading is performed twice by the data reading units 3a and 3b. Although it is read repeatedly, the time of one field is the same as about 1/60 second, so if the write address and the read address are shifted by a predetermined address, the write address does not overtake the read address and There is no reverse, and continuous writing and reading are performed.
[0015]
The addition unit 4 adds the image data read from the data reading units 3a and 3b, and the calculation unit 5 halves the addition result of the addition unit 4. If the arithmetic unit 5 is realized by a shift circuit, the circuit configuration can be simplified. A progressive scanning digital video signal (hereinafter simply referred to as a progressive signal), which is an output of the calculation unit 5, is L1 / 2 → (L1 + L263) / 2 → (L2 + L263) / 2 → (L2 + L264) / 2 →. (L represents a line), and this is sent to a CRT display or the like. The head L1 / 2 is not actually displayed.
[0016]
Next, a second embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 2, an apparatus according to the second embodiment for realizing the progressive scan conversion method according to the present invention includes a VDP 10, a host CPU 11 (CPU: Central Processing Unit), an external video device 12, The display device 13 and an SDRAM 14 (SDRAM: Synchronous Dynamic Random Access Memory) used as a field and frame memory.
[0017]
The VDP 10 includes a drawing unit 15, a video capture unit 16, plane A to D data reading units 17 a to 17 d, and a mixing circuit unit 18. The VDP 10 is a general-purpose element that generates display data based on a command such as drawing input from the outside. The VDP 10 has various functions such as a drawing function, a video capture function, and an α blending function. The drawing function is a function for drawing image data on the frame memory in accordance with commands and data from the host CPU 11.
[0018]
The video capture function refers to a function of capturing an external video signal in the field memory 14 in real time. The video signal captured in the field memory 14 is read out by an appropriate plane A to D data reading unit 17a to 17d, thereby outputting an output video signal. It becomes possible. In addition, the α blending function sets an α value from 0 to 1 representing opacity in a plane unit or a pixel unit, multiplies the α value set in each plane or each pixel, and then mixes the entire image. It is a function to build data.
[0019]
The host CPU 11 is an external terminal such as a personal computer. In this embodiment, the host CPU 11 instructs the drawing unit 15 to draw, and outputs the priority (priority) of each plane to the mixing circuit unit 18. Have The external video device 12 is a device that outputs a video signal to the outside, such as a television, a video camera, or a CCD camera (CCD: Charge-Coupled Devices). The display device 13 is a CRT or the like, and displays output data from the VDP 10 on the screen.
[0020]
Next, each element constituting the VDP 10 will be described. The drawing unit 15 performs processing for writing text data, graphic data, or image data corresponding to the background into the frame memory 14 in accordance with an instruction from the host CPU 11. The video capture unit 16 performs processing of writing image data from the external video device 12 to the field memory 14. The plane A to D data reading units 17a to 17d are devices for separately displaying elements for configuring a display screen such as text, graphics, or captured image data. The image data read by the plane A to D data reading units 17a to 17d is mixed by the mixing circuit 18 according to the priority designated by the host CPU 11, and the entire image data is constructed.
[0021]
Next, a processing method for converting an interlace signal into a progressive signal using this apparatus will be described. FIG. 3 shows the principle of a processing method in the case of converting an interlace signal into a progressive signal. That is, in this method, the field data of the odd field and the field data of the even field input to the VDP 10 are enlarged and displayed twice by the process in which the designated plane data reading unit reads the same line twice, and then mixed. In the circuit unit 18, conversion is performed by combining with a predetermined α value (for example, ½). Details of this processing will be described below with reference to FIG. In the field memories 1 and 2, the reading positions are shifted by one line time, and the field memory 1 is read by one line time ahead of 2, as in the first embodiment.
[0022]
FIG. 4 shows the video capture unit 16, the plane A and B data reading units 17a and 17b, the mixing circuit unit 18, and the display device 13 over time. The direction from top to bottom shows the passage of time. For example, assuming that an interlaced television signal is input from an external video device 12 such as a television, the field data of the odd field that is input first is written in the field memory 1 within the time of field 1 ( Captured). Further, the field memories 1 and 2 are also read out by the plane A and B data reading units 17a and 17b within the time of the field 1 asynchronously with the writing operation.
[0023]
As described with reference to FIG. 3, the same line is read twice, and the reading positions of the field memories 1 and 2 are shifted by one line time as described in FIG. Further, within the time of this field 1, in the mixing circuit 18, the image data read from the plane A data reading unit 17a and the image data read from the plane B data reading unit 17b respectively have predetermined weights. It is added after being given (for example, 1/2). It should be noted that since the image data is not yet stored in the field memory 2 within the time of the field 1, the image cannot be synthesized.
[0024]
Next, the field data of the even field is written (captured) in the field memory 2 within the time of the field 2. Further, the field memories 1 and 2 are read by the plane A and B data reading units 17a and 17b within the time of this field 2 (the writing is performed asynchronously), and the plane A data reading unit 17a is read by the mixing circuit 18. The weighted addition of the output image data and the image data read from the plane B data reading unit 17b is performed in the same manner as in the field 1 time. Then, the image data input within the time of the field 1 and the image data input within the time of the field 2 are combined and displayed within the time of the field 2.
[0025]
Next, field data of the odd field is written (captured) in the field memory 1 within the time of the field 3. Further, the plane memories A and B are read by the plane A and B data reading units 17a and 17b within the time of this field 3 (performed asynchronously with the writing), and are read from the plane A data reading unit 17a by the mixing circuit 18. The weighted addition of the read image data and the image data read from the plane B data reading unit 17b is performed in the same manner as in the time periods of the fields 1 and 2. Then, the image data input within the time of the field 2 and the image data input within the time of the field 3 are combined and displayed within the time of the field 3. Hereinafter, the same thing is repeated.
[0026]
As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to these embodiments, and includes design and the like within a scope not departing from the gist of the present invention. It is. For example, in the present embodiment, the α value has been set to 0.5, but other values may be set depending on the correlation state between fields.
[0027]
【The invention's effect】
As described above, according to the present invention, after the field data of the odd field and the field data of the even field are taken into different areas of the field memory and expanded by the method of reading the same line twice, these data are read out. Since the interlace signal is converted into the progressive signal by combining the signals, there is an effect that a flicker-free image can be provided by a simple method.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a scan conversion device according to a first embodiment of the present invention.
FIG. 2 is a configuration diagram of a scan conversion device according to a second embodiment of the present invention.
FIG. 3 is a principle diagram of a scan conversion method according to a second embodiment of the present invention.
FIG. 4 is a timing chart of the scan conversion method according to the second embodiment of the present invention.
FIG. 5 is a principle diagram relating to a first conventional example.
FIG. 6 is a principle diagram relating to a second conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Video capture part, 2a, 2b ... Field memory, 3a, 3b ... Data reading part, 4 ... Addition part, 5 ... Calculation part, 10 ... VDP, 11 ... Host CPU, 12 ... external video equipment, 13 ... display device, 14 ... SDRAM, 15 ... drawing unit, 16 ... video capture unit, 17a to 17d ... planes A to D Data reading unit, 18 ... MIX (mixing circuit unit),

Claims (1)

A drawing unit that generates image data in accordance with a drawing instruction from the host CPU and a video capture unit that captures an interlace signal supplied from a video device. The image data generated by the drawing unit and the video capture unit The image data is stored as a plurality of image planes, and the stored image planes are read out, given a predetermined weight by the α blending function, and then combined and supplied to the display device as a VDP . A progressive scan conversion method for converting the interlace signal into a progressive signal,
A first step of writing image data of odd fields of the interlace signal into a first field memory;
A second step of writing even field image data of the interlace signal into a second field memory;
A third step of reading each line of the image data written in the first field memory twice as a first plane;
A fourth step of reading each line of the image data written in the second field memory twice as a second plane;
Fifth step of adding and synthesizing the image data of the first plane and the image data of the second plane after adding 0.5 as the predetermined weight by the α blending function A progressive scan conversion method comprising:

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