JP2004311675A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent a chip from being reversely mounted when the chip is mounted to a substrate by face down bonding. <P>SOLUTION: A bump electrode 15 is provided in which an anode electrode is electrically connected to the central part of a certain chip region on the element forming surface of a semiconductor substrate. A pair of bump electrodes 16, 17 are provided at positions where the bump electrode 15 is sandwiched separately. The bump electrodes 16, 17 are electrically connected to a cathode electrode. Areas of the bump electrodes 16, 17 are increased as compared with the area of the bump electrode 15. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a technology for manufacturing the same, and more particularly to a semiconductor device in which an anode electrode and a cathode electrode are formed on one main surface of a semiconductor substrate, and a technology effective when applied to a method for manufacturing the same.
[0002]
[Prior art]
In a conventional diode, first, a front electrode is formed on a surface of a semiconductor chip (hereinafter, simply referred to as a chip), and a back electrode is formed on a back surface of the semiconductor chip. Then, by bonding the back surface of the chip to one lead of the lead frame, the lead and the back surface electrode are electrically connected. On the other hand, the surface electrode and the other lead are electrically connected by wire bonding using an Au (gold) wire. Then, packaging of the diode is performed by sealing the chip, the wire, and the lead with a resin material.
[0003]
However, in recent years, from the viewpoint of cost reduction and miniaturization of diodes, an anode electrode and a cathode electrode are formed on the same surface of a semiconductor chip, and the anode electrode and the cathode electrode are mounted on a substrate without using wires and leads. Down bonding is performed (for example, see Patent Document 1).
[0004]
In this face-down bonding, a bump electrode is formed on an anode electrode and a cathode electrode formed on the same surface of a chip, and the semiconductor chip is directly connected to a wiring pattern on a substrate with the surface on which the bump electrodes are formed facing downward. Things.
[0005]
[Patent Document 1]
JP-A-2000-150918 (pages 3 to 4, FIG. 1)
[0006]
[Problems to be solved by the invention]
However, when a chip on which a diode is formed is mounted on a substrate by the face-down bonding described above, there are the following problems.
[0007]
The area of the bump electrode formed on the anode electrode is usually the same as the area of the bump electrode formed on the cathode electrode. Therefore, when the chip is mounted on the substrate by face-down bonding, a mark (cathode band) indicating the cathode electrode is made to prevent the mounting positions of the anode electrode and the cathode electrode from being mistaken. Has been confirmed. However, when the chip size is about 0.6 mm × 0.3 mm or less, it is extremely difficult to perform engraving and mounting confirmation using the engraving. For this reason, there is a problem that reverse insertion into the storage tape for storing the chips or reverse mounting at the time of mounting occurs. Diodes have the characteristic that current flows in one direction but does not flow in the opposite direction, so if they are mounted in reverse, they will not operate as a normal circuit, resulting in product failure. There is.
[0008]
An object of the present invention is to provide a semiconductor device capable of preventing reverse mounting when a chip is mounted on a substrate by face-down bonding.
[0009]
It is another object of the present invention to provide a method of manufacturing a semiconductor device that can prevent reverse mounting.
[0010]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0012]
The present invention provides: (a) a semiconductor substrate; (b) one anode electrode formed on one main surface of the semiconductor substrate; (c) a first bump electrode formed on the anode electrode; d) a pair of cathode electrodes formed on one main surface of the semiconductor substrate, and (e) a pair of second bump electrodes formed on the pair of cathode electrodes, wherein the first bump electrodes are separated from each other. A pair of the second bump electrodes are formed at positions where the second bump electrodes are sandwiched.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.
[0014]
(Embodiment 1)
In the first embodiment, the present invention is applied to a PIN diode used for an antenna switch module of a mobile communication device or a high-speed data communication device, for example.
[0015]
FIG. 1 is a cross-sectional view taken along the line AA of FIG. 2, and FIG. 2 is a plan view of the PIN diode according to the first embodiment with the element formation surface thereof facing upward.
[0016]
In FIG. 1, an intrinsic epitaxial layer (first semiconductor layer) 2 is formed on a main surface (element formation surface) of a semiconductor substrate 1 into which an n-type (first conductivity type) impurity is introduced. In this epitaxial layer 2, p-type impurities are introduced. ⁺⁺ Semiconductor layer (second semiconductor layer) 5 and n doped with n-type impurities ⁺⁺ A type semiconductor layer (third semiconductor layer) 7 is formed.
[0017]
n ⁺⁺ Type semiconductor layer 7 is formed with p layer ⁺⁺ And is formed so as to surround the periphery of the type semiconductor layer 5. ⁺⁺ Type semiconductor layer 5, intrinsic epitaxial layer 2, n ⁺⁺ The type semiconductor layer 7 forms a pin junction of the PIN diode in the first embodiment.
[0018]
p ⁺⁺ An anode electrode 10 is formed on the mold semiconductor layer 5, and a bump electrode (first bump electrode) 15 is formed on the anode electrode 10 via a bump electrode base film 14. On the other hand, n ⁺⁺ A pair of cathode electrodes 11 and 12 are formed on the mold semiconductor layer 7, and a pair of bump electrodes (second bump electrodes) are formed on the respective cathode electrodes 11 and 12 via a bump electrode base film 14. ) 16 and 17 are formed. FIG. 2 shows the shapes and arrangement positions of the bump electrodes 15, 16, 17 as viewed from above.
[0019]
In FIG. 2, the PIN diode according to the first embodiment has most of the element formation surface covered with the final protective film 13, and a bump electrode 15 electrically connected to the anode electrode 10 is formed at the center. It is desirable that the area of the bump electrode 15 be as small as possible from the viewpoint of reducing the capacitance of the PIN diode.
[0020]
On both sides of the bump electrode 15, bump electrodes 16 and 17 are formed symmetrically with the final protective film 13 interposed therebetween, and the area of the bump electrodes 16 and 17 is larger than the area of the bump electrode 15. ing. The heights from the back surface of the semiconductor substrate 1 to the top surfaces of the bump electrodes 15, 16, 17 are all the same. The term “identical” here includes a manufacturing error caused by a semiconductor manufacturing apparatus used for forming the bump electrodes 15, 16, and 17.
[0021]
As described above, the bump electrodes 16 and 17 electrically connected to the cathode electrodes 11 and 12 are provided on both sides of the bump electrode 15 electrically connected to the anode electrode 10 so as to be symmetrical. Can be prevented. That is, in the conventional PIN diode, since only one anode electrode and one cathode electrode are provided on the chip, there is a possibility that the anode diode and the cathode electrode are mounted in reverse. However, in the PIN diode according to the first embodiment, one anode electrode and one cathode electrode are provided. Since the cathode electrodes 11 and 12 which are electrically equivalent to each other are provided on both sides separated from each other, an effect is obtained in which it is not necessary to manage the directionality when mounting the chip on which the PIN diode is formed on the substrate. Therefore, it is not necessary to manage the direction when the chip is stored in the storage tape, and it is not necessary to engrave the chip to indicate the position of the cathode.
[0022]
Also, in a conventional diode in which one anode electrode and one cathode electrode are formed on a chip, if the area of the bump electrode formed on the cathode electrode is made larger than the area of the bump electrode formed on the anode electrode, When a chip is mounted using solder, a so-called Manhattan phenomenon occurs in which the chip is tilted and one of the bump electrodes is separated from the substrate due to a difference in surface tension per unit area due to the solder. That is, the bump electrode having a small area connected to the anode electrode is separated from the substrate, and a chip cannot be completely mounted. For this reason, in the conventional diode, the area of the bump electrode formed on the cathode electrode is equal to the area of the bump electrode formed on the anode electrode.
[0023]
However, the PIN diode according to the first embodiment has a structure in which bump electrodes 16 and 17 are provided on both sides of the bump electrode 15. Therefore, when the chip is mounted on the substrate using solder, it is determined whether or not the Manhattan phenomenon occurs based on the relationship between the bump electrode 16 and the bump electrode 17 instead of the relationship between the bump electrode 15 and the bump electrode 16. Therefore, if the area of the bump electrode 16 and the area of the bump electrode 17 are made the same, the so-called Manhattan phenomenon can be prevented without making the area of the bump electrode 15 and the area of the bump electrodes 16 and 17 the same. From the above, the area of the bump electrodes 16 and 17 can be made larger than that of the bump electrode 15, and the chip can be mounted on the substrate stably.
[0024]
In addition, since a pair of bump electrodes 16 and 17 can be formed in addition to the bump electrode 15 and the area of the bump electrodes 16 and 17 can be increased, an unused portion that has not been used in a conventional diode can be mounted. It can be changed to an effective area.
[0025]
Furthermore, since the PIN diode according to the first embodiment has a larger effective area when mounted than the conventional diode, it is possible to absorb variations in the amount of solder applied. In other words, even if the amount of solder applied is somewhat large, the chip body does not float on the solder, and it is possible to prevent a change in height and a change in capacitance characteristics of the diode during chip mounting.
[0026]
The case where the bump electrodes 16 and 17 are formed symmetrically with respect to the bump electrode 15 has been described. However, even if the bump electrodes 16 and 17 are not formed at the symmetrical position, the bump electrodes 15 may be separated and sandwiched. Even when the bump electrodes 16 and 17 are formed on the substrate, various effects described above can be obtained.
[0027]
Next, an example of a method for manufacturing the PIN diode according to the first embodiment will be described with reference to the drawings.
[0028]
First, a semiconductor substrate 1 into which an n-type impurity is introduced at a high concentration is prepared. Subsequently, as shown in FIG. 3, an intrinsic epitaxial layer (first semiconductor layer) 2 is formed on the main surface (device formation surface) of the semiconductor substrate 1 by using a vapor phase growth method. When growing the intrinsic epitaxial layer 2, phosphorus, which is an n-type impurity, is slightly introduced.
[0029]
Next, as shown in FIG. 4, after forming a silicon oxide film 3 on the epitaxial layer 2 by using a thermal oxidation method, a photosensitive resist film 4 is applied on the silicon oxide film 3. Then, patterning is performed by exposure and development. Patterning is performed using p ⁺⁺ This is performed so as to open the first region of the epitaxial layer 2 forming the type semiconductor layer 5. Thereafter, the silicon oxide film 3 existing in the opened first region is removed by etching.
[0030]
Subsequently, after boron (B) is introduced from the opened first region to the epitaxial layer 2 using a polyboron film (PBF), the semiconductor substrate 1 is subjected to a heat treatment to thereby introduce the introduced boron. Is diffused into the epitaxial layer 2 and p ⁺⁺ A semiconductor layer (second semiconductor layer) 5 is formed.
[0031]
Next, as shown in FIG. ⁺⁺ After removing the resist film 4 used for forming the semiconductor layer 5, a new resist film 6 is applied on the semiconductor substrate 1. Then, patterning is performed by exposing and developing the resist film 6. Patterning is performed by n ⁺⁺ This is performed so as to open the second region of the epitaxial layer 2 forming the semiconductor layer 7. This open area is p ⁺⁺ The semiconductor layer 5 is formed so as to surround the periphery of the semiconductor layer 5 at a distance. Thereafter, using the patterned resist film 6 as a mask, the silicon oxide film 3 is etched to expose the surface of the epitaxial layer 2.
[0032]
Subsequently, phosphorus or the like, which is an n-type impurity, is implanted into the exposed second region of the epitaxial layer 2 using an ion implantation method using the patterned resist film 6 as a mask. ⁺⁺ A semiconductor layer (third semiconductor layer) 7 is formed. Where n ⁺⁺ The semiconductor layer 7 is p-type via the intrinsic epitaxial layer 2. ⁺⁺ It is formed so as to surround the periphery of the semiconductor layer 5. Thus, p ⁺⁺ Semiconductor layer 5, epitaxial layer 2, n ⁺⁺ A pin junction made of the semiconductor layer 7 can be formed.
[0033]
Next, as shown in FIG. 6, after a silicon oxide film 8 is formed on the semiconductor substrate 1 by using a thermal oxidation method, a PSG (Phospho Silicate Glass) film 9 is formed by using, for example, a CVD (Chemical Vapor Deposition) method. Is deposited to form an intermediate protective film composed of the silicon oxide film 8 and the PSG film 9.
[0034]
Subsequently, as shown in FIG. 7, a resist film (not shown) is applied on the intermediate protective film and patterned, and an opening region is formed in the intermediate protective film by etching using the patterned resist film as a mask. . In the open area, p ⁺⁺ A region exposing the surface of the semiconductor layer 5; ⁺⁺ There is a region exposing the surface of the semiconductor layer 7, and n ⁺⁺ In a region where the surface of the semiconductor layer 7 is exposed, p ⁺⁺ There are two regions formed at positions sandwiching the region exposing the surface of the semiconductor layer 5 with a space therebetween.
[0035]
Next, after removing the resist film (not shown), a metal film such as an aluminum film or a tungsten film is formed on the semiconductor substrate 1 by using, for example, a sputtering method. Then, by patterning the formed metal film, an anode electrode 10 and cathode electrodes 11 and 12 are formed as shown in FIG. The anode electrode 10 has p ⁺⁺ While electrically connected to the semiconductor layer 5, the cathode electrodes 11 and 12 ⁺⁺ It is electrically connected to the semiconductor layer 7. Further, the cathode electrodes 11 and 12 are formed at such positions as to sandwich the anode electrode 10 apart. That is, the cathode electrode 11 and the cathode electrode 12 are formed on both sides of the anode electrode, respectively.
[0036]
Subsequently, silicon nitride (Si) is formed on the semiconductor substrate 1 by using, for example, a CVD method. ₃ N ₄ After forming the film, a resist film (not shown) is applied and patterned. Then, as shown in FIG. 8, a final protective film 13 is formed by etching using a patterned resist film (not shown) as a mask.
[0037]
Next, as shown in FIG. 9, for example, a Ti—Pd film is deposited on the semiconductor substrate 1 to form the bump electrode base film 14. Subsequently, after a resist film (not shown) is applied on the bump electrode base film 14, a selective opening is formed in the resist film by using a photolithography technique. Then, bump electrodes 15, 16, and 17 as shown in FIG. 1 are formed on the region where the selective opening is formed. Here, the areas of the bump electrodes 16 and 17 are formed to be larger than the area of the bump electrodes 15. Further, a bump electrode 16 and a bump electrode 17 are formed so as to sandwich the bump electrode 15 at a distance.
[0038]
The material of the bump electrodes 15, 16, 17 is selected according to the material of the electrode formed at the location where the PIN diode is mounted in the first embodiment. For example, when the material of the electrode at the mounting position is gold (Au), a copper (Cu) film is formed by using a plating method on the formation regions of the bump electrodes 15, 16, and 17, and then the surface of the copper film The bump electrodes 15, 16, 17 can be formed by forming a gold film by using a plating method. Further, after a nickel (Ni) film is formed using a plating method, a bump film 15, 16, 17 may be formed by forming a gold film on the surface of the nickel film using a plating method. . When the material of the electrode at the mounting location is formed of solder, the bump electrodes 15, 16, 17 can be formed of solder.
[0039]
Next, after removing the resist film and the bump electrode base film 14 other than the regions where the bump electrodes 15, 16, 17 are formed, the semiconductor substrate 1 is separated into individual chips by dicing. Then, by mounting the separated chip on the substrate by face-down bonding, a substrate on which a PIN diode such as an antenna switch module is mounted can be formed.
[0040]
(Embodiment 2)
In the second embodiment, for example, the present invention is applied to a variable capacitance diode used for a high-frequency module such as an antenna switch module or a voltage-controlled oscillator module of a mobile communication device or a high-speed data communication device.
[0041]
FIG. 10 is a cross-sectional view taken along the line AA of FIG. 11, and FIG. 11 is a plan view of the variable capacitance diode according to the second embodiment with the element formation surface facing upward.
[0042]
In FIG. 10, the n-type (first conductivity type) doped semiconductor substrate 20 has a main surface (element formation surface) on which n-type doped n-type impurities are introduced. ⁻ Type epitaxial layer (fourth semiconductor layer) 21 is formed. This n ⁻ In the first region of the epitaxial layer 21, n reaching the semiconductor substrate 20 ⁺⁺ A semiconductor layer (fifth semiconductor layer) 24 is formed, and n ⁺⁺ The semiconductor layer 24 has n ⁻ The impurity is introduced so as to have a relatively higher concentration than the amount of the impurity introduced into the type epitaxial layer 21. In other words, n ⁻ Type epitaxial layer 21 has n ⁺⁺ The impurity is introduced so as to have a relatively lower concentration than the semiconductor layer 24.
[0043]
Also, n ⁻ In the second region of the n-type epitaxial layer 21, n-type impurities doped with n-type ⁺⁺ A semiconductor layer (sixth semiconductor layer) 27 is formed. ⁺⁺ The amount of impurities introduced into the semiconductor layer 27 is n ⁻ The concentration is relatively higher than the amount of impurities introduced into the type epitaxial layer 21.
[0044]
n ⁺⁺ On the semiconductor layer 27, p ⁺⁺ A semiconductor layer (seventh semiconductor layer) 29 is formed, and p-type impurities are introduced. This gives p ⁺⁺ Semiconductor layer 29 and n ⁺⁺ A pn junction is formed between the semiconductor layers 27.
[0045]
n ⁺⁺ On the semiconductor layer 24, an n-type impurity ⁺⁺ A semiconductor layer (eighth semiconductor layer) 32 is formed. ⁺⁺ The semiconductor layer 32 is made of p ⁺⁺ It is formed so as to surround the periphery of the semiconductor layer 29 at a distance. n ⁺⁺ The amount of impurities introduced into the semiconductor layer 32 is n ⁻ The concentration is relatively higher than the amount of impurities introduced into the type epitaxial layer 21.
[0046]
p ⁺⁺ An anode electrode 36 is formed on the mold semiconductor layer 29, and a bump electrode (first bump electrode) 41 is formed on the anode electrode 36 via a bump electrode base film 40. On the other hand, p ⁺⁺ N surrounding the type semiconductor layer 29 at a distance ⁺⁺ A pair of cathode electrodes 37 and 38 are formed on the mold semiconductor layer 32, and on each of the cathode electrodes 37 and 38, a pair of bump electrodes (second bump electrode ) 42, 43 are formed. FIG. 11 shows the shapes and arrangement positions of the bump electrodes 42 and 43 when viewed from above.
[0047]
10 and 11, most of the chip area of the semiconductor substrate 20 is covered with the final protective film 39, and a bump electrode 41 electrically connected to the anode electrode 36 is formed at the center. Bump electrodes 42 and 43 are formed so as to sandwich the bump electrode 41 apart, and the bump electrodes 42 and 43 are electrically connected to the cathode electrodes 37 and 38, respectively.
[0048]
In this manner, the bump electrodes 42 and 43 connected to the cathode electrodes 37 and 38 are provided so as to sandwich the bump electrode 41 connected to the anode electrode 36 at a distance, thereby preventing the variable capacitance diode from being reversely mounted on the substrate. can do. That is, since the bump electrodes 42 and 43 are formed on both sides of the semiconductor substrate 20 around the bump electrode 41, even if the chip area is rotated by 180 degrees, the bump electrodes 42 and 43 are not rotated. The structure does not change just by being replaced. Then, as shown in FIG. 10, the bump electrode 42 and the bump electrode 43 are connected to each other via the cathode electrodes 37 and 38. ⁺⁺ It is connected to the semiconductor layer 32. That is, since the bump electrodes 37 and 38 are electrically equivalent, the configuration is the same as before rotation. For this reason, even if the chip cut out from the chip area of the semiconductor substrate 20 is mounted on the mounting board in a state of being rotated by 180 degrees, the chip is not mounted in the reverse direction, and the management of the direction is unnecessary.
[0049]
Similarly, it is not necessary to manage the direction when the chip is stored in the storage tape, and it is not necessary to mark the chip to indicate the position of the cathode.
[0050]
Next, an example of a method of manufacturing the variable capacitance diode according to the second embodiment will be described with reference to the drawings.
[0051]
First, a semiconductor substrate 20 into which an n-type (first conductivity type) impurity such as phosphorus (P) is introduced is prepared. Then, as shown in FIG. 12, n is formed on the main surface (device forming surface) of the semiconductor substrate 20 by using a vapor growth method. ⁻ An epitaxial layer (fourth semiconductor layer) 21 is formed.
[0052]
Subsequently, as shown in FIG. ⁻ After a silicon oxide film 22 is formed on the epitaxial layer 21 by using a thermal oxidation method, a photosensitive resist film 23 is applied on the silicon oxide film 22. The resist film 23 is patterned by exposing and developing, and the silicon oxide film 22 is etched using the patterned resist film 23 as a mask. By this etching, n ⁻ The first region of the epitaxial layer 21 is opened.
[0053]
Thereafter, an n-type impurity such as phosphorus is n-doped by ion implantation using the patterned resist film 23 as a mask. ⁻ N is introduced into the first region of the epitaxial layer 21 and n ⁺⁺ A semiconductor layer (fifth semiconductor layer) 24 is formed. This n ⁺⁺ The semiconductor layer 24 is formed so as to reach the surface of the semiconductor substrate 20. And n ⁺⁺ A silicon oxide film 25 is formed on the surface of the semiconductor layer 24 by using a thermal oxidation method.
[0054]
Next, as shown in FIG. ⁺⁺ After removing the resist film 23 used for forming the semiconductor layer 24, a resist film 26 is applied on the semiconductor substrate 20. Then, the applied resist film 26 is patterned by exposing and developing, and the silicon oxide film 22 is etched using the patterned resist film 26 as a mask. By this etching, n ⁻ The second region of the epitaxial layer 21 is opened.
[0055]
Subsequently, an n-type impurity such as phosphorus is n-doped by ion implantation using the patterned resist film 26 as a mask. ⁻ Introduced into the second region of the epitaxial layer 21, n ⁺⁺ A semiconductor layer (sixth semiconductor layer) 27 is formed.
[0056]
Then, as shown in FIG. ⁺⁺ After removing the resist film 26 used for forming the semiconductor layer 27, a resist film 28 is newly applied on the main surface of the semiconductor substrate 20. Then, the applied resist film 28 is patterned by exposing and developing, and the silicon oxide film 22 is etched using the patterned resist film 28 as a mask.
[0057]
Subsequently, a p-type impurity such as boron (B) is introduced by an ion implantation method using the patterned resist film 28 as a mask. ⁺⁺ The semiconductor layer (seventh semiconductor layer) 29 is n ⁺⁺ It is formed on the semiconductor layer 27. Then p ⁺⁺ A silicon oxide film 30 is formed on the surface of the semiconductor layer 29 by using a thermal oxidation method.
[0058]
Next, as shown in FIG. ⁺⁺ After removing the resist film 28 used in forming the semiconductor layer 29, a resist film 31 is applied on the semiconductor substrate 20. Then, the applied resist film 31 is patterned by exposing and developing, and the silicon oxide film 22 is etched using the patterned resist film 31 as a mask.
[0059]
Subsequently, an n-type impurity such as phosphorus is introduced by an ion implantation method using the patterned resist film 31 as a mask to form an n-type impurity. ⁺⁺ A semiconductor layer (eighth semiconductor layer) 32 is formed. N formed here ⁺⁺ The semiconductor layer 32 has p ⁺⁺ It is formed so as to surround the periphery of the semiconductor layer 29 at a distance. Then n ⁺⁺ A silicon oxide film 33 is formed on the surface of the semiconductor layer 32 by using a thermal oxidation method.
[0060]
Then, as shown in FIG. ⁺⁺ After removing the resist film 31 on which the semiconductor layer 32 is formed, a silicon oxide film 34 is formed on the main surface of the semiconductor substrate 20 by using a thermal oxidation method. Thereafter, a PSG film 35 is formed on the silicon oxide film 34 by using a CVD method. Thus, an intermediate protective film composed of the silicon oxide film 34 and the PSG film 35 can be formed.
[0061]
Next, as shown in FIG. 18, a resist film (not shown) is applied on the intermediate protective film, and then patterned by exposing and developing, and the intermediate protective film is etched using the patterned resist film as a mask. By this etching, p ⁺⁺ Opening reaching semiconductor layer 29 and n ⁺⁺ An opening reaching the semiconductor layer 32 is formed. Where n ⁺⁺ Two openings reaching the semiconductor layer 32 are formed, and p ⁺⁺ It is formed at a position such that the opening reaching the semiconductor layer 29 is interposed therebetween.
[0062]
Then, after removing the resist film (not shown), an aluminum film is formed on the semiconductor substrate 20 by using a sputtering method. Further, by patterning the subsequently formed aluminum film, an anode electrode 36 and cathode electrodes 37 and 38 are formed. Here, the cathode electrodes 37 and 38 are formed so as to sandwich the anode electrode 36 at a distance.
[0063]
Subsequently, as shown in FIG. 19, silicon nitride (Si) is ₃ N ₄ After the film is formed, a final protective film 39 is formed by etching using a resist film (not shown) as a mask.
[0064]
Next, as shown in FIG. 20, a Ti—Pd film is deposited on the semiconductor substrate 20 to form a bump electrode base film 40. Subsequently, after a resist film (not shown) is applied on the bump electrode base film 40, a selective opening is formed in the resist film using a photolithography technique. Then, bump electrodes 41, 42, and 43 as shown in FIG. 10 are formed on the region where the selective opening is provided. Here, the bump electrodes 42 and 43 are formed so as to sandwich the bump electrode 41 apart.
[0065]
The material of the bump electrodes 41, 42, and 43 is selected according to the material of the electrode formed at the position where the variable capacitance diode is mounted, as described in the first embodiment.
[0066]
Subsequently, after removing the resist film and the bump electrode base film 40 other than the regions where the bump electrodes 41, 42, and 43 are formed, the semiconductor substrate 20 is separated into individual chips by dicing. Then, by mounting the separated chip on the substrate by face-down bonding, a substrate on which a variable capacitance diode such as a high-frequency module is mounted can be formed.
[0067]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0068]
The present invention can be applied to a diode whose polarity is changed from that of the diode described in the above embodiment. That is, while the p-type impurity is introduced into the layer into which the n-type impurity is introduced in the above-described embodiment, the diode formed by introducing the n-type impurity into the layer into which the p-type impurity is introduced in the embodiment is also used. The invention can be applied.
[0069]
In the above-described embodiment, an example in which the present invention is applied to a PIN diode and a variable capacitance diode has been described. However, the present invention is not limited to this. The present invention can be applied to a flip-chip type diode. For example, the present invention can be applied to a Zener diode, a switching diode, a Schottky diode, and the like.
[0070]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0071]
Since the pair of cathode electrodes are formed so as to sandwich the anode electrode at a distance, it is possible to prevent reverse mounting when the chip is mounted on the substrate by face-down bonding.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a section of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a plan view showing an element formation surface of the semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 3;
FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 4;
FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 5;
FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 6;
FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 7;
FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 8;
FIG. 10 is a sectional view showing a section of a semiconductor device according to a second embodiment of the present invention;
FIG. 11 is a plan view showing an element formation surface of the semiconductor device according to the second embodiment of the present invention;
FIG. 12 is a sectional view illustrating a manufacturing step of the semiconductor device according to the second embodiment of the present invention;
FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 12;
FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 13;
FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 14;
FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 15;
FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 16;
FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 17;
FIG. 19 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 18;
FIG. 20 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 19;
[Explanation of symbols]
1 semiconductor substrate
2 Epitaxial layer (first semiconductor layer)
3 Silicon oxide film
4 Resist film
5 p ⁺⁺ Semiconductor layer (second semiconductor layer)
6 Resist film
7 n ⁺⁺ Semiconductor layer (third semiconductor layer)
8 Silicon oxide film
9 PSG film
10 Anode electrode
11 Cathode electrode
12 Cathode electrode
13 Final protective film
14 Underlayer for bump electrode
15 Bump electrode (first bump electrode)
16 Bump electrode (second bump electrode)
17 Bump electrode (second bump electrode)
20 Semiconductor substrate
21 n ⁻ Epitaxial layer (fourth semiconductor layer)
22 Silicon oxide film
23 Resist film
24 n ⁺⁺ Semiconductor layer (fifth semiconductor layer)
25 Silicon oxide film
26 Resist film
27 n ⁺⁺ Semiconductor layer (sixth semiconductor layer)
28 Resist film
29p ⁺⁺ Semiconductor layer (seventh semiconductor layer)
30 silicon oxide film
31 Resist film
32 n ⁺⁺ Semiconductor layer (eighth semiconductor layer)
33 silicon oxide film
34 silicon oxide film
35 PSG film
36 Anode electrode
37 Cathode electrode
38 Cathode electrode
39 Final protective film
40 Underlayer for bump electrode
41 Bump electrode (first bump electrode)
42 Bump electrode (second bump electrode)
43 Bump electrode (second bump electrode)

Claims (5)

A semiconductor device having an anode electrode and a cathode electrode on a main surface of a semiconductor substrate,
A semiconductor device, wherein a pair of the cathode electrodes is formed so as to sandwich the anode electrode at a distance. A semiconductor device having an anode electrode and a cathode electrode on a main surface of a semiconductor substrate,
Comprising a pair of the cathode electrodes formed so as to sandwich the anode electrode at a distance,
The semiconductor device according to claim 1, wherein the pair of cathode electrodes are formed symmetrically with respect to the anode electrode. (A) a semiconductor substrate;
(B) one anode electrode formed on the main surface of the semiconductor substrate;
(C) a first bump electrode formed on the anode electrode;
(D) a pair of cathode electrodes formed on the main surface of the semiconductor substrate;
(E) a pair of second bump electrodes formed on the pair of cathode electrodes,
A semiconductor device, wherein a pair of the second bump electrodes is formed so as to sandwich the first bump electrode at a distance. (A) preparing a semiconductor substrate into which impurities of the first conductivity type are introduced;
(B) forming an intrinsic first semiconductor layer on the semiconductor substrate;
(C) introducing an impurity of a conductivity type different from the first conductivity type into the first region of the first semiconductor layer to form a second semiconductor layer;
(D) introducing a first conductivity type impurity into a second region of the first semiconductor layer to form a third semiconductor layer surrounding the second semiconductor layer at a distance;
(E) forming an anode electrode on the second semiconductor layer;
(F) forming a pair of cathode electrodes on the third semiconductor layer so as to sandwich the anode electrode at a distance;
(G) forming a first bump electrode on the anode electrode and forming a pair of second bump electrodes on the pair of cathode electrodes;
A method of manufacturing a semiconductor device, wherein a pair of the second bump electrodes is formed so as to sandwich the first bump electrode at a distance. (A) preparing a semiconductor substrate into which impurities of the first conductivity type are introduced;
(B) forming a fourth semiconductor layer doped with a first conductivity type impurity on the semiconductor substrate;
(C) forming a fifth semiconductor layer, which is a layer in which a first conductivity type impurity is introduced into the first region of the fourth semiconductor layer and reaches the semiconductor substrate;
(D) forming a sixth semiconductor layer into which impurities of the first conductivity type are introduced in the second region of the fourth semiconductor layer;
(E) forming a seventh semiconductor layer in the fourth semiconductor layer by introducing impurities of a conductivity type different from the first conductivity type on the sixth semiconductor layer;
(F) a layer formed so as to be electrically connected to the fifth semiconductor layer by introducing a first conductivity type impurity into the fourth semiconductor layer, wherein the seventh semiconductor layer is separated from the fifth semiconductor layer; Forming an surrounding eighth semiconductor layer;
(G) forming an anode electrode on the seventh semiconductor layer;
(H) forming a pair of cathode electrodes on the eighth semiconductor layer so as to sandwich the anode electrode apart from each other;
(I) forming a first bump electrode on the anode electrode and forming a second bump electrode on the pair of cathode electrodes;
A method of manufacturing a semiconductor device, wherein a pair of the second bump electrodes is formed so as to sandwich the first bump electrode at a distance.

Images