JP2003124222A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up the responsiveness of a lateral pin diode. SOLUTION: In a lateral structure pin diode 1, after a pin junction is formed, a lead electrode 9a formed integrally with an anode electrode 9 electrically connected with a p<+> type diffusion layer 5 is disposed so as to be separated from an n<+> type diffusion layer 4. Hereby, a parasitic capacitance is prevented from being formed between the n<+> type diffusion layer 4 and the anode electrode 9, and a high speed response of the pin diode 1 is ensured by forming a bump electrode on the foregoing two electrodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effectively applied to a semiconductor device having a lateral pin junction capable of face-down bonding.

[0002]

2. Description of the Related Art In recent years, miniaturization, low power consumption, high frequency, and multiband have been rapidly progressing in digital mobile phones and the like. Therefore, a pin diode used as an antenna switch operates at a low current, has a small loss of transmission / reception power, has a small inter-terminal capacitance and a small signal leakage, and has a large impedance variation even at high frequencies. It is required not to.

By the way, in the pin diode, the back surface electrode of the pin diode having a vertical type (planar type or mesa type) structure is connected to the tab side of the lead frame,
There is a structure in which a surface electrode is wire-connected to a post side of a lead frame by a gold wire or the like and then a semiconductor chip is sealed with a molding resin.

In a pin diode, a p-type diffusion layer and an n-type diffusion layer are formed on the surface of an intrinsic layer (i layer) grown on the main surface of a semiconductor substrate, and a p-type diffusion layer and an n-type diffusion layer are formed. There is also a beam lead structure (horizontal structure) in which electrodes are formed on the respective diffusion layers.

Further, in the lateral pin diode, a p-type diffusion layer is arranged at the center of the main surface of the semiconductor chip, and i (intrinsic) surrounding the p-type diffusion layer is provided.
There is a lateral type in which a layer and an n-type diffusion layer surrounding the i-layer are concentrically arranged.

Further, there is CSP (Chip Size Package) as a package technology developed for the purpose of miniaturization, in which bump electrodes which are external terminals do not protrude in the lateral direction of the package and are arranged in the chip mounting surface, It is possible to implement down.

Regarding the above-mentioned pin diode, for example, Nikkan Kogyo Shimbun, March 20, 1999, "Semiconductor Term Dictionary," pages 123 to 124, or Denpa Shimbun, May 20, 1984, corporation It is described in "Comprehensive Electronic Components Handbook", page 179, edited by Japan Electronic Machinery Manufacturers Association.

[0008]

However, in the above-described vertical pin diode of the prior art, the surface electrode is wire-connected to the post side of the lead frame, and then the outer peripheral portion of the semiconductor chip is sealed with the molding resin. Therefore, there is a problem that the thickness of the resin is increased due to the loop height of the wire, and it becomes difficult to reduce the mounting height of the package. Further, since the wire and the lead are used, the wiring length becomes long, the inductance of the wiring becomes large, and there is a problem that the operation in the high frequency region is limited.

On the other hand, the above-mentioned prior art lateral structure pi
In the n-diode, since the electrodes are arranged laterally with respect to the main surface of the semiconductor chip, the anode electrode and the cathode electrode can be arranged on the same plane, and the bump electrodes are formed on the electrodes. CS like
There is an advantage that face-down mounting such as P can be performed.

However, in the lateral pin diode, the p-type diffusion layer located at the center of the main surface of the semiconductor chip, the i-layer surrounding the p-type diffusion layer, and the n-type diffusion layer surrounding the i-layer are concentric. In the case of adopting the lateral structure arranged in, when the anode bump electrode is provided on the p-type diffusion layer and the cathode bump electrode is provided on the n-type diffusion layer, the anode bump electrode is located at the center of the semiconductor chip, Since the cathode bump electrode is located around the semiconductor chip,
The arrangement is asymmetric with respect to the center of the semiconductor chip. For this reason, when face-down mounting is performed on the wiring board, uneven stress is generated in each bump electrode, so that the connection reliability between the bump electrode and the wiring board becomes low.

Further, an insulating film is provided on a part of the n-type diffusion layer of the semiconductor chip, a lead electrode portion extending from the anode electrode is formed on the insulating film, and an anode bump electrode is formed on the lead electrode portion. By forming the bump electrodes, the two bump electrodes can be arranged symmetrically with respect to the center of the main surface of the semiconductor chip. However, since parasitic capacitance is generated between the n-type diffusion layer and the anode electrode arranged via the insulating film, there arises a problem that high-speed response cannot be obtained.

An object of the present invention is to provide a lateral type pin diode having a lateral structure in which a parasitic capacitance does not occur when a bump electrode is formed on an extraction electrode portion integrally formed with an anode electrode, and a high-speed response is obtained. P can be obtained
to provide an in diode.

Another object of the present invention is to provide a technique capable of improving the high frequency characteristics of a lateral type pin diode.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, according to the present invention, the first semiconductor layer made of an intrinsic semiconductor is provided on the semiconductor substrate, and the third semiconductor layer of the second conductivity type is provided at the center of the surface of the first semiconductor layer. The first semiconductor layer includes a first region that surrounds the third semiconductor layer at regular intervals, a second region that forms a rectangle in the peripheral portion of the semiconductor substrate, and the first region and the second region. A first electrode that is integrally formed in a third region located between the first semiconductor layer and a first conductive type second semiconductor layer that surrounds the first semiconductor layer, and that is electrically connected to the second semiconductor layer; A second electrode electrically connected to the third semiconductor layer and a lead electrode portion that is integral with the second electrode are provided, and the lead electrode portion is formed to extend to the second region, and the first electrode is provided. Bump electrodes are formed on the electrodes and the extraction electrode portions, and Electrode is characterized by being disposed at positions symmetrical to each other with respect to the center of the main surface of the semiconductor chip.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) A semiconductor device according to the first embodiment is, for example, a pin diode 1 as shown in FIGS. 1 and 2, and FIG. 1 is a plan view of a main part showing an internal structure of the pin diode 1. FIG. 2 and FIG. 2 are cross-sectional views of main parts taken along the line AA of FIG.

The pin diode 1 of the first embodiment is
Intrinsic epitaxial layer (i layer (first semiconductor layer)) 3 grown on the surface of n-type (first conductivity type) semiconductor substrate 2 and n ⁺ formed on the surface of epitaxial layer 3
A lateral pin junction is formed by a type (first conductivity type) diffusion layer (second semiconductor layer) 4 and ap ⁺ type (second conductivity type) diffusion layer (third semiconductor layer) 5.

Further, the p ⁺ type diffusion layer 5 is located substantially at the center of the surface of the epitaxial layer 3 and is formed so as to be surrounded by the epitaxial layer 3. The n ⁺ type diffusion layer 4 is
It is located in the peripheral portion of the surface of the epitaxial layer 3 and is formed so as to surround the epitaxial layer 3. That is, on the surface of the epitaxial layer 3, the epitaxial layer 3 has a lateral structure in which it is joined to the p ⁺ type diffusion layer 5 formed inside and the n ⁺ type diffusion layer 4 formed outside.

Further, as shown in FIG.
The surface pattern of the ruled layer 3 is circular p ⁺Concentric type diffusion layer 5
A circular first region 3a surrounding a circle, a peripheral portion of the semiconductor substrate 2
And an anode bump electrode 9p to be described later is formed
Rectangular second area 3b, and first area 3a and second area
Third region 3c located between 3b and having a smaller area than those
Are formed integrally.

A surface protection film (first insulating film) 6 formed by oxidizing the epitaxial layer 3 is formed on the epitaxial layer 3. n ⁺ an upper portion of the diffusion layer 4 a cathode electrode (first electrode) 10 which is electrically connected to the n ⁺ -type diffusion layer 4 is formed, the p ⁺ -type on the top of the p ⁺ -type diffusion layer 5 An anode electrode 9 (second electrode) electrically connected to the diffusion layer 5 is formed.

Anode electrode 9 and cathode electrode 10
Is formed of a metal film such as an aluminum (Al) alloy or tungsten (W). The anode electrode 9 is formed integrally with the extraction electrode portion 9a starting from the p ⁺ type diffusion layer 5 and extending to the upper portion of the surface protective film 6 on the second region 3b of the epitaxial layer 3. Since the lead electrode portion 9a is arranged on the surface protective film 6 on the second region 3b, it is not located on the n ⁺ type diffusion layer 4.

An anode bump electrode 9p is formed on the extraction electrode portion 9a, and a cathode bump electrode 10n is formed on the cathode electrode 10. The anode bump electrode 9p and the cathode bump electrode 10n are
The semiconductor substrate 2 is arranged substantially symmetrically with respect to the line BB passing through the center of the main surface of the semiconductor substrate 2.

That is, in the pin diode 1 of the present embodiment, since the extraction electrode portion 9a is arranged above the surface protection film 6 on the second region 3b, the anode electrode 9 is n ^+.
Since it has a positional relationship apart from the type diffusion layer 4, no parasitic capacitance is generated between the n ⁺ type diffusion layer 4 and the anode electrode 9. As a result, high-speed response of the pin diode 1 can be realized.

Further, in the pin diode 1 of the first embodiment, by forming the external terminal with the bump electrode,
Since no lead or wire is required, high frequency characteristics can be improved.

Further, since the anode bump electrode 9p and the cathode bump electrode 10n are arranged substantially symmetrically with respect to the center of the main surface of the semiconductor substrate 2, they are mounted face down on a wiring board (not shown). At this time, substantially uniform stress is applied to the anode bump electrode 9p and the cathode bump electrode 10n. Therefore, the connection reliability between the two bump electrodes and the wiring board is improved.

Next, a method of manufacturing the pin diode 1 according to the present embodiment will be described with reference to FIG.
~ It demonstrates using FIG.

First, as shown in FIG.
An intrinsic epitaxial layer 3 (i layer (first semiconductor layer)) is formed on the main surface of the type (first conductivity type) semiconductor substrate 2 by an epitaxial growth method (P1), and then the surface of the epitaxial layer 3 is formed. By oxidizing
A surface protective film 6 (first insulating film) made of a silicon oxide film is formed (P2).

Next, as shown in FIG. 6, the surface protective film 6 in the region where the n ⁺ type diffusion layer 4 is to be formed is removed by dry etching using a photoresist film (not shown) as a mask. Using the resist film as a mask, an n-type impurity (for example, P
(Phosphorus)) is introduced. Subsequently, heat treatment is performed to thermally diffuse the n-type impurities to form the n ⁺ -type diffusion layer 4 (P3).

Next, after the photoresist film is removed, as shown in FIG. 7, a p ⁺ type diffusion layer 5 is formed by dry etching using a new photoresist film (not shown) as a mask. The surface protective film 6 in the region is removed, and a p-type impurity (for example, B (boron)) is introduced into the epitaxial layer 3 by the ion implantation method using this photoresist film as a mask. Then, by applying heat treatment,
This p-type impurity is thermally diffused to form the p ⁺ -type diffusion layer 5 (P4).

The surface pattern of the epitaxial layer 3 obtained by the formation of the n ⁺ type diffusion layer 4 and the p ⁺ type diffusion layer 5 described above is formed in the substantially central portion of the semiconductor substrate 2 as shown in FIG. A circular first region 3a that concentrically surrounds the formed circular p ⁺ -type diffusion layer 5, a rectangular second region 3b that is located in the peripheral portion of the semiconductor substrate 2 and on which the anode bump electrode 9p is formed, and A third region 3c located between the first region 3a and the second region 3b and having a smaller area than those is integrally formed.

Next, as shown in FIG. 8, after removing the photoresist film used for forming the p ⁺ type diffusion layer 5 described above, Al is formed on the semiconductor substrate 2 by, for example, a sputtering method.
A metal film 7 of (aluminum) alloy or W (tungsten) is deposited.

Subsequently, a photoresist film (not shown) is formed on the surface of the metal film 7, and the metal film 7 is etched by using this photoresist film as a mask, so that the structure shown in FIG.
, The cathode electrode 10 (first electrode) electrically connected to the n ⁺ type diffusion layer 4 is formed, and the p ⁺ type diffusion layer 5 is formed.
An anode electrode 9 (second electrode) electrically connected to the anode electrode 9 and an extraction electrode portion 9a which is integrated with the anode electrode 9 and extends from the p ⁺ type diffusion layer 5 to the second region 3b of the epitaxial layer 3 as a starting point. To form. (P5).

Next, as shown in FIG. 10, for example, CVD
By depositing a silicon nitride film on the semiconductor substrate 2 by the method, and further depositing a silicon oxide film on this silicon nitride film, a final surface protective film 8 (second film) made of a laminated film of silicon nitride and silicon oxide is formed. Form an insulating film (P
6).

Further, the final surface protection film 8 is patterned by a photolithography technique to expose a part of the anode electrode 9 and the cathode electrode 10 (a bump electrode forming region 11). Subsequently, after forming a bump electrode base film (not shown) made of a Ti (titanium) -Pd (palladium) film on the surface of the bump electrode formation region 11, the anode bump is formed on the bump electrode base film. The electrode 9p and the cathode bump electrode 10n are formed (P7). The anode bump electrode 9p and the cathode bump electrode 10n
The material can be selected according to the specifications. For example, when the electrode is Au (gold), a Cu (copper) or Ni (nickel) base film is deposited on the bump electrode formation region 11 by plating. Alternatively, it may be formed by further depositing a gold film on this underlayer film by a plating method.

Thereafter, the semiconductor substrate 2 is diced.
By individually separating (semiconductor chips), the pin diode 1 of the present embodiment shown in FIGS. 1 and 2 is formed (P8).

(Embodiment 2) In Embodiment 2, the high frequency characteristics of the pin diode (semiconductor device) described in Embodiment 1 are further improved. Since the members and the manufacturing process are the same as those in the first embodiment, the description of the similar members and the processes will be omitted.

FIG. 11 shows the lateral type pin of this embodiment.
FIG. 6 is a cross-sectional view of an essential part for explaining the relationship between a p ⁺ type diffusion layer 5 and a high frequency resistance in a diode.

The high frequency characteristic (rf) is the same as that of the p ⁺ type diffusion layer 5 and n ^+.
The junction area (S) is directly proportional to the distance (α) from the mold diffusion layer 4.
Since it is inversely proportional to, it is represented by rf∝α + (1 / S).

That is, when it is desired to reduce the high frequency resistance, p ⁺
The distance (α) between the type diffusion layer 5 and the n ⁺ type diffusion layer 4 is made very small, or the junction area (S) is made very large.

In the first embodiment, as shown in FIG.
As described above, the first region 3a of the epitaxial layer 3 is p⁺Type diffusion
P is because ply 5 is surrounded by concentric circles.⁺Type diffusion layer
5 and n ⁺The distance (α) from the mold diffusion layer 4 is substantially constant.

[0043] This embodiment for a lateral structure of a lateral junction area (S) is joined lengths of the p ⁺ -type diffusion layer 5 and the epitaxial layer 3 and the thickness of the p ⁺ -type diffusion layer 5 (W) (L )
Is the product of That is, the high frequency resistance depends on α + (1 / p ⁺ type diffusion layer 5 side area (W × L)).

In order to increase the thickness (W) of the p ⁺ type diffusion layer 5, it is necessary to perform heat treatment at a high temperature for a long time.

Therefore, in the second embodiment, the junction length (L) between the p ⁺ type diffusion layer 5 and the epitaxial layer 3 is increased to increase the p
By increasing the side area (W × L) of the ⁺ type diffusion layer 5,
The high frequency resistance can be made smaller than that in the first embodiment.

For example, as shown in FIG. 12, the junction length (L) between the p ⁺ type diffusion layer 5 and the epitaxial layer 3 is formed in a comb shape, and the p ⁺ type diffusion layer 5 and the n ⁺ type diffusion layer are formed. By making the interval (α) between the pin diode 4 and 4 substantially constant, the high frequency characteristics of the pin diode 12 can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the present invention, and does not depart from the gist of the invention. It goes without saying that various changes can be made with.

For example, in the present embodiment, the p ⁺ type diffusion layer 5 is formed by B (boron) diffusion, but instead of this, Zn (zinc) diffusion may be performed.

[0049]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows. (1) The extraction electrode portion formed integrally with the anode electrode is n
⁺ By forming away -type diffusion layer, the parasitic capacitance between the n ⁺ -type diffusion layer and the anode electrode is not generated, thereby it is possible to realize a high-speed response. (2) By increasing the junction length between the p ⁺ -type diffusion layer and the epitaxial layer and making the interval between the p ⁺ -type diffusion layer and the n ⁺ -type diffusion layer substantially constant, the high frequency characteristics can be improved.

[Brief description of drawings]

FIG. 1 is a main part plan view showing an internal structure which is an example of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a main-portion cross-sectional view showing an example of the semiconductor device in accordance with the first embodiment of the present invention.

FIG. 3 is a main part plan view showing an example of a surface pattern of an epitaxial layer of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process flow chart showing an example of manufacturing steps of the semiconductor device shown in FIG. 2;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step according to the present embodiment, following FIG. 4;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step according to the present embodiment, following FIG. 5;

7 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process according to the present embodiment, which is subsequent to FIG. 6;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step according to the present embodiment, following FIG. 7;

9 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process according to the present embodiment, which is subsequent to FIG. 8;

10 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof according to the present embodiment, which is subsequent to FIG. 9;

FIG. 11 is a diagram showing a semiconductor device according to a second embodiment of the present invention
FIG. 4 is a cross-sectional view of an essential part for explaining the relationship between ⁺ type diffusion layer 5 and high frequency resistance.

FIG. 12 shows p of a semiconductor device according to a second embodiment of the present invention.
FIG. 4 is a plan view of a main part showing an example of formation of a ⁺ type diffusion layer.

[Explanation of symbols]

1 pin diode (semiconductor device) 2 n type (first conductivity type) semiconductor substrate (semiconductor chip) 3 epitaxial layer (i layer (first semiconductor layer)) 3a first region 3b second region 3c third region 4 n ⁺ Type (first conductivity type) diffusion layer (second semiconductor layer) 5 p ⁺ type (second conductivity type) diffusion layer (third semiconductor layer) 6 Surface protective film (first insulating film) 7 Metal film 8 Final surface protection Film (second insulating film) 9 Anode electrode (second electrode) 9a Extraction electrode part 9p Anode bump electrode 10 Cathode electrode (first electrode) 10n Cathode bump electrode 11 Bump electrode formation region 12 Pin diode (semiconductor device) P1 P8 step α P ⁺ type diffusion layer 5 and n ⁺ type diffusion layer 4 distance W p ⁺ type diffusion layer 5 thickness L p ⁺ type diffusion layer 5 junction length

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shinji Naito             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Shuichi Suzuki             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F term (reference) 4M104 BB02 BB18 CC01 DD16 DD52                       DD53 DD63 EE02 EE06 EE12                       EE16 EE17 FF11 FF13 GG02                       HH20                 5F044 QQ02 QQ03 QQ04

Claims (3)

[Claims] 1. A first substrate made of an intrinsic semiconductor on a semiconductor substrate.
A semiconductor layer is provided, a second conductive type third semiconductor layer is provided in a central portion of a surface of the first semiconductor layer, and the first semiconductor layer surrounds the third semiconductor layer at a constant interval. And a second rectangular part formed on the periphery of the semiconductor substrate.
A first region formed integrally with a region and a third region located between the first region and the second region and surrounding the first semiconductor layer;
A second semiconductor layer of conductivity type is provided, and is integrally formed with a first electrode electrically connected to the second semiconductor layer, a second electrode electrically connected to the third semiconductor layer, and the second electrode. A semiconductor device, wherein a certain extraction electrode portion is provided, the extraction electrode portion is formed to extend to the second region, and bump electrodes are formed on the first electrode and the extraction electrode portion. 2. A first semiconductor comprising an intrinsic semiconductor on a semiconductor substrate.
A semiconductor layer is provided, a second conductive type third semiconductor layer is provided in a central portion of a surface of the first semiconductor layer, and the first semiconductor layer surrounds the third semiconductor layer at a constant interval. And a second rectangular part formed on the periphery of the semiconductor substrate.
A first region formed integrally with a region and a third region located between the first region and the second region and surrounding the first semiconductor layer;
A second semiconductor layer of conductivity type is provided, and is integrally formed with a first electrode electrically connected to the second semiconductor layer, a second electrode electrically connected to the third semiconductor layer, and the second electrode. A semiconductor chip in which a certain extraction electrode portion is provided, the extraction electrode portion is formed to extend to the second region, and bump electrodes are formed on the first electrode and the extraction electrode portion. The semiconductor device is characterized in that the electrodes are arranged at positions symmetrical to each other with respect to the center of the main surface of the semiconductor chip. 3. A first substrate made of an intrinsic semiconductor on a semiconductor substrate.
A semiconductor layer is provided, a second conductive type third semiconductor layer is provided in a central portion of a surface of the first semiconductor layer, and the first semiconductor layer surrounds the third semiconductor layer at a constant interval. And a second rectangular part formed on the periphery of the semiconductor substrate.
A first region formed integrally with a region and a third region located between the first region and the second region and surrounding the first semiconductor layer;
A second semiconductor layer of conductivity type is provided, and is integrally formed with a first electrode electrically connected to the second semiconductor layer, a second electrode electrically connected to the third semiconductor layer, and the second electrode. A semiconductor chip in which a certain extraction electrode portion is provided, the extraction electrode portion is formed to extend to the second region, and bump electrodes are formed on the first electrode and the extraction electrode portion. The electrodes are arranged symmetrically with respect to the center in the main surface of the semiconductor chip, and the outer periphery of the third semiconductor layer is long like a comb tooth.