CN114496812A - Power semiconductor device, preparation method thereof and radio frequency power amplifier - Google Patents

Power semiconductor device, preparation method thereof and radio frequency power amplifier Download PDF

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Publication number
CN114496812A
CN114496812A CN202111682546.6A CN202111682546A CN114496812A CN 114496812 A CN114496812 A CN 114496812A CN 202111682546 A CN202111682546 A CN 202111682546A CN 114496812 A CN114496812 A CN 114496812A
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semiconductor substrate
layer
electrode
metal layer
power semiconductor
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李海滨
许明伟
樊晓兵
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Shenzhen Huixin Communication Technology Co ltd
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Shenzhen Huixin Communication Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device

Abstract

The invention discloses a power semiconductor device, a preparation method thereof and a radio frequency power amplifier, wherein the power semiconductor device comprises a semiconductor substrate, a medium passivation layer, an input electrode metal layer, an output electrode metal layer, a grounding electrode metal layer and a device structure layer with an input electrode, an output electrode and a grounding electrode; the device structure layer covers the front surface of the semiconductor substrate; the dielectric passivation layer covers the surface of one side of the device structure layer, which is back to the semiconductor substrate; the grounding electrode metal layer covers the surface of one side of the dielectric passivation layer, which is opposite to the device structure layer, and is electrically connected with the grounding electrode; the input electrode metal layer covers the first area of the semiconductor substrate and is electrically connected with the input electrode; the output electrode metal layer covers the second area of the semiconductor substrate and is electrically connected with the output electrode; the setting area of the semiconductor substrate is exposed. The power semiconductor device disclosed by the invention has the advantage of good heat dissipation performance.

Description

Power semiconductor device, preparation method thereof and radio frequency power amplifier
Technical Field
The invention relates to the technical field of semiconductors, in particular to a power semiconductor device, a preparation method thereof and a radio frequency power amplifier.
Background
The new generation of wireless communication technology adopts a higher carrier communication frequency band, the original radio frequency power amplifier for the base station is a technical scheme based on an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device, the requirement of the new generation of technology cannot be met because the working frequency of the LDMOS is close to the limit, and the gallium nitride radio frequency power amplifier technology becomes a substitute technology of the radio frequency power amplifier for the new generation of wireless communication base station because of higher power frequency, higher power density and higher efficiency. Since the power consumption of the rf power semiconductor device is very large during operation, heat dissipation is often a concern during the design of the rf power semiconductor device.
In the related art, a third-generation semiconductor gallium nitride material with high quality is directly grown and deposited on a silicon substrate, and the manufacturing cost of a gallium nitride device can be greatly reduced by means of a large-size and low-cost silicon wafer and an automatic process line thereof, however, because the thermal conductivity of silicon is poor, even if the gallium nitride wafer based on the silicon substrate is thinned as much as possible, the thermal resistance of the gallium nitride wafer is still large, and excellent heat dissipation performance is difficult to obtain.
The above-mentioned contents are only the techniques known to the inventor of the present application, and are only used for assisting understanding of the technical solution of the present application, and do not represent an admission that the above-mentioned contents are the prior art.
Disclosure of Invention
The invention mainly aims to provide a power semiconductor device and a preparation method thereof, and aims to solve the technical problem that the existing radio-frequency power semiconductor device based on a silicon substrate is poor in heat dissipation capability.
In order to achieve the above object, the present invention provides a method for manufacturing a power semiconductor device, comprising the following steps:
manufacturing a device structure layer on the front surface of the semiconductor substrate; the device structure layer comprises an input electrode, an output electrode and a grounding electrode, and the device structure layer covers the front surface of the semiconductor substrate;
manufacturing a medium passivation layer on the device structure layer; wherein the medium passivation layer covers one side surface of the device structure layer, which faces away from the semiconductor substrate;
manufacturing a grounding electrode opening corresponding to the grounding electrode on the surface of one side, back to the device structure layer, of the dielectric passivation layer; wherein the grounding electrode opening penetrates through the dielectric passivation layer and exposes the grounding electrode;
manufacturing a grounding electrode metal layer on the medium passivation layer; the grounding electrode metal layer covers the surface of one side, back to the device structure layer, of the dielectric passivation layer, and is connected with the grounding electrode after the grounding electrode metal layer fills the grounding electrode opening;
thinning the semiconductor substrate from the back side of the semiconductor substrate; the thinned semiconductor substrate is thicker than the dielectric passivation layer;
manufacturing an input electrode opening corresponding to the input electrode and an output electrode opening corresponding to the output electrode on the back surface of the thinned semiconductor substrate; the input electrode opening penetrates through the semiconductor substrate and exposes the input electrode, and the output electrode opening penetrates through the semiconductor substrate and exposes the output electrode;
manufacturing a metal covering layer on the back surface of the semiconductor substrate; the metal covering layer covers the back surface of the semiconductor substrate, is filled in the input electrode open hole and then is connected with the input electrode, and is filled in the output electrode open hole and then is connected with the output electrode;
and removing part of the metal covering layer in the set area to form an input electrode metal layer connected with the input electrode and an output electrode metal layer connected with the output electrode on the back surface of the semiconductor substrate, and exposing the back surface of the semiconductor substrate in the set area.
Further, after the step of removing a portion of the metal covering layer in the setting region, the method further includes:
and attaching the grounding electrode metal layer to a prepared tube shell of the packaging tube.
Further, after the step of removing a portion of the metal covering layer in the setting region, the method further includes:
and respectively welding metal leads on the input electrode metal layer and the output electrode metal layer.
Further, the material of the semiconductor substrate is any one of silicon, gallium nitride, gallium arsenide, silicon carbide and sapphire.
Further, the device structure layer is any one of a Si LDMOS device, an integrated circuit including the Si LDMOS device, a GaN HEMT device, an integrated circuit including the GaN HEMT device, a GaAs HEMT device, an integrated circuit including the GaAs HEMT device, a GaAs HBT device, and an integrated circuit including the GaAs HBT device.
Further, the material of the dielectric passivation layer is any one of silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass and borophosphosilicate glass.
Furthermore, the thickness of the thinned semiconductor substrate is 300-500 microns.
Further, the thickness of the medium passivation layer is 0.8-2.5 micrometers.
Furthermore, the thickness of the grounding electrode metal layer is 2-8 microns.
Furthermore, the thickness of the input pole metal layer is 2-8 microns, and the thickness of the output pole metal layer is 2-8 microns.
In order to achieve the above object, the present invention further provides a power semiconductor device, which is prepared by the preparation method of the power semiconductor device.
To achieve the above object, the present invention also provides a power semiconductor device, including:
the back surface of the semiconductor substrate is provided with a first area, a second area and a set area, the set area is positioned between the first area and the second area, and the set area is exposed;
a device structure layer having an input electrode, an output electrode, and a ground electrode, the device structure layer overlying the front surface of the semiconductor substrate;
the dielectric passivation layer covers one side surface, back to the semiconductor substrate, of the device structure layer;
the grounding electrode metal layer covers the surface of one side, back to the device structure layer, of the dielectric passivation layer, and is electrically connected with the grounding electrode;
the input electrode metal layer covers the first area of the semiconductor substrate and is electrically connected with the input electrode;
and the output electrode metal layer covers the second area of the semiconductor substrate and is electrically connected with the output electrode.
Furthermore, the power semiconductor device further comprises a packaging tube, and a tube shell of the packaging tube is attached to the grounding electrode metal layer.
Furthermore, the power semiconductor device further comprises a first metal lead and a second metal lead, wherein one end of the first metal lead is welded with the input electrode metal layer, and one end of the second metal lead is welded with the output electrode metal layer.
Furthermore, the power semiconductor device further comprises a bonding layer, the bonding layer covers the surface of one side, back to the medium passivation layer, of the grounding electrode metal layer, and the tube shell of the packaging tube is attached to the grounding electrode metal layer through the bonding layer.
Furthermore, a grounding electrode opening corresponding to the grounding electrode is formed in the medium passivation layer, a first conductive connecting portion is arranged on one side, facing the medium passivation layer, of the grounding electrode metal layer, and the first conductive connecting portion penetrates through the grounding electrode opening and then is electrically connected with the grounding electrode.
Furthermore, an input electrode opening corresponding to the input electrode and an output electrode opening corresponding to the output electrode are formed in the semiconductor substrate, a second conductive connecting portion is arranged on one side, facing the semiconductor substrate, of the input electrode metal layer, a third conductive connecting portion is arranged on one side, facing the semiconductor substrate, of the output electrode metal layer, the second conductive connecting portion penetrates through the input electrode opening and then is electrically connected with the input electrode, and the third conductive connecting portion penetrates through the output electrode opening and then is electrically connected with the output electrode.
Further, the material of the semiconductor substrate is any one of silicon, gallium nitride, gallium arsenide, silicon carbide and sapphire.
Further, the device structure layer is any one of a Si LDMOS device, an integrated circuit including the Si LDMOS device, a GaN HEMT device, an integrated circuit including the GaN HEMT device, a GaAs HEMT device, an integrated circuit including the GaAs HEMT device, a GaAs HBT device, and an integrated circuit including the GaAs HBT device.
Further, the material of the dielectric passivation layer is any one of silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass and borophosphosilicate glass.
Further, the thickness of the semiconductor substrate is 300-500 microns.
Furthermore, the thickness of the medium passivation layer is 0.8-2.5 micrometers.
Furthermore, the thickness of the grounding electrode metal layer is 2-8 microns.
Furthermore, the thickness of the input pole metal layer is 2-8 microns, and the thickness of the output pole metal layer is 2-8 microns.
In order to achieve the above object, the present invention further provides a radio frequency power amplifier, which includes the aforementioned power semiconductor device.
Compared with the prior art, the invention has the beneficial effects that:
the technical scheme of the invention is that the grounding electrode metal layer is arranged on one side of the front surface of the semiconductor substrate, and the input electrode metal layer and the output electrode metal layer are arranged on one side of the back surface of the semiconductor substrate, the grounding electrode metal layer is only needed to be attached to the tube shell of the packaging tube, and the input electrode metal layer and the output electrode metal layer are electrically connected with other components in a routing mode, since the thickness of the dielectric passivation layer on the front side of the device structure layer is small and much smaller relative to the thickness of the semiconductor substrate, therefore, the thermal resistance of heat generated in the working process of the structural layer of the device in the process of conducting through the heat conducting path of the dielectric passivation layer-tube shell is smaller than that of heat generated in the process of conducting through the heat conducting path of the substrate-tube shell in the prior art, so that the heat dissipation effect of the device can be effectively improved; moreover, because the thickness of the semiconductor substrate positioned on the back side of the device structure layer is larger and much larger than that of the medium passivation layer, the heat generated in the working process of the device structure layer can be radiated through the semiconductor substrate with larger radiation heat radiation volume in the process of conducting through a heat radiation path with surface radiation, and the heat radiation effect of the device can be further improved; moreover, the thickness of the thinned semiconductor substrate is thicker than that of the substrate obtained by adopting the conventional technology, so that the volume of the whole power semiconductor device is increased, and the heat capacity of the whole power semiconductor device is increased, so that the lower junction temperature of the device can be obtained under the condition of the same heat productivity; therefore, even if the silicon substrate with poor heat conductivity is adopted as the semiconductor substrate, the manufactured power semiconductor device based on the silicon substrate can obtain excellent heat dissipation performance, so that the power semiconductor device can be applied to high-power semiconductor devices such as radio-frequency power amplifiers for base stations with strict heat dissipation performance requirements, and the technical problem that the existing radio-frequency power semiconductor device based on the silicon substrate cannot be applied to the radio-frequency power amplifiers for the base stations due to poor heat dissipation performance is effectively solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 to fig. 10 are sectional views of specific process steps of a method for manufacturing a power semiconductor device according to an embodiment of the present invention, in which:
fig. 1 is a cross-sectional view of a device structure layer obtained by a method for manufacturing a power semiconductor device according to the present invention;
FIG. 2 is a cross-sectional view of a dielectric passivation layer obtained by a method for fabricating a power semiconductor device according to the present invention;
FIG. 3 is a cross-sectional view of a power semiconductor device according to the present invention after a ground electrode is perforated;
FIG. 4 is a cross-sectional view of a ground metal layer obtained by the method of the present invention;
fig. 5 is a cross-sectional view of a thinned semiconductor substrate obtained by a method of manufacturing a power semiconductor device according to the present invention;
FIG. 6 is a cross-sectional view of an input electrode opening and an output electrode opening made by a method of fabricating a power semiconductor device according to the present invention;
fig. 7 is a cross-sectional view of a metal cap layer obtained by the method for manufacturing a power semiconductor device according to the present invention;
fig. 8 is a cross-sectional view of a power semiconductor device obtained by the method for manufacturing a power semiconductor device according to the present invention;
fig. 9 is a cross-sectional view of a power semiconductor device after being packaged by a method for manufacturing a power semiconductor device according to the present invention;
fig. 10 is a cross-sectional view of a packaged power semiconductor device after wire bonding by using the method for manufacturing a power semiconductor device of the present invention.
The reference numbers illustrate:
1-semiconductor substrate, 11-input pole open pore, 12-output pole open pore;
2-device structure layer, 21-input electrode, 22-output electrode, 23-ground electrode;
3-dielectric passivation layer, 31-opening of grounding electrode;
4-ground metal layer, 41-first conductive connection;
5-metal cap, 51-input pole metal layer, 511-second conductive connection, 52-output pole metal layer, 521-third conductive connection;
6-a bonding layer;
7-a tube shell;
81-first metal lead, 82-second metal lead.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture, and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, if the meaning of "and/or", "and/or" and/or "appears throughout this document, it includes three parallel schemes, such as" a and/or B ", including a scheme, or B scheme, or a scheme satisfied by both a and B. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
At present, a third generation semiconductor gallium nitride material with high quality is directly grown and deposited on a silicon substrate, the manufacturing cost of a gallium nitride device can be greatly reduced by means of a large-size and low-cost silicon wafer and an automatic process line thereof, however, because the thermal conductivity of silicon is poor, even if the gallium nitride wafer based on the silicon substrate is thinned as much as possible, the thermal resistance of the gallium nitride wafer is still larger, and excellent heat dissipation performance is difficult to obtain.
In order to solve the technical problem that the conventional radio frequency power semiconductor device based on a silicon substrate cannot be applied to a radio frequency power amplifier for a base station due to poor heat dissipation capacity, referring to fig. 1 to 10, an embodiment of the present invention provides a method for manufacturing a power semiconductor device, including the following steps:
step S11, fabricating a device structure layer 2 on the front surface of the semiconductor substrate 1; wherein the device structure layer 2 comprises an input electrode 21, an output electrode 22 and a ground electrode 23, and the device structure layer 2 covers the front surface of the semiconductor substrate 1;
in this step S11, specifically, referring to fig. 1, the device structure layer 2 may be fabricated on the front surface of the semiconductor substrate 1 by using a semiconductor device fabrication process mature in the art, where the device structure layer 2 may be a GaN HEMT (i.e., a gallium nitride high electron mobility transistor) device, an integrated circuit including a GaN HEMT device, a GaAs HEMT (i.e., a gallium arsenide high electron mobility transistor) device, an integrated circuit including a GaAs HEMT device, a Si LDMOS (i.e., a silicon laterally diffused metal oxide semiconductor) device, an integrated circuit including a Si LDMOS device, a GaAs HBT (i.e., a gallium arsenide heterojunction bipolar transistor) device, or an integrated circuit including a GaAs HBT device, and may be determined according to actual use requirements. When the device structure layer 2 is a GaN HEMT device or an integrated circuit including a GaN HEMT device, the input electrode 21 is a gate electrode, the output electrode 22 is a drain electrode, and the ground electrode 23 is a source electrode, the semiconductor substrate 1 may be made of any one of silicon (Si), gallium nitride (GaN), silicon carbide (SiC), and sapphire, and in this case, the device structure layer 2 may be manufactured on the front surface of the semiconductor substrate 1 by using a GaN HEMT device manufacturing process that is mature in the technical field. When the device structure layer 2 is a GaAs HEMT device or an integrated circuit including a GaAs HEMT device, the input electrode 21 is a gate, the output electrode 22 is a drain, and the ground electrode 23 is a source, the semiconductor substrate 1 may be made of any one of silicon (Si) and gallium arsenide (GaAs), and the device structure layer 2 may be manufactured on the front surface of the semiconductor substrate 1 by using a GaAs HEMT device manufacturing process that is mature in the art.
Step S12, manufacturing a dielectric passivation layer 3 on the device structure layer 2; wherein, the medium passivation layer 3 covers the surface of one side of the device structure layer 2, which faces away from the semiconductor substrate 1;
in this step S12, specifically, with reference to fig. 2, the dielectric passivation layer 3 may be fabricated on the device structure layer 2 by using existing processes, such as a CVD (chemical vapor deposition) process, a spin coating process, and the like, which are mature in the technical field, and the dielectric passivation layer 3 may perform a passivation protection function on the device structure layer 2, so as to ensure the electrical performance and reliability of the subsequent power semiconductor device finished product. Wherein the dielectric passivation layer 3 may be silicon dioxide (SiO)2) Silicon nitride (SiNx), silicon oxynitride (sion), phosphosilicate glass (PSG), and borophosphosilicate glass (BPSG), wherein the thickness of the dielectric passivation layer 3 is 0.8-2.5 μm.
Step S13, forming a grounding electrode opening 31 corresponding to the grounding electrode 23 on the surface of the side of the dielectric passivation layer 3 opposite to the device structure layer 2; wherein, the grounding electrode opening 31 penetrates through the medium passivation layer 3 and exposes the grounding electrode 23;
in this step S13, specifically, with reference to fig. 3, the ground electrode opening 31 may be etched on the surface of the dielectric passivation layer 3 opposite to the device structure layer 2 by using a conventional process, such as a photolithography-etching process, which is well known in the art, so that the ground electrode 23 of the device structure layer 2 is exposed, thereby providing a basis for performing the related process operation of the following step 14.
Step S14, manufacturing a grounding electrode metal layer 4 on the medium passivation layer 3; the grounding electrode metal layer 4 covers the surface of one side, back to the device structure layer 2, of the dielectric passivation layer 3, and the grounding electrode metal layer 4 is connected with the grounding electrode 23 after filling the grounding electrode opening 31;
in this step S14, specifically, with reference to fig. 4, the existing processes such as a metal deposition process mature in the technical field may be adopted to perform metal filling on the grounding electrode opening 31 and form a grounding electrode metal layer 4 on the dielectric passivation layer 3, which covers the side surface of the dielectric passivation layer 3 facing away from the device structure layer 2, so that the grounding electrode 23 of the device structure layer 2 is electrically connected to the grounding electrode metal layer 4, and during the later-stage encapsulation, the grounding electrode metal layer 4 and the tube shell 7 of the encapsulation tube are attached together by welding or the like, so as to achieve the effect of grounding the grounding electrode 23 of the device structure layer 2. The metal material filled in the ground electrode opening 31 and the material of the ground electrode metal layer 4 covering the surface of one side of the dielectric passivation layer 3 include, but are not limited to, any one of silver, copper, aluminum, tungsten, titanium, nickel, and gold, and the thickness of the ground electrode metal layer 4 may be 2 to 8 micrometers.
Step S15 of thinning the semiconductor substrate 1 from the back surface of the semiconductor substrate 1; the thickness of the thinned semiconductor substrate 1 is far greater than that of the dielectric passivation layer 3;
in this step S15, specifically, with reference to fig. 5, after the front process of the power semiconductor device is completed, the device semi-finished product with the ground electrode metal layer 4 is reversely attached to the carrier, so that the ground electrode metal layer 4 is attached to the carrier, and then the back surface of the semiconductor substrate 1 can be thinned and polished by using a thinning process mature in the technical field, so that the thickness of the semiconductor substrate 1 reaches the required thickness, thereby reducing the thermal resistance of the semiconductor substrate 1 and improving the heat dissipation effect of the device structure layer 2. It should be noted here that the thickness of the semiconductor substrate 1 to be thinned is mainly considered in two aspects: in the first aspect, from the viewpoint of operability in device fabrication, the thicker the thickness of the semiconductor substrate 1, the more reliable the operability in processing, and the lower the risk of chipping brought about in the production process; in the second aspect, from the perspective of device heat dissipation, the thinner the thickness of the semiconductor substrate 1 is, the lower the thermal resistance thereof is, and the more beneficial the heat dissipation of the heat generated in the later operation of the device structure layer 2 is. Therefore, in the embodiment of the present invention, the thickness of the thinned semiconductor substrate 1 may be determined by combining the two factors, and preferably, the thickness of the thinned semiconductor substrate 1 may be 300 to 500 micrometers (the thickness is much greater than the thickness of the dielectric passivation layer 3 by 0.8 to 2.5 micrometers), so that compared with the conventional method in which the thickness of the semiconductor substrate 1 needs to be thinned to 80 to 100 micrometers, the method can not only ensure the heat dissipation performance of the power semiconductor device manufactured in the later stage, but also effectively reduce the risk of wafer fragments in the production process, thereby facilitating the improvement of the yield of the product.
Step S16 of forming an input electrode opening 11 corresponding to the input electrode 21 and an output electrode opening 12 corresponding to the output electrode 22 on the back surface of the thinned semiconductor substrate 1; the input electrode opening 11 penetrates through the semiconductor substrate 1 and exposes the input electrode 21, and the output electrode opening 12 penetrates through the semiconductor substrate 1 and exposes the output electrode 22;
in step S16, specifically, with reference to fig. 6, the input electrode opening 11 and the output electrode opening 12 may be formed on the back surface of the thinned semiconductor substrate 1 by using existing processes, such as a double-sided overlay-back-hole etching process, which are mature in the technical field, so that the input electrode 21 and the output electrode 22 of the device structure layer 2 are exposed, and a basis is provided for performing related process operations of the following step 17.
Step S17, forming a metal cap layer 5 on the back surface of the semiconductor substrate 1; the metal covering layer 5 covers the back surface of the semiconductor substrate 1, and the metal covering layer 5 is connected with the input electrode 21 after filling the input electrode opening hole 11, and is connected with the output electrode 22 after filling the output electrode opening hole 12;
in this step S17, specifically, with continued reference to fig. 7, the input electrode opening 11 and the output electrode opening 12 may be filled with metal and a metal covering layer 5 covering the back surface of the semiconductor substrate 1 may be formed on the back surface of the semiconductor substrate 1 by using an existing process, such as a metal deposition process mature in the art, so that the input electrode 21 and the output electrode 22 of the device structure layer 2 are electrically connected to the metal covering layer 5. The metal material filled in the input electrode opening 11 and the output electrode opening 12 and the material of the metal covering layer 5 covering the back surface of the semiconductor substrate 1 include, but are not limited to, any one of silver, copper, aluminum, tungsten, titanium, nickel, and gold, and the thickness of the metal covering layer 5 may be 2 to 8 micrometers.
Step S18, removing a portion of the metal covering layer 5 in the setting area to form an input electrode metal layer 51 connected to the input electrode 21 and an output electrode metal layer 52 connected to the output electrode 22 on the back surface of the semiconductor substrate 1, and to expose the back surface of the semiconductor substrate 1 in the setting area.
In step S18, referring to fig. 8, a part of the metal covering layer 5 in the set region may be removed by using a conventional process, such as a photolithography-etching process, which is well known in the art, so as to obtain an input electrode metal layer 51 electrically connected to the input electrode 21 of the device structure layer 2 and an output electrode metal layer 52 electrically connected to the output electrode 22 of the device structure layer 2 on the back surface of the semiconductor substrate 1, where the thickness of the input electrode metal layer 51 is 2 to 8 micrometers, and the thickness of the output electrode metal layer 52 is 2 to 8 micrometers. Thus, the power semiconductor device in the form of a bare chip can be obtained, and after the power semiconductor device in the form of the bare chip is packaged by a packaging process in the later stage, a finished product of the power semiconductor device which can be directly applied to an actual circuit (such as a radio frequency power amplifier applied to a base station) can be obtained. It should be noted here that, in the actual production of power semiconductor devices, in order to improve the production efficiency and reduce the production cost, a plurality of power semiconductor devices in the form of dies are simultaneously processed on the basis of one semiconductor substrate 1, and therefore, in order to obtain a power semiconductor device in the form of a single die, a wafer dicing process is generally required for the device obtained after the step S18.
In one exemplary embodiment, when a power semiconductor device in the form of a single bare chip is packaged through a packaging process, the method mainly comprises the following steps:
step S19, attaching the grounding electrode metal layer 4 to a prepared tube shell 7 of the packaging tube;
in step S19, specifically, with reference to fig. 9, the ground electrode metal layer 4 may be attached to the package case 7 of the package tube by using a bonding material such as AuSn alloy or silver paste, so as to achieve the effect of grounding the ground electrode 23 of the device structure layer 2.
In step S20, metal leads are soldered to the input electrode metal layer 51 and the output electrode metal layer 52, respectively.
In this step S19, specifically, with reference to fig. 9, by soldering a metal lead on the input electrode metal layer 51 and the output electrode metal layer 52, respectively, the input electrode 21 and the output electrode 22 of the device structure layer 2 can be electrically connected to other components in the circuit when the prepared power semiconductor device is applied to an actual circuit in a later stage.
In summary, in the method for manufacturing a power semiconductor device according to the embodiment of the present invention, the ground electrode metal layer 4 is disposed on the front side of the semiconductor substrate 1, and the input electrode metal layer 51 and the output electrode metal layer 52 are disposed on the back side of the semiconductor substrate 1, when packaging, only the ground electrode metal layer 4 is mounted on the package 7 of the package tube and the input electrode metal layer 51 and the output electrode metal layer 52 are electrically connected to other components by wire bonding, since the thickness of the dielectric passivation layer 3 on the front side of the device structure layer 2 is smaller and much smaller than that of the semiconductor substrate 1, the thermal resistance of the heat generated in the working process of the device structure layer 2 is smaller than that of the heat generated in the conventional process of conducting through the heat conducting path of the "dielectric passivation layer 3-package 7", thereby effectively improving the heat dissipation effect of the device; moreover, because the thickness of the semiconductor substrate 1 on the back side of the device structure layer 2 is larger and much larger than that of the dielectric passivation layer 3, the heat generated in the working process of the device structure layer 2 can be radiated through the semiconductor substrate 1 with larger radiation heat radiation volume in the process of conducting through a heat radiation path of surface radiation, so that the heat radiation effect of the device can be further improved; moreover, the thickness of the thinned semiconductor substrate 1 is thicker than that of the substrate obtained by adopting the conventional technology, so that the volume of the whole power semiconductor device is increased, and the heat capacity of the whole power semiconductor device is increased, so that the lower junction temperature of the device can be obtained under the condition of the same heat productivity; therefore, even if the silicon substrate with poor heat conductivity is adopted as the semiconductor substrate 1, the manufactured power semiconductor device based on the silicon substrate can obtain excellent heat dissipation performance, so that the power semiconductor device can be applied to high-power semiconductor devices such as radio-frequency power amplifiers for base stations with strict requirements on heat dissipation performance, and the technical problem that the existing radio-frequency power semiconductor device based on the silicon substrate cannot be applied to the radio-frequency power amplifiers for the base stations due to poor heat dissipation performance is effectively solved. In addition, the preparation method of the power semiconductor device in the embodiment of the invention does not need harsh requirements for substrate thinning thickness (in the embodiment of the invention, when the semiconductor substrate 1 is thinned, the thickness of the thinned semiconductor substrate 1 can be 300-500 micrometers, and the substrate does not need to be thinned to 80-100 micrometers or even thinner to obtain excellent heat dissipation performance like the traditional method), so that the risk of wafer fragments in the production process can be effectively reduced, and the yield of products is improved. In addition, because the thickness of the dielectric passivation layer 3 in the embodiment of the present invention is relatively thin (the thickness of the dielectric passivation layer 3 is only 0.8 to 2.5 micrometers, which is much smaller than the thickness of the semiconductor substrate 1), compared with the conventional ground electrode metal wire (the conventional ground electrode metal wire penetrates through the substrate), in the power semiconductor device manufactured in the embodiment of the present invention, the conductive line between the ground electrode metal layer 4 and the ground electrode 23 is much shorter, so that the parasitic inductance of the ground electrode 23 can be reduced, and the power semiconductor device can obtain better working performance, thereby being applicable to high-frequency power semiconductor devices and radio frequency/millimeter wave monolithic integrated circuits which have strict requirements on heat dissipation capability and parasitic electrical parameters.
In the method for manufacturing a power semiconductor device according to the embodiment of the present invention, it should be noted that, in the specific implementation, the material of the semiconductor substrate 1 may be determined flexibly according to the actual application requirements, and the material of the semiconductor substrate 1 may be any one of silicon, gallium nitride, gallium arsenide, silicon carbide, and sapphire. Generally, the cost of a silicon substrate is much lower than that of a gallium nitride substrate, a gallium arsenide substrate and a silicon carbide substrate under the same conditions; in the aspect of thermal conductivity, the thermal conductivity of the silicon substrate is not much lower than that of the gallium nitride substrate, but the thermal conductivity of the silicon substrate is better than that of the gallium arsenide substrate and the sapphire substrate, but the thermal conductivity of the silicon substrate is obviously poorer than that of the silicon carbide substrate, so that the heat dissipation performance of the power semiconductor device manufactured based on the silicon substrate is poorer than that of the power semiconductor device manufactured based on the silicon carbide substrate, and therefore, in practical application, the material of the semiconductor substrate 1 can be flexibly selected in the aspects of comprehensive production cost and heat dissipation performance. When the power semiconductor device manufactured by the embodiment of the invention is a gallium nitride radio-frequency power amplifier chip based on a silicon substrate (namely, the device structure layer 2 at this time is an integrated circuit containing a GaN HEMT device), compared with the traditional gallium nitride radio-frequency power amplifier chip based on a silicon substrate, the gallium nitride radio-frequency power amplifier chip based on a silicon substrate manufactured by the embodiment of the invention has better heat dissipation performance, so that the chip can be applied to high-power semiconductor devices such as radio-frequency power amplifiers for base stations with strict requirements on heat dissipation performance; compared with the traditional gallium nitride radio-frequency power amplifier chip based on the silicon carbide substrate, the gallium nitride radio-frequency power amplifier chip based on the silicon substrate prepared by the embodiment of the invention has lower production cost (specifically, because the power consumption of the radio-frequency power semiconductor device is very large in the working process, the heat dissipation problem of the radio-frequency power amplifier chip is considered, the existing gallium nitride radio-frequency power device is manufactured by adopting a gallium nitride wafer epitaxially grown on the silicon carbide substrate with high heat conductivity, although the gallium nitride wafer of the silicon carbide substrate has good heat conductivity, because the production cost of the silicon carbide substrate is high, and a large-size high-quality wafer (the current limit of the semiconductor manufacturing process level) cannot be obtained, the cost of the gallium nitride radio-frequency power amplifier chip based on the silicon carbide substrate is high, in addition, in order to obtain excellent heat dissipation performance, the back of the silicon carbide substrate needs to be thinned as much as possible in the preparation process of the gallium nitride radio-frequency power amplifier chip based on the silicon carbide substrate, and the silicon carbide substrate is too thin, which reduces the operability of wafer processing, increases the risk of fragments in production, and is not beneficial to the improvement of product yield.
In addition, in order to solve the technical problem that the conventional silicon substrate-based radio frequency power semiconductor device cannot be applied to a radio frequency power amplifier for a base station due to poor heat dissipation capacity, referring to fig. 1 to 10, an embodiment of the present invention further provides a power semiconductor device, and the power semiconductor device is prepared by the preparation method of the power semiconductor device according to any one of the embodiments.
In this embodiment, thanks to the improvement of the manufacturing method of the power semiconductor device, the power semiconductor device in the embodiment of the present invention has the advantages of good heat dissipation performance and low parasitic inductance of the ground electrode 23, and thus can be applied to high-power semiconductor devices such as radio frequency power amplifiers for base stations with strict requirements on heat dissipation performance.
In addition, in order to solve the technical problem that the conventional silicon substrate-based radio frequency power semiconductor device cannot be applied to a radio frequency power amplifier for a base station due to poor heat dissipation capability, referring to fig. 1 to 10, an embodiment of the present invention further provides a power semiconductor device, which includes a semiconductor substrate 1, a device structure layer 2, a dielectric passivation layer 3, a ground electrode metal layer 4, an input electrode metal layer 51, and an output electrode metal layer 52; wherein:
the back surface of the semiconductor substrate 1 is provided with a first area, a second area and a set area, wherein the set area is positioned between the first area and the second area and is exposed;
the device structure layer 2 has an input electrode 21, an output electrode 22 and a ground electrode 23, and the device structure layer 2 is covered on the front surface of the semiconductor substrate 1;
the dielectric passivation layer 3 covers the surface of one side of the device structure layer 2, which is back to the semiconductor substrate 1;
the grounding electrode metal layer 4 covers the surface of the side of the dielectric passivation layer 3 opposite to the device structure layer 2, and the grounding electrode metal layer 4 is electrically connected with the grounding electrode 23 (specifically, the dielectric passivation layer 3 is provided with a grounding electrode opening 31 corresponding to the grounding electrode 23, the side of the grounding electrode metal layer 4 facing the dielectric passivation layer 3 is provided with a first conductive connecting part 41, and the first conductive connecting part 41 passes through the grounding electrode opening 31 and then is electrically connected with the grounding electrode 23, so that not only is the electrical connection between the grounding electrode metal layer 4 and the grounding electrode 23 reliably realized, but also because the first conductive connecting part 41 is made of metal, the thermal conductivity of the first conductive connecting part 41 is better than that of the dielectric passivation layer 3, so that the thermal resistance of heat generated during the operation of the device structure layer 2 in the process of conducting through the heat conducting path of the dielectric passivation layer 3-the tube shell 7' can be further reduced, thereby being beneficial to further improving the heat dissipation effect of the device);
the input electrode metal layer 51 covers the first region of the semiconductor substrate 1, and the input electrode metal layer 51 is electrically connected to the input electrode 21 (specifically, the semiconductor substrate 1 is provided with an input electrode opening 11 corresponding to the input electrode 21, the side of the input electrode metal layer 51 facing the semiconductor substrate 1 is provided with a second conductive connecting portion 511, and the second conductive connecting portion 511 penetrates through the input electrode opening 11 and then is electrically connected to the input electrode 21, so that the electrical connection between the input electrode metal layer 51 and the input electrode 21 is reliably realized);
the output electrode metal layer 52 covers the second region of the semiconductor substrate 1, and the output electrode metal layer 52 is electrically connected to the output electrode 22 (specifically, the semiconductor substrate 1 is further provided with an output electrode opening 12 corresponding to the output electrode 22, a third conductive connecting portion 521 is provided on a side of the output electrode metal layer 52 facing the semiconductor substrate 1, and the third conductive connecting portion 521 passes through the output electrode opening 12 and then is electrically connected to the output electrode 22, so that the electrical connection between the output electrode metal layer 52 and the output electrode 22 is reliably achieved).
In the embodiment of the present invention, the material of the semiconductor substrate 1 may be any one of silicon, gallium nitride, gallium arsenide, silicon carbide, and sapphire. The device structure layer 2 can be any one of a Si LDMOS device, an integrated circuit comprising the Si LDMOS device, a GaN HEMT device, an integrated circuit comprising the GaN HEMT device, a GaAs HEMT device, an integrated circuit comprising the GaAs HEMT device, a GaAs HBT device and an integrated circuit comprising the GaAs HBT device. The material of the dielectric passivation layer 3 can be any one of silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass and borophosphosilicate glass. The thickness of the semiconductor substrate 1 may be 300 to 500 μm. The thickness of the medium passivation layer 3 can be 0.8-2.5 microns. The thickness of the grounding electrode metal layer 4 is 2-8 micrometers. The thickness of the input electrode metal layer 51 is 2 to 8 micrometers, and the thickness of the output electrode metal layer 52 is 2 to 8 micrometers.
The power semiconductor device provided by the embodiment of the invention is characterized in that the grounding electrode metal layer 4 is arranged on one side of the front surface of the semiconductor substrate 1, the input electrode metal layer 51 and the output electrode metal layer 52 are arranged on one side of the back surface of the semiconductor substrate 1, and during packaging, the grounding electrode metal layer 4 is only required to be attached to the tube shell 7 of the packaging tube, and the input electrode metal layer 51 and the output electrode metal layer 52 are electrically connected with other components in a routing manner, because the thickness of the dielectric passivation layer 3 positioned on one side of the front surface of the device structural layer 2 is smaller and much smaller than that of the semiconductor substrate 1, the thermal resistance suffered by heat generated in the working process of the device structural layer 2 in the process of conducting through the heat conducting path of the dielectric passivation layer 3-the tube shell 7 is smaller than that suffered by heat generated in the traditional process of conducting through the heat conducting path of the substrate-the tube shell 7, thereby effectively improving the heat dissipation effect of the device; moreover, because the thickness of the semiconductor substrate 1 on the back side of the device structure layer 2 is larger and much larger than that of the dielectric passivation layer 3, the heat generated in the working process of the device structure layer 2 can be radiated through the semiconductor substrate 1 with larger radiation heat radiation volume in the process of conducting through a heat radiation path of surface radiation, so that the heat radiation effect of the device can be further improved; moreover, the thinned thickness of the semiconductor substrate 1 is thicker than that of the substrate obtained by adopting the conventional technology, so that the volume of the whole power semiconductor device is increased, and the heat capacity of the whole power semiconductor device is increased, so that the temperature of the device structure layer 2 can be reduced more quickly under the condition of the same heat productivity; therefore, even if a silicon substrate with poor thermal conductivity is adopted as the semiconductor substrate 1, the power semiconductor device of the embodiment of the invention can obtain excellent heat dissipation performance, so that the power semiconductor device can be applied to high-power semiconductor devices such as a radio frequency power amplifier for a base station with strict requirements on heat dissipation performance, and the technical problem that the existing radio frequency power semiconductor device based on the silicon substrate cannot be applied to the radio frequency power amplifier for the base station due to poor heat dissipation performance is effectively solved. In addition, the power semiconductor device of the embodiment of the invention has no strict requirement on the thickness of the substrate (in the embodiment of the invention, the thickness of the semiconductor substrate 1 can be 300-500 micrometers, and the thickness of the substrate does not need to be reduced to 80-100 micrometers or even thinner in the production process for obtaining excellent heat dissipation performance like the traditional method), so that the risk of wafer fragments in the production process can be effectively reduced, and the yield of products is improved. In addition, because the thickness of the dielectric passivation layer 3 in the embodiment of the present invention is relatively thin (the thickness of the dielectric passivation layer 3 is only 0.8 to 2.5 micrometers, which is much smaller than the thickness of the semiconductor substrate 1), compared with the conventional ground electrode metal wire (the conventional ground electrode metal wire penetrates through the substrate), in the power semiconductor device manufactured in the embodiment of the present invention, the conductive line (i.e., the first conductive connection portion 41) between the ground electrode metal layer 4 and the ground electrode 23 is much shorter, so that the parasitic inductance of the ground electrode 23 can be reduced, and the power semiconductor device can obtain better working performance, and can be applied to a high-frequency power semiconductor device and a radio frequency/millimeter wave monolithic integrated circuit which have strict requirements on heat dissipation capability and parasitic electrical parameters.
In the power semiconductor device according to the embodiment of the present invention, it should be noted that, in the specific implementation, the material of the semiconductor substrate 1 may be determined flexibly according to the actual application requirements, and the material of the semiconductor substrate 1 may be any one of silicon, gallium nitride, gallium arsenide, silicon carbide, and sapphire. Generally, under the same other conditions, the cost of the silicon substrate is much lower than that of the gallium nitride substrate, the gallium arsenide substrate and the silicon carbide substrate, and in terms of thermal conductivity, the thermal conductivity of the silicon substrate is not much lower than that of the gallium nitride substrate, but the thermal conductivity of the silicon substrate is better than that of the gallium arsenide substrate and the sapphire substrate, but the thermal conductivity of the silicon substrate is significantly worse than that of the silicon carbide substrate, so that the heat dissipation performance of the power semiconductor device manufactured based on the silicon substrate is also worse than that of the power semiconductor device based on the silicon carbide substrate, and therefore, in practical application, the material of the semiconductor substrate 1 can be flexibly selected in terms of both the production cost and the heat dissipation performance. When the power semiconductor device manufactured by the embodiment of the invention is a gallium nitride radio-frequency power amplifier chip based on a silicon substrate (namely, the device structure layer 2 at this time is an integrated circuit containing a GaN HEMT device), compared with the traditional gallium nitride radio-frequency power amplifier chip based on a silicon substrate, the gallium nitride radio-frequency power amplifier chip based on a silicon substrate manufactured by the embodiment of the invention has better heat dissipation performance, so that the chip can be applied to high-power semiconductor devices such as radio-frequency power amplifiers for base stations with strict requirements on heat dissipation performance; compared with the conventional gallium nitride radio-frequency power amplifier chip based on the silicon carbide substrate, the gallium nitride radio-frequency power amplifier chip based on the silicon substrate prepared by the embodiment of the invention has lower production cost (specifically, because the power consumption of a radio-frequency power semiconductor device in the working process is very large, the heat dissipation problem of the radio-frequency power amplifier chip is considered, the existing gallium nitride radio-frequency power device is manufactured by adopting a gallium nitride wafer epitaxially grown on the silicon carbide substrate with high heat conductivity, although the gallium nitride wafer of the silicon carbide substrate has good heat conductivity, the production cost of the silicon carbide substrate is high, and a large-size high-quality wafer (the current limit of the semiconductor manufacturing process level) cannot be obtained, so the cost of the gallium nitride radio-frequency power amplifier chip based on the silicon carbide substrate is high, in addition, in order to obtain excellent heat dissipation performance, the back of the silicon carbide substrate needs to be thinned as much as possible in the preparation process of the gallium nitride radio-frequency power amplifier chip based on the silicon carbide substrate, and the silicon carbide substrate is too thin, which reduces the operability of wafer processing, increases the risk of fragments in production, and is not beneficial to the improvement of product yield.
Further, in order to enable the power semiconductor device in the form of a single bare chip to be more conveniently applied to an actual circuit (such as a radio frequency power amplifier for a base station) in a later circuit application, referring to fig. 9, in an exemplary embodiment, the power semiconductor device further includes a packaging tube, and the tube shell 7 of the packaging tube is attached to the grounding electrode metal layer 4, so that an effect of grounding the grounding electrode 23 of the device structure layer 2 is achieved, and no additional grounding operation is required in a subsequent use.
Further, referring to fig. 9, in an exemplary embodiment, the power semiconductor device further includes a bonding layer 6, the bonding layer 6 covers a surface of the ground electrode metal layer 4 on a side opposite to the dielectric passivation layer 3, and the package 7 encapsulating the tube is attached to the ground electrode metal layer 4 through the bonding layer 6. Therefore, by arranging the bonding layer 6, the grounding electrode metal layer 4 and the tube shell 7 of the packaging tube can be conveniently and reliably attached together, and the grounding effect of the grounding electrode 23 of the device structure layer 2 is achieved. In a specific implementation, the material of the bonding layer 6 may be a bonding material such as AuSn alloy, silver paste, or the like.
Further, referring to fig. 10, in an exemplary embodiment, the power semiconductor device further includes a first metal lead 81 and a second metal lead 82, one end of the first metal lead 81 is welded to the input electrode metal layer 51, and one end of the second metal lead 82 is welded to the output electrode metal layer 52. Thus, when the power semiconductor device of the present embodiment is applied to an actual circuit (e.g., a radio frequency power amplifier for a base station), the input electrode 21 and the output electrode 22 of the device structure layer 2 can be electrically connected to other components in the circuit through the two reserved metal leads.
In addition, an embodiment of the present invention further provides a radio frequency power amplifier, where the radio frequency power amplifier includes the power semiconductor device in any of the above embodiments.
In this embodiment, thanks to the improvement of the power semiconductor device of the foregoing embodiment, the radio frequency power amplifier of this embodiment has the same technical effects as the power semiconductor device of any of the foregoing embodiments, and details thereof are omitted.
It should be noted that, other contents of the power semiconductor device, the power semiconductor manufacturing method, and the radio frequency power amplifier disclosed in the embodiments of the present invention may be referred to in the prior art, and are not described herein again.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (10)

1. A preparation method of a power semiconductor device is characterized by comprising the following steps:
manufacturing a device structure layer on the front surface of the semiconductor substrate; the device structure layer comprises an input electrode, an output electrode and a grounding electrode, and the device structure layer covers the front surface of the semiconductor substrate;
manufacturing a medium passivation layer on the device structure layer; wherein the medium passivation layer covers one side surface of the device structure layer, which faces away from the semiconductor substrate;
manufacturing a grounding electrode opening corresponding to the grounding electrode on the surface of one side, back to the device structure layer, of the dielectric passivation layer; wherein the grounding electrode opening penetrates through the medium passivation layer and exposes the grounding electrode;
manufacturing a grounding electrode metal layer on the medium passivation layer; the grounding electrode metal layer covers the surface of one side, back to the device structure layer, of the dielectric passivation layer, and is connected with the grounding electrode after the grounding electrode metal layer fills the grounding electrode opening;
thinning the semiconductor substrate from the back side of the semiconductor substrate; the thinned semiconductor substrate is thicker than the dielectric passivation layer;
manufacturing an input electrode opening corresponding to the input electrode and an output electrode opening corresponding to the output electrode on the back surface of the thinned semiconductor substrate; the input electrode opening penetrates through the semiconductor substrate and exposes the input electrode, and the output electrode opening penetrates through the semiconductor substrate and exposes the output electrode;
manufacturing a metal covering layer on the back surface of the semiconductor substrate; the metal covering layer covers the back surface of the semiconductor substrate, is filled in the input electrode open hole and then is connected with the input electrode, and is filled in the output electrode open hole and then is connected with the output electrode;
and removing part of the metal covering layer in the set area to form an input electrode metal layer connected with the input electrode and an output electrode metal layer connected with the output electrode on the back surface of the semiconductor substrate, and exposing the back surface of the semiconductor substrate in the set area.
2. The method for manufacturing a power semiconductor device according to claim 1, wherein after the step of removing a portion of the metal cap layer in the setting region, the method further comprises:
and attaching the grounding electrode metal layer to a prepared tube shell of the packaging tube.
3. The method for manufacturing a power semiconductor device according to claim 1 or 2, wherein the step of removing a portion of the metal cap layer in the setting region further comprises:
and respectively welding metal leads on the input electrode metal layer and the output electrode metal layer.
4. The method for manufacturing a power semiconductor device according to claim 1, wherein the material of the semiconductor substrate is any one of silicon, gallium nitride, gallium arsenide, silicon carbide, and sapphire;
and/or the device structure layer is any one of a SiLDMOS device, an integrated circuit containing the SiLDMOS device, a GaN HEMT device, an integrated circuit containing the GaN HEMT device, a GaAs HEMT device, an integrated circuit containing the GaAs HEMT device, a GaAs HBT device and an integrated circuit containing the GaAs HBT device;
and/or the material of the medium passivation layer is any one of silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass and borophosphosilicate glass;
and/or the thickness of the thinned semiconductor substrate is 300-500 microns;
and/or the thickness of the medium passivation layer is 0.8-2.5 microns;
and/or the thickness of the grounding electrode metal layer is 2-8 microns;
and/or the thickness of the input pole metal layer is 2-8 microns, and the thickness of the output pole metal layer is 2-8 microns.
5. A power semiconductor device characterized by being produced by the production method of a power semiconductor device according to any one of claims 1 to 4.
6. A power semiconductor device, comprising:
the back surface of the semiconductor substrate is provided with a first area, a second area and a set area, the set area is positioned between the first area and the second area, and the set area is exposed;
a device structure layer having an input electrode, an output electrode, and a ground electrode, the device structure layer overlying the front surface of the semiconductor substrate;
the dielectric passivation layer covers one side surface, back to the semiconductor substrate, of the device structure layer;
the grounding electrode metal layer covers the surface of one side, back to the device structure layer, of the dielectric passivation layer, and is electrically connected with the grounding electrode;
the input electrode metal layer covers the first area of the semiconductor substrate and is electrically connected with the input electrode;
and the output electrode metal layer covers the second area of the semiconductor substrate and is electrically connected with the output electrode.
7. The power semiconductor device of claim 6, further comprising:
the tube shell of the packaging tube is attached to the grounding electrode metal layer;
and/or a first metal lead and a second metal lead, wherein one end of the first metal lead is welded with the input electrode metal layer, and one end of the second metal lead is welded with the output electrode metal layer.
8. The power semiconductor device of claim 7, further comprising:
and the bonding layer covers the surface of one side of the grounding electrode metal layer, which faces back to the medium passivation layer, and the tube shell of the packaging tube is attached to the grounding electrode metal layer through the bonding layer.
9. The power semiconductor device according to any one of claims 6 to 8, wherein the dielectric passivation layer has a ground electrode opening corresponding to the ground electrode, and the ground electrode metal layer has a first conductive connection portion on a side facing the dielectric passivation layer, the first conductive connection portion passing through the ground electrode opening and being electrically connected to the ground electrode;
and/or an input electrode opening hole arranged corresponding to the input electrode and an output electrode opening hole arranged corresponding to the output electrode are formed in the semiconductor substrate, a second conductive connecting part is arranged on one side, facing the semiconductor substrate, of the input electrode metal layer, a third conductive connecting part is arranged on one side, facing the semiconductor substrate, of the output electrode metal layer, the second conductive connecting part penetrates through the input electrode opening hole and then is electrically connected with the input electrode, and the third conductive connecting part penetrates through the output electrode opening hole and then is electrically connected with the output electrode;
and/or the material of the semiconductor substrate is any one of silicon, gallium nitride, gallium arsenide, silicon carbide and sapphire;
and/or the device structure layer is any one of a Si LDMOS device, an integrated circuit containing the Si LDMOS device, a GaN HEMT device, an integrated circuit containing the GaN HEMT device, a GaAs HEMT device, an integrated circuit containing the GaAs HEMT device, a GaAs HBT device and an integrated circuit containing the GaAs HBT device;
and/or the material of the medium passivation layer is any one of silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass and borophosphosilicate glass;
and/or the thickness of the semiconductor substrate is 300-500 microns;
and/or the thickness of the medium passivation layer is 0.8-2.5 microns;
and/or the thickness of the grounding electrode metal layer is 2-8 microns;
and/or the thickness of the input pole metal layer is 2-8 microns, and the thickness of the output pole metal layer is 2-8 microns.
10. A radio frequency power amplifier comprising a power semiconductor device according to any one of claims 5 to 9.
CN202111682546.6A 2021-12-31 2021-12-31 Power semiconductor device, preparation method thereof and radio frequency power amplifier Pending CN114496812A (en)

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