TWI813237B - Semiconductor device and method forming the same - Google Patents

Abstract

A semiconductor device includes: a substrate; a seed layer, disposed on the substrate; a compound semiconductor stack layer, disposed on the seed layer; and a source metal layer and a drain metal layer, disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer, at least partially covering the source metal layer and the drain metal layer, and covering opposing sidewall surfaces of the seed layer and opposing sidewall surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.

Description

Semiconductor components and methods of forming the same

The present invention relates to semiconductor elements and methods of forming the same, and in particular to a conductive layer of a high electron mobility transistor and a method of forming the same.

GaN-based semiconductor materials have many excellent material properties, such as high thermal resistance, wide band-gap, and high electron saturation rate. Therefore, semiconductor materials based on gallium nitride are suitable for use in high-temperature, high-voltage, or high-current environments. In recent years, semiconductor materials based on gallium nitride have been widely used in light emitting diode (LED) components or high-frequency components, such as high electron mobility transistors with heterogeneous interface structures. transistor, HEMT).

Although high electron mobility transistors have many advantages, conventional high electron mobility transistors still have many problems that need to be overcome in applications with high current and high voltage. For example, in the operation of high electron mobility transistor devices, the epitaxial layer located at the lower layer of the device structure is prone to accumulating excessive charges due to its own material characteristics. In such a case, these accumulated charges will affect the normal operation of the component.

In view of this, it is necessary to propose an improved high electron mobility transistor to improve the shortcomings of conventional high electron mobility transistors.

A semiconductor element, including: a substrate; a seed layer provided on the substrate; a compound semiconductor stack provided on the seed layer; a source metal layer and a drain metal layer provided on the compound semiconductor stack; and at least part of A conductive layer covering the source metal layer and the drain metal layer, and the conductive layer covers the opposite side surfaces of the seed layer and the opposite side surfaces of the compound semiconductor stack, wherein the conductive layer is electrically connected to the seed layer and the source metal layer.

A method for forming a semiconductor element, including: providing a substrate; forming a seed layer on the substrate; forming a compound semiconductor stack on the seed layer; forming a source metal layer and a drain metal layer on the compound semiconductor stack; and performing cutting. Process to form a cutting opening passing through the compound semiconductor stack and the seed layer and extending into at least a portion of the substrate; compliantly depositing a conductive layer on the bottom and sidewalls of the cutting opening and covering the source metal layer and the drain metal layer ; and removing the portion of the conductive layer located between the source metal layer and the drain metal layer.

The following disclosure provides many different embodiments or examples for implementing different components of embodiments of the present disclosure. Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present disclosure. For example, the description mentioning that the first component is formed on the second component may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components. , an embodiment in which the first and second components are not in direct contact. Additionally, the present disclosure may repeat component symbols and/or letters in various examples. Such repetition is for purposes of simplicity and clarity and does not in itself govern the relationship between the various embodiments and/or configurations discussed.

In addition, in some embodiments of the present invention, terms related to joining and connecting, such as "connection", "interconnection", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that the two structures are not in direct contact. Direct contact, where other structures are located between the two structures.

Furthermore, spatially related terms can be used here, such as "under", "below", "below", "above", "above" and similar terms can be used here to facilitate description. The diagram shows the relationship between one element or component and other elements or components. These spatial terms are intended to include the various orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is rotated 90° or at any other orientation, the spatially relative descriptors used herein may be interpreted similarly to the rotated orientation.

The terms "about", "approximately" and "approximately" used herein generally mean within ±20% of a given value, preferably within ±10%, and more preferably within ±5%. Or within ±3%, or within ±2%, or within ±1%, or within ±0.5%. The numerical values given here are approximate values. That is to say, in the absence of specific instructions of "about", "approximately" and "approximately", the given numerical values may still imply "about", "approximately", "approximately" "Probably" meaning.

Some embodiments of the present disclosure are described below in which additional steps may be provided before, during, and/or after the various stages described in these embodiments. Additional components may be added to the semiconductor device structure. Some of the described components may be replaced or omitted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, the steps may be performed in another logical order.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It is understood that these terms, such as those defined in general dictionaries, should be interpreted to have a meaning consistent with the relevant technology and the background or context of the invention, and should not be interpreted in an idealized or overly formal manner. Unless otherwise defined in the embodiments of this disclosure.

1 to 4, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A illustrate the semiconductor device 10 and its packaging device 1000 at various stages according to some embodiments of the present disclosure. Schematic cross-sectional view of the formation method. In some embodiments, the semiconductor device 10 may include any number of active and passive components depending on the field of application. For the sake of simplicity, FIG. 1 only shows two transistors 10T arranged adjacent to each other. According to some embodiments of the present disclosure, the transistor 10T may be a high electron mobility transistor (HEMT). The packaging device 1000 can be used to carry at least one transistor 10T after single crystallization (singulation).

Referring to FIG. 1 , the semiconductor device 10 may include a substrate 100 , a buried oxide layer 110 , a seed layer 120 , a compound semiconductor stack 200 , a dielectric layer 300 , a source electrode 410 , a drain electrode 420 , and a gate electrode. 430. Source contact 510, drain contact 520, source metal layer 610, drain metal layer 620, and passivation layer 700. In some embodiments, the compound semiconductor stack 200 may include a buffer layer 210, a channel layer 220, and a barrier layer 230. Furthermore, the dielectric layer 300 may include a first dielectric layer 310 and a second dielectric layer 320 . Each source electrode 410, each drain electrode 420, and each gate electrode 430 disposed between the source electrode 410 and the drain electrode 420 may constitute the transistor 10T of the present invention, such as a high electron mobility transistor. . In one embodiment, the film thickness of the semiconductor device 10 minus the substrate 100 is about 1 μm to about 25 μm. Referring to FIG. 1 , the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium; a compound semiconductor, including gallium nitride (GaN), silicon carbide , SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (indium antimonide, InSb); alloy semiconductor, including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AlInAs) alloy, arsenic Aluminum gallium arsenide (AlGaAs) alloy, gallium indium arsenide (GaInAs) alloy, gallium indium phosphide (GaInP) alloy, and/or gallium indium arsenide phosphide (GaInAsP) Alloys, or combinations thereof.

In certain embodiments of the present disclosure, the substrate 100 may have an active region (not shown) and an isolation region (not shown). In some embodiments, the substrate 100 may include a ceramic substrate or a silicon substrate. In some embodiments, substrate 100 is an insulating substrate. In some embodiments, the material of the ceramic substrate may include aluminum nitride (AlN), silicon carbide (SiC), aluminum oxide (Al ₂ O ₃ ), other similar materials, or combinations thereof . In some embodiments, the ceramic powder can be sintered at high temperature through powder metallurgy to form the ceramic substrate.

Continuing to refer to FIG. 1 , a buried oxide (BOX) layer 110 may be formed on the substrate 100 . In some embodiments, the buried oxide layer 110 may encapsulate the substrate 100 and may be a film layer with good thermal stability at high temperatures. The material of the buried oxide layer 110 may include silicon oxide. For example, the buried oxide layer 110 may be an oxide seed layer made of tetraethylorthosilicate (TEOS). The thickness of the buried oxide layer 110 may be approximately between 0.5 μm and 5 μm.

Referring to FIG. 1 , a seed layer 120 may be formed on the buried oxide layer 110 . In some embodiments, the seed layer 120 can alleviate the lattice difference between the substrate 100 and the film layer grown above to improve the crystal quality. In other embodiments, the substrate 100 , the buried oxide layer 110 , and the seed layer 120 may together be regarded as a semiconductor on insulator (SOI) substrate. The semiconductor-on-insulator substrate may include a substrate (eg, substrate 100), a buried oxide layer (eg, buried oxide layer 110) disposed on the substrate, and a semiconductor layer (eg, buried oxide layer 110) disposed on the buried oxide layer. For example, seed layer 120). In addition, the semiconductor substrate on the insulating layer may be of N-type or P-type conductivity (for example, the seed layer 120 is doped with phosphorus to form an N-type conductivity type, or the seed layer 120 is doped with boron to form a P-type conductivity type). ). The thickness of the seed layer 120 may be approximately between 50 nm and 500 nm, such as 250 nm. The seed layer 120 may be formed by an epitaxial process, which may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular Molecular beam epitaxy (MBE), other suitable methods, or combinations thereof.

Continuing to refer to FIG. 1 , a compound semiconductor stack 200 may be formed on the seed layer 120 . In some embodiments, seed layer 120 and compound semiconductor stack 200 may be considered epitaxial material layers of semiconductor device 10 . According to some embodiments of the present disclosure, the thickness of the compound semiconductor stack 200 may be approximately 2 to 3 times the thickness of the seed layer 120 . As previously described, the compound semiconductor stack 200 may include a buffer layer 210, a channel layer 220, and a barrier layer 230. In some embodiments, the buffer layer 210 may be disposed on the seed layer 120 , and the buffer layer 210 directly contacts the seed layer 120 . A channel layer 220 may be provided on the buffer layer 210. Afterwards, a barrier layer 230 may be provided on the channel layer 220. The material of the compound semiconductor stack 200 may include gallium nitride (GaN), aluminum nitride (aluminum nitride, AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (aluminum indium nitride, AlInN), other suitable materials, or combinations thereof. In certain embodiments of the present disclosure, the compound semiconductor stack 200 may be a GaN-based material. The thickness of the compound semiconductor stack 200 may be approximately between 2 μm and 10 μm, such as 5.5 μm. The compound semiconductor stack can be formed by organic metal chemical vapor deposition, atomic layer deposition (ALD), molecular beam epitaxy, liquid phase epitaxy (LPE), other suitable processes, or a combination thereof. Layer 200.

According to some embodiments, the buffer layer 210 can slow down the strain of the channel layer 220 subsequently formed above the buffer layer 210 to prevent defects from being formed in the upper channel layer 220. The strain is caused by the relationship between the channel layer 220 and the underlying film layer. caused by mismatch. According to some embodiments, channel layer 220 may provide an electron transport path between source electrode 410 and drain electrode 420 (described in detail below) of transistor 10T. In some embodiments, channel layer 220 may be doped (eg, with N-type doping or P-type doping), or undoped.

Referring to FIG. 1 , a dielectric layer 300 may be formed on the compound semiconductor stack 200 . As previously described, the dielectric layer 300 may include a first dielectric layer 310 and a second dielectric layer 320. Although the dielectric layer 300 in this case is shown as having two dielectric layers, the embodiment of the present disclosure is not limited thereto. For example, dielectric layer 300 may include any number of dielectric layers, depending on application and design requirements. In some embodiments, in addition to providing protection and insulation for underlying film layers, dielectric layer 300 can also separate different levels of conductive materials. In some embodiments, the material of the dielectric layer 300 may include silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (silicon oxynitride), _SiON ), silicon _{oxycarbonitride} (e.g. _, SiO (Such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass ( boron doped silicon glass (BSG)), low dielectric constant dielectric materials, or other suitable dielectric materials. Dielectric layer 300 may be formed by deposition or other similar methods.

Continuing to refer to FIG. 1 , before forming the dielectric layer 300 , a plurality of openings (not shown) may be formed through the barrier layer 230 and extend into the channel layer 220 . A source electrode 410 and a drain electrode 420 are formed on the compound semiconductor stack 200 and fill the openings. According to some embodiments of the present disclosure, the source electrode 410 and the drain electrode 420 may pass through the barrier layer 230 and extend into the channel layer 220 to form an ohmic contact. Next, the first dielectric layer 310 of the dielectric layer 300 is first formed, so that the source electrode 410 and the drain electrode 420 are buried therein. An opening (not shown) may be formed again through the first dielectric layer 310 and expose a portion of the surface of the barrier layer 230 . Gate electrode 430 is formed on first dielectric layer 310 . According to some embodiments of the present disclosure, the gate electrode 430 may pass through the first dielectric layer 310 and sit on the barrier layer 230 to form a Schottky contact. Then, the second dielectric layer 320 of the dielectric layer 300 is formed such that the gate electrode 430 is buried therein.

In some embodiments, the materials of the source electrode 410 , the drain electrode 420 , and the gate electrode 430 may include amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride (such as titanium nitride) (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicides (such as nickel silicide (NiSi), cobalt silicide (CoSi), silicon Tantalum nitride (TaSiN), or other similar materials), metal carbides (such as tantalum carbide (TaC), tantalum carbonitride (TaCN), or other similar materials), metal oxides, and metals. Metals may include cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W), copper (copper, Cu), titanium (Ti), tantalum (Ta) ), silver (Ag), gold (Au), nickel (Ni), other similar materials, combinations thereof, or multi-film layers thereof. In some embodiments, photolithography processes (eg, photoresist coating, soft baking, exposure, post-exposure baking, development, other suitable techniques, or combinations thereof) and etching processes (eg, wet etching) may be used process, dry etching process, other suitable methods, or combinations thereof), other suitable processes, or combinations thereof to form the above-mentioned opening in the barrier layer 230 or the first dielectric layer 310 . Next, the above materials are filled in the openings to form the source electrode 410, the drain electrode 420, and the gate electrode 430.

Referring to FIG. 1 , a plurality of openings (not shown) may be formed through the second dielectric layer 320 and extend into the first dielectric layer 310 to expose the surfaces of the source electrode 410 and the drain electrode 420 . Source contacts 510 and drain contacts 520 are formed in the openings to contact the source electrode 410 and the drain electrode 420 respectively. The materials of the source contact 510 and the drain contact 520 may be similar to the materials of the source electrode 410 , the drain electrode 420 , and the gate electrode 430 , and the details thereof will not be repeated here. The formation method of the source contact 510 and the drain contact 520 may be similar to the formation method of the source electrode 410 , the drain electrode 420 , and the gate electrode 430 , and the details thereof will not be repeated here.

Continuing to refer to Figure 1, a source metal layer 610 and a drain metal layer 620 can be formed on the second dielectric layer 320 of the dielectric layer 300, which are electrically connected to the source contact 510 and the drain contact 520 respectively. . It is worth noting that the dielectric layer 300 is vertically disposed between the source metal layer 610 and the drain metal layer 620 and the compound semiconductor stack 200 . In other words, the source electrode 410 is electrically coupled to the source metal layer 610 through the source contact 510 , and the drain electrode 420 is electrically coupled to the drain metal layer 620 through the drain contact 520 . In some embodiments, the source metal layer 610 and the drain metal layer 620 may serve as bonding pads for a back-end of line (BEOL) process and/or a packaging process for forming the package device 1000 . The materials of the source metal layer 610 and the drain metal layer 620 may be similar to the materials of the source electrode 410 , the drain electrode 420 , and the gate electrode 430 , and the details thereof will not be repeated here. The formation method of the source metal layer 610 and the drain metal layer 620 may be similar to the formation method of the source electrode 410, the drain electrode 420, and the gate electrode 430, and the details thereof will not be repeated here.

Referring to FIG. 1 , a passivation layer 700 may be covered on the structural surface of the semiconductor device 10 . In some embodiments, passivation layer 700 may provide protection for underlying film layers. In addition, the passivation layer 700 can be patterned to expose part of the surface of the source metal layer 610 and the drain metal layer 620, so that the bonding of the subsequent process and/or packaging process can be smoothly performed. The material of the passivation layer 700 may be similar to the material of the dielectric layer 300, and the details thereof will not be repeated here. The formation method of the passivation layer 700 may be similar to the formation method of the dielectric layer 300, and the details thereof will not be repeated here.

Referring to Figure 2, a cutting opening 702 is formed at a position corresponding to a subsequent cutting lane. The cutting opening 702 is formed from one side of the source metal layer 610 and the drain metal layer 620 and is located outside the active area, such as around the two transistors 10T. According to some embodiments of the present disclosure, the cutting process used to form the cutting opening 702 is preferably laser cutting to expose the sides of the seed layer 120 so that the subsequently formed conductive layer 740 (described in detail below) can The seed layer 120 is electrically connected to the upper source metal layer 610 to discharge accumulated charges to reduce the resistance of the semiconductor device and increase the speed of operation. In order to electrically connect the seed layer 120 , the cutting opening 702 must pass through the passivation layer 700 , the dielectric layer 300 , and the compound semiconductor stack 200 . In one embodiment, the cutting opening 702 further extends to the top surface of the substrate 100 or within the substrate 100 to ensure that the side surfaces of the seed layer 120 can be completely exposed. In other words, the cutting opening 702 exposes the side surfaces of the passivation layer 700 , the side surfaces of the dielectric layer 300 , the side surfaces of the compound semiconductor stack 200 , the side surfaces of the seed layer 120 , the surface of the buried oxide layer 110 , and part of the side surfaces of the substrate 100 .

According to some embodiments of the present disclosure, the cutting opening 702 may have a cutting depth D1, measured from the passivation layer 700 to the bottom of the cutting opening 702. As shown in FIG. 2 , the substrate 100 has a remaining thickness D2 below the cutting opening 702 . The cutting depth D1 may be approximately between 20 μm and 60 μm, such as 50 μm. The remaining thickness D2 may be approximately between 500 μm and 800 μm. In addition to ensuring that the cutting depth D1 can completely expose the seed layer 120 , the remaining thickness D2 must also be maintained at a certain size to ensure that subsequent thinning processes will not form cracks on the semiconductor element 10 .

Referring to FIG. 3 , a conductive layer 740 can be compliantly formed on the structure of the semiconductor device 10 , covering the passivation layer 700 , the exposed surfaces of the source metal layer 610 and the drain metal layer 620 , and the sidewalls and bottom of the cutting opening 702 . Since the cutting opening 702 isolates the two transistors 10T from each other, the conductive layer 740 covers the opposite side surfaces of the seed layer 120 , the compound semiconductor stack 200 , and the dielectric layer 300 of each transistor 10T. The conductive layer 740 can electrically connect the seed layer 120 and the source metal layer 610 from the cutting opening 702 . According to some embodiments of the present disclosure, the conductive layer 740 directly contacts one of the opposite side surfaces of the seed layer 120 and the top surface of the source metal layer 610 . It is worth noting that when the conductive layer 740 is initially formed, in addition to electrically connecting the seed layer 120 and the source metal layer 610, the conductive layer 740 also connects the source metal layer 610, the drain metal layer 620, and the seed layer. layer 120 and drain metal layer 620, as well as two adjacent transistors 10T. The material of the conductive layer 740 may include titanium, copper, aluminum, cobalt, titanium nitride, tantalum nitride, other similar materials, or any combination thereof. The thickness of conductive layer 740 may be between approximately 1000 Å and 1 μm, such as 3000 Å. The conductive layer 740 may be formed by a sputtering process, an evaporating process, chemical plating, other similar methods, or a combination thereof.

Referring to FIG. 4 , the conductive layer 740 is covered with an insulating layer 760 . In some embodiments, the insulating layer 760 covers the entire semiconductor device 10 and fills the cutting opening 702, and has a substantially flat top surface. The function of the insulating layer 760 is to subsequently pattern the conductive layer 740 and cut off portions of the conductive layer 740 that may cause an electrical short circuit to the semiconductor element 10 . The material of the insulating layer 760 includes polyimide (PI), polyamide (PA), combinations thereof, or other similar materials. The thickness of the insulating layer 760 to the conductive layer 740 may be between about 1 μm and 10 μm, such as 3.5 μm. Can be processed by spin-on coating, chemical vapor deposition (CVD), atomic layer deposition, high-density plasma chemical vapor deposition (HDP-CVD) , plasma-enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD) , other similar methods, or a combination thereof to form the insulating layer 760.

5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B illustrate cross-sections of semiconductor devices 10 and packaging devices 1000 of different aspects according to other embodiments of the present disclosure. Schematic diagram. In the embodiments of Figures 1 to 4, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A, the two transistors 10T of the semiconductor device 10 are adjacent to each other but operate independently. Two active components, such as high electron mobility transistors. In comparison, Figures 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B illustrate two transistors 10T connected in series, and the drain metals of the two transistors 10T Layers 620 are arranged adjacent to each other. Since the previous processes of the embodiments shown in Figures 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B may be similar to those described in Figures 1 to 4, the details will not be as follows. Repeat.

Referring to Figures 5A and 5B, the insulating layer 760 is patterned to form a patterned insulating layer 760. After patterning, as shown in FIG. 5A , first openings 762 , second openings 764 , and third openings 766 are formed in the insulating layer 760 . The first opening 762 exposes a portion of the conductive layer 740 located at the bottom of the cutting opening 702 . The second opening 764 exposes the portion of the conductive layer 740 located on the top surface of the source metal layer 610 and the top surface of the drain metal layer 620 . The third opening 766 exposes the portion of the conductive layer 740 between the source metal layer 610 and the drain metal layer 620 , and the portion between the drain metal layer 620 and the cutting opening 702 close to the drain metal layer 620 . It should be noted that the portion between the source metal layer 610 and the cutting opening 702 close to the source metal layer 610 must remain covered in order to achieve electrical connection between the seed layer 120 and the source metal layer 610 in the embodiment of the present disclosure. Conductive layer 740 is an innovative way to discharge accumulated charges.

The portion of the conductive layer 740 exposed by the first opening 762 and the third opening 766 of the insulating layer 760 may cause an electrical short circuit to the semiconductor device 10 during operation, and therefore needs to be removed in subsequent processes, that is, the continuous The conductive layer 740 is cut off. In addition, the portion of the conductive layer 740 exposed by the second opening 764 will not be cut off, but the bonding pad 800 will be formed on the portion. In other words, the opening of the insulating layer 760 may cut off the conductive layer 740 (as described above) or form the bonding pad 800 . In some embodiments, photolithography processes (eg, photoresist coating, soft bake, exposure, post-exposure bake, development, other suitable techniques, or combinations thereof) and etching processes (eg, wet etching processes, dry etching) may be used. process, other suitable methods, or combinations thereof), other suitable processes, or combinations thereof to form the first opening 762, the second opening 764, and the third opening 766.

As shown in FIG. 5B , only the second opening 764 and the third opening 766 are formed in the insulating layer 760 . Since the two transistors 10T are connected in series with each other, the insulating layer 760 will not expose the cutting opening 702 between the two transistors 10T. The second opening 764 exposes the portion of the conductive layer 740 located on the top surface of the source metal layer 610 and the top surface of the drain metal layer 620 . The third opening 766 exposes the portion of the conductive layer 740 between the source metal layer 610 and the drain metal layer 620 and the portion between the drain metal layer 620 and the cutting opening 702 . As mentioned above, the portion between the source metal layer 610 and the cutting opening 702 close to the source metal layer 610 must remain covered to achieve the innovative method of discharging accumulated charges in the embodiment of the present disclosure. The formation method of the second opening 764 and the third opening 766 may be similar to that described in FIG. 5A , and the details thereof will not be repeated here.

Referring to FIGS. 6A and 6B , a photoresist layer 780 is formed on the exposed portion of the conductive layer 740 and the patterned insulating layer 760 , and then the photoresist layer 780 is patterned to form a photoresist opening 784 . The patterned photoresist layer 780 is used to define the locations where the bonding pads 800 are formed. It should be understood that the photoresist opening 784 of the photoresist layer 780 corresponds to the second opening 764 of the insulating layer 760, that is, the portion of the conductive layer 740 exposed through the photoresist opening 784 and the second opening 764 will be protected by the bonding pad 800, so as to Avoid oxidation of the conductive layer 740. It is worth noting that the photoresist layer 780 will first cover the first opening 762 and the third opening 766 in Figure 5A (the part where the conductive layer 740 is to be cut off), or cover the third opening 766 in Figure 5B (the part where the conductive layer 740 is to be cut off). Cover the cut-off portion of the conductive layer 740). This approach is because the bonding pads 800 need to be formed first before the portions of the conductive layer 740 that may cause an electrical short circuit can be cut off. The formation method and patterning method of the photoresist layer 780 may be similar to the formation method and patterning method of the insulating layer 760 , and the details thereof will not be repeated here.

Referring to Figures 7A and 7B, bonding pads 800 are formed in photoresist openings 784. The bonding pad 800 covers the portion of the conductive layer 740 exposed through the photoresist opening 784 (or the second opening 764 ). In other words, the bonding pad 800 is disposed on the portion of the conductive layer 740 located on the top surface of the source metal layer 610 and the top surface of the drain metal layer 620 . Since the focus of the embodiment of the present invention is to electrically connect the seed layer 120 and the source metal layer 610 through the conductive layer 740, the conductive layer 740 must be retained on the top surface of the source metal layer 610.

Generally speaking, the materials of the source metal layer 610 and the drain metal layer 620 may include nickel, gold, platinum (Pt), palladium (Palladium, Pd), iridium (iridium, Ir), titanium, chromium (chromium, Cr), tungsten, aluminum, copper, combinations thereof, or other suitable materials. In a specific embodiment of this case, the material of the bonding pad 800 may include copper, nickel, and gold, so that during the packaging process of forming the packaging device 1000 of the semiconductor device 10, either a bonding wire or a bonding ball may be disposed on the bonding Pad 800 on. The result can be obtained by compliantly depositing a metal material layer on the photoresist layer 780 and in the photoresist opening 784 (corresponding to the second opening 764 ), and then removing the photoresist layer 780 and the metal material layer thereon simultaneously. Bonding pads 800 above conductive layer 740 on source metal layer 610 and drain metal layer 620 . The deposition method of the bonding pad 800 may be similar to the deposition method of the source metal layer 610 or the drain metal layer 620, and the details thereof will not be repeated here.

Referring to Figures 8A and 8B, after the bonding pads 800 are formed, the patterned photoresist layer 780 may be removed. After the photoresist layer 780 is removed, the first opening 762 and the third opening 766 may be exposed (refer to FIG. 5A ), or only the third opening 766 may be exposed (refer to FIG. 5B ). It should be noted that the conductive layer 740 originally exposed by the second opening 764 in FIG. 5A or 5B has been covered by the bonding pad 800 . The patterned photoresist layer 780 can be removed by ashing, stripping, other similar methods, or a combination thereof.

Referring to Figures 9A and 9B, the portion of the conductive layer 740 that is not protected by the insulating layer 760 and the bonding pad 800 is removed. In other words, the portion of the continuous conductive layer 740 exposed through the first opening 762 and the third opening 766 in FIG. 8A is cut off, or the portion of the continuous conductive layer 740 exposed through the third opening 766 in FIG. 8B is cut off. cut off to prevent the semiconductor device 10 from being electrically short-circuited in subsequent operations. As shown in FIG. 9A , when the portion of the conductive layer 740 exposed through the first opening 762 is cut off, the two adjacent transistors 10T will not be turned on. When the portion of the conductive layer 740 exposed through the third opening 766 is cut off, the source metal layer 610 and the drain metal layer 620 will not be connected, and the seed layer 120 and the drain metal layer 620 will not be connected either. As shown in FIG. 9B , when the portion of the conductive layer 740 exposed through the third opening 766 is cut off, the source metal layer 610 and the drain metal layer 620 of each transistor 10T will not be turned on. In addition, the drain metal layers 620 of the two transistors 10T will not be turned on, but the two transistors 10T can still be maintained in series with each other. Therefore, cutting off the above-mentioned portion of the conductive layer 740 can effectively prevent the semiconductor device 10 from electrical short circuit in subsequent operations. The continuous conductive layer 740 can be cut off by a suitable etching process (eg, wet etching).

Referring to Figures 10A and 10B, after the conductive layer 740 is cut off, the substrate 100 is thinned. Depending on the application and design requirements, the backside of the substrate 100 (the other side relative to the seed layer 120 ) may be thinned to a desired thickness. The substrate 100 can be thinned through a Taiko grinding process, a non-Taiko grinding process, or other similar methods. As shown in Figure 10A, since the two transistors 10T are active components that operate independently, an additional single crystallization process needs to be performed on the thinned substrate 100. Since the position scheduled to be single crystallized has been partially laser-cut previously from the front side of the substrate 100, only the remaining substrate 100 after grinding needs to be cut. It is worth noting that the two transistors 10T in Figure 10B are connected in series with each other, so there is no need to perform a single crystallization process on the thinned substrate 100. The single crystallization process of the semiconductor device 10 in FIG. 10A can be performed by blade sawing, die break dicing, or other similar methods.

As mentioned previously, since a portion of the conductive layer 740 in the embodiment of the present disclosure is disposed on the top surface of the source metal layer 610 and the top surface of the drain metal layer 620 , the bonding pad 800 includes copper, nickel, and gold. Cover the portion of conductive layer 740 . The bonding pad 800 is arranged so that both solder balls and bonding wires can be used to bond the bonding pad 800 during the packaging process. Appropriate packaging processes can be performed before or after single crystallization. Suitable types of packaging processes include wafer level chip scale package (WLCSP), transistor outline (TO), small outline integrated circuit (SOIC), quad flat package (quad flat package, QFP), dual flat non-leaded (DFN), quad flat non-leaded (QFN), and ball grid array (BGA).

Referring to Figures 11A and 11B, for a flip-chip type packaging process, solder balls 900 can be formed on the bonding pads 800. In some embodiments, the solder ball 900 may also be called a "solder bump" and is used to connect at least one single crystallized transistor 10T to the packaging substrate 1100 of the packaging device 1000 (More details below). A bonding machine can be used to thermally bond the solder balls 900 to the bonding pads 800, and then perform a reflow process. After reflow is completed, the diameter of the solder ball 900 outside the insulating layer 760 may be between about 20 μm and 400 μm, such as 45 μm. The material of solder ball 900 may include any suitable metallic material. In other embodiments, before bonding the solder ball 900, a barrier metal layer may be formed on the bonding pad 800 to increase the adhesion strength between the solder ball 900 and the bonding pad 800.

Referring to Figures 12A and 12B, a package substrate 1100 is provided. The packaging substrate 1100 may be a laminate. For example, the packaging substrate 1100 may include a plurality of metal layers and a plurality of dielectric layers in a staggered arrangement, and have vias passing through the dielectric layer to couple each metal layer. To simplify the drawing, details of the packaging substrate 1100 are not shown here. In some embodiments, the upper surface of the package substrate 1100 is used to connect the transistor 10T, and the lower surface is used to connect to, for example, a printed circuit board (PCB). The outermost metal layer of the package substrate 1100 may be patterned to form solder pads 1120 on the upper surface.

According to some embodiments of the present disclosure, the transistor 10T and the packaging substrate 1100 may be connected in a flip-chip manner. In other words, the transistor 10T electrically connects the solder ball 900 to the solder pad 1120 in an "inverted" manner. When the topmost part of the transistor 10T does not include the copper, nickel, and gold bonding pads 800 , the transistor 10T and the packaging substrate 1100 need to be connected to the packaging substrate 1100 by wire bonding. However, excessively long metal traces can increase the inductance between components. When the transistor 10T in the embodiment of the present disclosure has the bonding pad 800, the solder ball 900 can be directly soldered to the soldering pad 1120. Due to the omission of wire bonding, the size of the transistor 10T and the configuration of the circuit can be more flexible, while optimizing the performance of the overall structure. This process can be called Surface Mount Technology (SMT).

Continuing to refer to FIGS. 12A and 12B , an underfill 1130 may be injected into the space between the transistor 10T and the packaging substrate 1100 . In some embodiments, underfill 1130 may contact and surround solder ball 900 . Underfill 1130 may be cured to further secure transistor 10T and solder balls 900 on package substrate 1100 . In some embodiments, the underfill 1130 may overflow out of the space between the transistor 10T and the packaging substrate 1100 and surround part of the peripheral sidewalls of the transistor 10T to enhance the stability of the transistor 10T. The material of the underfill 1130 may include epoxy resin or silicone. The underfill 1130 can be penetrated into the space between the transistor 10T and the packaging substrate 1100 by dispensing.

Referring to Figures 13A and 13B, a first glue layer 1140 is formed on the packaging substrate 1100. Viewed from a top view, the first glue layer 1140 may have a ring-shaped structure surrounding the transistor 10T (or the underfill 1130 ). It is worth noting that the first glue layer 1140 is laterally spaced apart from the transistor 10T. According to some embodiments of the present disclosure, the first adhesive layer 1140 can be used to define the position of the subsequently formed reinforced annular structure 1160 and increase the adhesion between the packaging substrate 1100 and the reinforced annular structure 1160 .

The material of the first adhesive layer 1140 may include bisphenol A type epoxy resin, bisphenol F type epoxy resin, or bisphenol S type epoxy resin. epoxy resin), phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenyl type epoxy resin, aralkyl type epoxy resin dicyclopentadiene type epoxy resin), dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, bisphenol aralkyl type epoxy resin Oxygen resin (biphenyl aralkyl type epoxy resin), fluorene type epoxy resin (fluorene type epoxy resin), dibenzopyran type epoxy resin (xanthene type epoxy resin), triglycidyl isocyanurate (TGIC) ), combinations thereof, or other similar materials. The first adhesive layer 1140 can be formed by dispensing using a syringe printing process.

Referring to Figures 14A and 14B, a reinforced annular structure 1160 is formed on the first glue layer 1140. From the top view, the reinforced annular structure 1160 may also have an annular structure surrounding the transistor 10T (or the underfill 1130). The ring structure can be circular, rectangular, or any acceptable geometric shape. Reinforcement ring structure 1160 is laterally spaced from transistor 10T. According to some embodiments of the present disclosure, the reinforced annular structure 1160 can support the space between the packaging substrate 1100 and the subsequently formed heat sink 1200 to prevent the structure of the packaging device 1000 from warpage. The material of the reinforced ring structure 1160 may include ceramics, plastics, other similar materials, or combinations thereof. The top surface of the reinforced ring structure 1160 may be substantially flush with the backside of the substrate 100 of the transistor 10T (relative to the other side surface of the seed layer 120 ). Heat-resistant glue, solder paste, other similar materials, or a combination thereof may be used and then cured to form the reinforced ring structure 1160 .

Referring to Figures 15A and 15B, a second glue layer 1180 and a heat sink 1200 are sequentially formed on the top surface of the reinforced ring structure 1160 and the back side of the substrate 100 of the transistor 10T. According to some embodiments of the present disclosure, the second adhesive layer 1180 can increase the adhesion between the reinforced ring structure 1160 and/or the transistor 10T and the heat sink 1200 . The material and formation method of the second glue layer 1180 may be similar to the first glue layer 1140, and the details thereof will not be repeated here. In other embodiments, the second glue layer 1180 may include thermally conductive material, which may assist the heat dissipation function of the heat sink 1200 .

According to some embodiments of the present disclosure, the heat sink 1200 can release heat generated from the transistor 10T during operation, and can provide an additional heat dissipation path, so that the heat dissipation efficiency can be more effectively improved. The thickness of the heat sink 1200 may be between about 0.05 mm and 5 mm, but the present invention is not limited thereto. The material of the heat sink 1200 may include any material with thermal conductivity, such as graphene or metal. The heat sink 1200 may be deposited using physical vapor deposition, atomic layer deposition, electroplating, other suitable processes, or a combination thereof.

In a comparative example, etching is used to penetrate the compound semiconductor stack 200, and then a through GaN via (TGV) is formed to electrically connect the seed layer and the source metal layer as a ground, so that the accumulated charge can be discharged. However, since the compound semiconductor stack 200 is difficult to etch, the process of forming through-gallium nitride via holes requires a high cost and a long cycle time. Furthermore, the energy required for the etching process is difficult to control, and the risk of damaging other components is also high. Therefore, the high cost and high risk required by the above process are self-evident.

As the area and thickness of gallium nitride-based structures increase, the material's tendency to easily accumulate charges will become more and more apparent. In the embodiment of the present disclosure, the conductive layer is used to compliantly and continuously extend from the side of the seed layer to the top surface of the source metal layer, thereby draining the accumulated charges in the seed layer, thereby reducing the device resistance and improving the device operation. speed.

The features of several embodiments are summarized above so that those with ordinary skill in the art can better understand the concepts of the disclosed embodiments. Those of ordinary skill in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present disclosure to achieve the same purposes and/or advantages as the embodiments introduced here. Those with ordinary knowledge in the technical field should also understand that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and various changes can be made without departing from the spirit and scope of the present disclosure. Replace and replace.

10:Semiconductor components

10T: transistor

100:Base

110: Buried oxide layer

120:Seed layer 200: Compound semiconductor stack 210: Buffer layer 220: Channel layer 230:Barrier layer 300: Dielectric layer 310: First dielectric layer 320: Second dielectric layer 410: Source electrode 420: Drain electrode 430: Gate electrode 510: Source contact 520:Drain contact 610: Source metal layer 620: Drain metal layer 700: Passivation layer 702: Cutting opening 740: Conductive layer 760:Insulation layer 762:First opening 764:Second opening 766:The third opening 780: Photoresist layer 784: Photoresist opening 800:Joint pad 900: Solder ball 1000:Packaging device 1100:Package substrate 1120:Welding pad 1130: Bottom filler 1140: First glue layer 1160: Strengthen ring structure 1180: Second glue layer 1200:Heat sink D1: cutting depth D2: remaining thickness

Various aspects of the disclosed embodiments will be described in detail below with reference to the accompanying drawings. It should be noted that, consistent with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the present disclosure. Figures 1 to 4, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A are schematic cross-sectional views illustrating a method of forming a semiconductor device at various stages according to some embodiments of the present disclosure. . 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B are schematic cross-sectional views showing different aspects of semiconductor devices according to other embodiments of the present disclosure.

10:Semiconductor components

10T: transistor

100:Base

110: Buried oxide layer

120:Seed layer

200: Compound semiconductor stack

210:Buffer layer

220: Channel layer

230:Barrier layer

300: Dielectric layer

310: First dielectric layer

320: Second dielectric layer

410: Source electrode

420: Drain electrode

430: Gate electrode

510: Source contact

520:Drain contact

610: Source metal layer

620: Drain metal layer

700: Passivation layer

740: Conductive layer

760:Insulation layer

762:First opening

766:The third opening

800:Joint pad

Claims (22)

A semiconductor component including: a base; A seed crystal layer is provided on the substrate; A compound semiconductor stack is provided on the seed layer; A source metal layer and a drain metal layer are disposed on the compound semiconductor stack; and A conductive layer, at least partially covering the source metal layer and the drain metal layer, and covering the opposite side surfaces of the seed layer and the opposite side surfaces of the compound semiconductor stack, wherein the conductive layer is electrically connected to the seed layer and the source metal layer. The semiconductor device of claim 1, wherein the conductive layer directly contacts one of the opposite side surfaces of the seed layer and the top surface of the source metal layer. The semiconductor device of claim 1, further comprising an insulating layer covering the conductive layer, and the insulating layer exposing at least a portion of the conductive layer located on the top surface of the source metal layer and the top surface of the drain metal layer; one of which The bonding pad covers the top surface of the source metal layer and the top surface of the drain metal layer. The semiconductor device of claim 1, further comprising at least one dielectric layer disposed between the compound semiconductor stack and the source metal layer; wherein the conductive layer at least partially covers opposite side surfaces of the dielectric layer. The semiconductor device of claim 4, wherein at least the dielectric layer includes: a first dielectric layer disposed on the compound semiconductor stack; and A second dielectric layer is disposed on the first dielectric layer. The semiconductor device of claim 1, wherein the compound semiconductor stack further includes: A buffer layer is provided on the seed layer; A channel layer is provided on the buffer layer; and A barrier layer is provided on the channel layer. For example, the semiconductor component of claim 1 further includes: a source electrode, wherein the source electrode is electrically coupled to the source metal layer through a source contact; a drain electrode, wherein the drain electrode is electrically coupled to the drain metal layer through a drain contact; and A gate electrode is disposed between the source electrode and the drain electrode, wherein the source electrode, the drain electrode, and the gate electrode form a transistor. The semiconductor device of claim 1, wherein the substrate is a ceramic substrate, and the materials of the ceramic substrate include aluminum nitride (AlN), silicon carbide (SiC), aluminum oxide (Al ₂ O) ₃ ), or a combination thereof. The semiconductor component of claim 7 further includes a packaging device for multiplying the transistor, and the packaging device includes: A packaging substrate, wherein the transistor is flip-chip mounted on the packaging substrate; A reinforced annular structure is provided on the packaging substrate and surrounds the transistor; and A heat sink covers the transistor and the reinforced ring structure. A method for forming a semiconductor element, including: provide a base; forming a seed layer on the substrate; Forming a compound semiconductor stack on the seed layer; forming a source metal layer and a drain metal layer on the compound semiconductor stack; performing a dicing process to form a dicing opening through the compound semiconductor stack and the seed layer and extending into at least a portion of the substrate; Compliantly deposit a conductive layer on the bottom and sidewalls of the cutting opening and cover the source metal layer and the drain metal layer; and Remove the portion of the conductive layer between the source metal layer and the drain metal layer. The method of forming a semiconductor device according to claim 10 further includes removing a portion of the conductive layer located at the bottom of the cutting opening. The method of forming a semiconductor device according to claim 10 further includes removing a portion of the conductive layer between the drain metal layer and the cutting opening. The method of forming a semiconductor device according to claim 10 further includes forming an insulating layer to cover the source metal layer and the drain metal layer and fill the cutting opening before removing part of the conductive layer. The method of forming a semiconductor device according to claim 13, further comprising patterning the insulating layer to form a first opening, a second opening and a third opening, wherein: The first opening exposes a portion of the conductive layer located at the bottom of the cutting opening; The second opening exposes the portion of the conductive layer located on the top surface of the source metal layer and the top surface of the drain metal layer; and The third opening exposes a portion of the conductive layer between the source metal layer and the drain metal layer and a portion between the drain metal layer and the cutting opening close to the drain metal layer. The method of forming a semiconductor device according to claim 13, further comprising patterning the insulating layer to form a first opening and a second opening, wherein: the first opening exposes the conductive layer located on the source metal layer and the drain The part between the metal layers and the part between the drain metal layer and the cutting opening close to the drain metal layer; and the second opening exposes the conductive layer on the top surface of the source metal layer and the drain The top surface of the metal layer. The method of forming a semiconductor device according to any one of claims 14 and 15, further comprising forming a bonding pad in the second opening and disposing it on the portion of the conductive layer exposed by the second opening. The method of forming a semiconductor device according to claim 16, further comprising, before forming the bonding pad, coating a photoresist layer on the insulating layer, and then patterning the photoresist layer to form a photoresist opening corresponding to the second opening. . The method of forming a semiconductor element as claimed in claim 10, wherein the method of depositing the conductive layer includes a sputtering process and an evaporating process. The method of forming a semiconductor device according to claim 10, wherein the method of removing the portion of the conductive layer includes a wet etching process. The method of forming a semiconductor element as claimed in claim 10, further comprising: thinning the substrate after removing part of the conductive layer; and A singulation process is performed on the thinned portion of the substrate located under the cutting opening. As claimed in claim 20, the method for forming a semiconductor element, wherein the method for thinning the substrate includes a Taiko grinding process and a non-Taiko grinding process, and the single crystallization process includes a blade saw and a crystal. Die break dicing. The method of forming a semiconductor device according to claim 16 further includes performing a packaging process, including: forming a solder ball on the bonding pad; flip-chip connecting the solder ball to a packaging substrate; and forming a heat sink opposite to the substrate. on the other side of the seed layer; and forming a reinforced annular structure to support the space between the packaging substrate and the heat sink.

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