JP2004311538A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a module to be more reduced in wiring inductance so as to prevent high-frequency oscillations from occurring. <P>SOLUTION: An IGBT chip 3A is equipped with an insulating layer 17 formed on its main surface 3AS1 so as to cover only a gate wiring pattern 3AG (1), and a metal layer 10 formed on its main surface 3AS1 so as to cover an emitter electrode and the insulating layer 17 together. The flat end face 5BES of a first external connection main circuit terminal 5B1 whose other end is supported with a resin case is wholly face-bonded to the flat top surface 10S of the metal layer 10 by cold welding. Therefore, wiring inductance can be more reduced than a case in which a rugged structure is provided on the end face of the external connection main circuit terminal, which is conducive to the prevention of high-frequency oscillations. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to improving the electrical characteristics of a high withstand voltage and high current semiconductor module.
[0002]
[Prior art]
As a semiconductor module having a power semiconductor chip bonded on an insulating substrate, there are, for example, those disclosed in Patent Documents 1 to 4.
[0003]
[Patent Document 1]
JP-A-7-94673 (FIG. 3)
[Patent Document 2]
JP 2000-26251 A (FIG. 1)
[Patent Document 3]
JP-A-8-8395 (FIG. 1)
[Patent Document 4]
JP-A-5-160339 (FIG. 1)
[0004]
[Problems to be solved by the invention]
Depending on the relationship between the wiring inductance inside the module and the output capacitance of the IGBT chip, a resonance phenomenon called high-frequency vibration may occur under arbitrary conditions. The electromagnetic noise called high-frequency vibration may cause an operation failure of the information communication device. Therefore, it is required to reduce the wiring inductance as much as possible. From this viewpoint, the structures disclosed in Patent Documents 1 to 4 cannot be said to be sufficient.
[0005]
Therefore, an object of the present invention is to provide a more preferable structure for reducing the above problems.
[0006]
[Means for Solving the Problems]
The present invention relates to a power semiconductor chip having a first main surface on which a gate wiring pattern and a first main electrode are formed and a second main surface opposed to the first main surface and having a second main electrode formed thereon. A power semiconductor chip, wherein the power semiconductor chip includes an insulating layer formed on the first main surface so as to cover only the gate wiring pattern; A metal layer formed on the first main surface so as to cover both the electrode and the insulating layer; the other end of the external connection main circuit terminal is supported by the resin case; and One end surface of the external connection main circuit terminal is directly surface-bonded to the upper surface of the metal layer.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
FIG. 1 is a top view showing a base plate 1 used in the semiconductor module according to the present embodiment, and FIG. 2 shows the base plate 1 from the back surface of a resin case (reference numeral 100 indicates an outer frame of the case). Positions of first external connection main circuit terminals (hereinafter simply referred to as first main circuit terminals) 5B1 and 5B2 and second external connection main circuit terminals (hereinafter simply referred to as second main circuit terminals) 5A when viewed. It is a rear view which shows a relationship typically. As shown in FIGS. 1 and 2, the first main circuit terminals 5B1 and 5B2 are connected to first main electrodes (emitter electrodes, anode electrodes: not shown) formed on the first main surfaces of the power semiconductor chips 3A and 3B. ), Directly connected. Since this point is a core part of the present embodiment, it will be described later with reference to FIG. 3 which is an enlarged view of part A in FIG. The second main circuit terminal 5A is directly connected to the electrode pattern 2AP formed on the upper surface of the insulating metallized substrate 2A. The collector electrode (not shown) formed on the back surface (second main surface) of the IGBT chip 3A and the cathode electrode (second surface) formed on the back surface (second main surface) of the freewheel diode 3B. The main electrodes (not shown) are both soldered to the electrode pattern 2AP.
[0008]
The base plate 1 is, for example, a metal plate made of Cu or AlSiC or Cu-Mo material, the surface of which is plated with Ni, and the upper surface on which the insulating metallized substrate 2A is mounted. Is coated with a resist for positioning.
[0009]
The insulating metallized substrate 2A is made of, for example, an AlN substrate having a thickness of 0.635 mm, and a copper plate having a thickness of about 0.1 to 0.35 mm is bonded to both surfaces of the AlN substrate by an active metal method or a direct bonding method. ing. The surface of the copper plate is plated with Ni. The upper surface of the Ni-plated surface corresponds to the electrode pattern 2AP on which the semiconductor chips 3A and 3B are mounted. Moreover, a resist for positioning each chip is applied on the electrode pattern 2AP. On the other hand, the lower surface of the Ni plating surface is soldered to the upper surface of the base plate 1.
[0010]
The power semiconductor chip (IGBT chip) 3A has a plurality of IGBT segments in a silicon substrate, and furthermore, a gate wiring arranged so as to divide an emitter electrode (first main electrode) and an adjacent emitter electrode. A first main surface 3AS1 (FIG. 3) on which the pattern 3AG (FIG. 3) is formed, and a second main surface 3AS2 (FIG. 3) facing the first main surface 3AS1 and on which the collector electrode (second main electrode) is formed. FIG. 3). As described above, the power semiconductor chip (diode chip) 3B has the first main surface on which the anode electrode is formed and the second main surface on which the cathode electrode is formed.
[0011]
The resin case is fixed to the base plate 1 with screws or silicone rubber. As a result, the insulating metallized substrate 2A, the power semiconductor chips 3A and 3B, and the IGBT chip driver substrate 2C are incorporated in a manner surrounded by the internal space formed by the resin case and the base plate 1. Then, a silicon gel (not shown) is injected and baked from a case opening (not shown) to a height capable of protecting the entire surface of the power semiconductor chips 3A and 3B.
[0012]
FIGS. 3A and 3B are views showing a bonding state between the first main circuit terminal 5B1 for the IGBT chip and the IGBT chip 3A, wherein FIG. 3B is a top view and FIG. , (C) is a longitudinal sectional view taken along line II-II.
[0013]
As shown in FIG. 3, in the IGBT chip 3A, {circle around (1)} only the respective gate wiring patterns 3AG formed in the active region 3AR on the first main surface 3AS1 except for the gate extraction electrode portion of the gate pad region GPR. The insulating layer 17 formed on the first main surface 3AS1 so as to cover and insulate them all, and (2) all the first main electrodes (not shown) in the active region 3AR except for the gate pad region GPR. ) And a metal layer (for example, an aluminum film) 10 formed on the first main surface 3AS1 so as to cover both surfaces of the insulating layer 17. The exposed gate extraction electrode portion of the exposed gate pad region GPR is connected to a terminal (not shown) by a bonded wire 18.
[0014]
The other end of the IGBT chip first main circuit terminal 5B1 is supported by a resin case, not shown, and extends from the other end to a position directly above the IGBT chip 3A. One end face (bottom face) 5BES of a size included in the active region 3AR and smooth (flat) is provided.
[0015]
Then, the entire surface of the one end surface 5BES of the first main circuit terminal 5B1 is directly surface-bonded to the upper surface of the metal layer 10 by pressing or fixing with an adhesive. Thereby, the electrical connection between the first main circuit terminal 5B1 and the first main electrode (emitter electrode) of the IGBT chip 3A is made via the metal layer 10 and without causing a short circuit state with each gate wiring pattern 3AG. Contact or continuity is achieved. In this case, the wiring between the two portions 5BES and 10 is secured by surface contact between the two flat portions, so that wire bonding with the first main circuit terminal is performed in the region 2B of FIG. The wiring inductance can be drastically reduced as compared with the conventional case, and moreover, compared with the case where the uneven shape is provided as in Patent Document 1 and local contact with the protrusion is performed, The structure of the present embodiment is advantageous in that the contact area can be increased to further reduce the wiring inductance.
[0016]
Moreover, according to the present embodiment, it is expected that the heat radiation characteristics during energization will be improved by increasing the contact area between first main circuit terminal 5B1 and IGBT chip 3A. Further, since the one end 5BE has a simple shape, a reduction in the manufacturing cost of the first main circuit terminal 5B1 can be expected. In addition, the short circuit between the first main circuit terminal 5B1 and each gate wiring pattern 3AG does not occur, so that the reliability of the module can be improved. Further, the present embodiment can contribute to downsizing of the device.
[0017]
Note that the insulating layer 17 and the metal layer 10 thereover may be provided only at least in the contact area with the one end face 5BES (the area of the one end face 5BES) of the first main circuit terminal 5B1.
[0018]
(Embodiment 2)
This embodiment relates to an improvement of the first embodiment. The feature of this embodiment is that a gate connection terminal 11 (FIG. 4) is provided for the first main circuit terminal 5B1 in the first embodiment, and a wire 18 in the gate pad region GPR is provided. By eliminating the need for bonding, the wiring inductance can be further reduced. Therefore, hereinafter, only the differences will be described based on the drawings, and the description of the first embodiment will be cited for the description of the common members.
[0019]
FIG. 4 is a diagram showing a bonding state between the IGBT chip first main circuit terminal 5B1 with the gate connection terminal 11 and the IGBT chip 3A. Among them, (B) is a top view, (A) is a vertical cross-sectional view along line II, and (C) is a vertical cross-sectional view along line III-III when cut along a plane perpendicular to the paper surface. FIG. 5 is an enlarged longitudinal sectional view showing the internal structure of the gate connection terminal 11 at the portion B in FIG. 4C. Further, FIG. 6 is a diagram showing a hollow structure in the intermediate portion or the extension portion 5BI of the first main circuit terminal 5B1, when the line is taken along a plane perpendicular to the paper surface with respect to the line IV-IV in FIG. Corresponds to the cross-sectional view. The presence of the annular insulator 19 in FIG. 6 is optional.
[0020]
As shown in FIGS. 4 to 6, a part of the gate wiring pattern 3AG, that is, the upper surface of the gate extraction electrode portion of the gate pad region GPR connected to each pattern 3AG is not covered with the insulating layer 17 but is exposed to the outside. It is exposed. This is the same as the first embodiment. Then, a part of the intermediate portion (extended portion) 5BI connecting the other end (not shown) of the first main circuit terminal 5B1 on the resin case side and one end surface 5BES or one end portion 5BE (one end portion 5BE side). A gate connection terminal 11 having an L-shaped vertical cross-sectional shape extends from the junction 5BJP to a position just above the upper surface of the gate extraction electrode portion in the gate pad region GPR. Is a cylindrical insulator 15, and a columnar metal 12 is inserted into an opening at a tip 15E of the cylindrical insulator 15. One end surface (gate electrode connection surface) 12S1 of the metal 12 is provided. Are surface-bonded (surface-contacted) directly to the exposed upper surface portion 3AGES of the gate wiring pattern 3AG in the gate pad region GPR, for example, by pressure welding.
[0021]
In addition, in the internal space of the cylindrical insulator 15 of the gate connection terminal 11, a spring 13 for applying a pressing force (elastic force) to the metal 12, and another end surface 12S2 receiving the pressing of the metal 12 are joined. An electric wire 16 having one end is incorporated. In addition, the gate resistor 14 provided in the driver board 2C of FIG. 1 in the conventional module is provided in the middle of the extension of the electric wire 16 in the internal space of the tubular insulator 15.
[0022]
Moreover, in the first main circuit terminal 5B1, at least the intermediate portion 5BI from the other end to the joining portion 5BJP is a cylindrical metal body. Then, the electric wire 16 extends in the space of the tubular insulator 15 to reach the joint portion 5BJP, and further enters the tubular metal body of the first main circuit terminal 5B1, and then enters the first main circuit terminal 5B1. Extends toward the other end of the cylindrical metal body. In this case, the insulator 19 may be interposed.
[0023]
With the above configuration, the following effects can be obtained.
[0024]
The gate connection terminal 11 and the gate extraction electrode portion, which extend the continuity between the gate extraction electrode portion of the gate pad region GPR and the external terminal from a position near the gate extraction electrode portion side in the first main circuit terminal 5B1. This is achieved by direct surface contact with For this reason, since wire bonding in the gate pad region GPR becomes unnecessary, in addition to the further reduction of the wiring inductance in the conductive portion on the side of the emitter electrode obtained in Embodiment 1, the wiring inductance on the gate electrode side is reduced. As a result, the high frequency vibration can be significantly suppressed. Needless to say, similarly to the first embodiment, the number of components can be reduced (the wire bonding area 2B in FIG. 1 is deleted) and the size of the case can be reduced.
[0025]
In addition, since the gate resistor 14 is provided in the middle of the extension of the electric wire 16 in the tubular insulator 15, the insulating metallized substrate 2C for the gate resistor in FIG. 1 can be omitted. It is possible to further reduce the number of parts and promote the downsizing of the case. In addition, since the gate resistor 14 is provided immediately above the gate pad region GPR, the wiring inductance generated on the gate driver substrate side can be reduced. In this respect, the wiring inductance of the entire module can be reduced. Can contribute. Further, since the arrangement of the power semiconductor chip is not restricted as in the conventional wire bond wiring structure, the degree of freedom in the arrangement of the power semiconductor chip on the insulating metallized substrate is increased (as a result, the arrangement having good heat radiation efficiency) Can be selected).
[0026]
(Embodiment 3)
The present embodiment also relates to an improvement of the first embodiment, and a cross-sectional view of FIG. 7 is presented as a drawing showing its features. The feature point shown in FIG. 7 is a gate terminal (metal body) that can be directly in electrical contact with gate pad region GPR from above gate pad region GPR instead of wire 18 of IGBT chip 3A in the first embodiment. 5B3 is additionally provided.
[0027]
Thus, the present embodiment is characterized in that the members required in the first embodiment, that is, (1) the wire 18 connecting the gate pad region GPR and the electrode on the driver substrate 2C of FIG. The driver board 2C having an external extraction electrode portion (not shown) connected to the external extraction terminal of the case by wire is unnecessary.
[0028]
Here, the other end (not shown) of the gate terminal 5B3 is directly joined to and supported by an external extraction terminal (not shown) of the resin case, and a bottom surface or an end surface 5B3ES at one end 5B3E of the terminal 5B3. Are provided just above the gate pad region GPR so as to be vertically movable. Then, as illustrated in FIG. 7, for example, the gate pad metal layer 10A provided on the gate pad region GPR and the gate terminal end face 5B3ES are electrically and mechanically mutually soldered. Join. Alternatively, even if the metal terminal 10A is not provided and the gate terminal end face 5B3ES is directly (plane) pressed into contact with the gate pad region GPR, electrical and mechanical contact between the two members 5B3 and GPR is realized. good.
[0029]
Other points are the same as the first embodiment.
[0030]
As described above, one end face 5B3ES of the gate terminal 5B3 whose other end is supported by the external extraction terminal of the resin case is entirely on the exposed portion GPR of the gate wiring pattern directly or via the metal layer 10A. Surface bonded. Therefore, according to the present embodiment, since the gate terminal 5B3 is taken out from the gate pad region GPR vertically upward to the external take-out terminal, the gate drive substrate arranged adjacent to the power insulating substrate 2A is taken out. The metal base plate 1A can be made unnecessary (naturally, wire bonding therefor is also unnecessary), and a metal base plate 1A having a smaller size in a planar direction than the metal base plate 1 according to the first embodiment is provided. The advantage that it can be obtained is obtained.
[0031]
(Note)
As described above, the embodiments of the present invention have been disclosed and described in detail. However, the above description exemplifies applicable aspects of the present invention, and the present invention is not limited thereto. That is, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.
[0032]
【The invention's effect】
According to the present invention, one end face of the external connection main circuit terminal is entirely surface-bonded directly to the upper surface of the metal layer, so that the uneven structure is provided on one end face of the external connection main circuit terminal. In addition, the effect is obtained that the wiring inductance can be further reduced and the generation of high-frequency vibration can be suppressed.
[Brief description of the drawings]
FIG. 1 is a top view showing a base plate used for a semiconductor module according to the present embodiment.
FIG. 2 is a rear view schematically showing a positional relationship between a first external connection main circuit terminal and a second external connection main circuit terminal when the base plate is viewed from the back surface of the resin case.
FIG. 3 is a diagram illustrating a bonding state between a first main circuit terminal for an IGBT chip and an IGBT chip;
FIG. 4 is a diagram showing a bonding state between a first main circuit terminal for an IGBT chip with a gate connection terminal and the IGBT chip.
FIG. 5 is an enlarged longitudinal sectional view showing a structure of a gate connection terminal.
FIG. 6 is a cross-sectional view showing a hollow structure in an intermediate portion of the first main circuit terminal.
FIG. 7 is a cross-sectional view schematically illustrating a contact relationship between an IGBT chip on a metal base plate and a gate terminal according to the third embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Base board, 2A insulating metallized board, 3A IGBT chip, 5B1 1st external connection main circuit terminal for IGBT chips, 5A 2nd external connection main circuit terminal, 10 metal layers, 12 metals, 14 gate resistance, 15 cylindrical insulator , 16 electric wires, 17 insulating layers, 5B3 gate terminal.

Claims (2)

A power semiconductor chip having a first main surface on which a gate wiring pattern and a first main electrode are formed and a second main surface facing the first main surface and having a second main electrode formed therein is assembled in a resin case. A semiconductor device that is modularized
The power semiconductor chip,
An insulating layer formed on the first main surface so as to cover only the gate wiring pattern;
A metal layer formed on the first main surface so as to cover both the first main electrode and the insulating layer;
The other end of the external connection main circuit terminal is supported by the resin case, and
One end surface of the external connection main circuit terminal is entirely surface-bonded directly to the upper surface of the metal layer,
Semiconductor device. The semiconductor device according to claim 1,
A part of the gate wiring pattern is exposed without being covered with the insulating layer,
One end surface of the gate terminal whose other end is supported by the resin case is entirely joined to the exposed portion of the gate wiring pattern,
Semiconductor device.

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