JP2004304158A - Capacitor, capacitor with semiconductor element, substrate with capacitor, structure composed of semiconductor element, capacitor, and substrate, intermediate substrate, intermediate substrate with semiconductor element, substrate with intermediate substrate, and structure composed of semiconductor element, intermediate substrate, and substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive structure that is excellent in noise eliminating ability, can be manufactured easily, and is composed of a semiconductor element, a capacitor, and a substrate. <P>SOLUTION: This structure 11 is composed of the semiconductor element 21, capacitor 31, and substrate 41. The semiconductor element 21 has surface connector terminals 22, and the substrate 41 has surface connector pads 46. In addition, the capacitor 31 has a capacitor main body 38 and a plurality of conductor columns 35. The semiconductor element 21 is mounted on the first surface 32 of the capacitor main body 38, and the second surface 33 of the main body 38 is mounted on the surface of the substrate 41. The plurality of conductor columns 35 are connected to the surface connector terminals 22 and surface connector pads 46 through the first and second surfaces 32 and 33 of the capacitor main body 38. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a capacitor, a capacitor with a semiconductor element, a substrate with a capacitor, a structure including a semiconductor element, a capacitor, and a substrate, a relay substrate, a relay substrate with a semiconductor element, a substrate with a relay substrate, a semiconductor element, a relay substrate, and a substrate. It is related to a structure that becomes.

  2. Description of the Related Art In recent years, various structures have been known in which a relay board called an interposer is interposed between an IC chip and a wiring board, instead of directly connecting the IC chip and the wiring board. By the way, the operation of the IC chip is becoming faster and faster due to the advance of the integrated circuit technology. However, noise is superimposed on the power supply wiring and the like, which may cause a malfunction. Therefore, measures have been taken in the above-described structure to remove noise and supply a good power to the IC chip. For example, it has already been proposed to embed a capacitor on the wiring board side and connect the capacitor and an IC chip via a conductor in an interposer (for example, see Patent Document 1).

JP-A-2000-349225 (FIGS. 26, 28, etc.)

  Generally, when there is a wiring (capacitor connection wiring) connecting a capacitor and an IC chip, the longer the capacitor connection wiring, the higher the possibility that noise is superimposed at that location. Therefore, in order to enhance the noise removal capability, it is preferable that the capacitor connection wiring be as short as possible.

  However, in the above-described structure in which the capacitor is embedded on the wiring board side, the length of the wiring (capacitor connection wiring) connecting the capacitor and the IC chip is necessarily longer than the thickness of the interposer. Therefore, it has been considered that it is necessary to take some new countermeasures in order to achieve a further reduction in noise and improve the reliability of the structure.

  In addition, in the above structure in which the capacitor is embedded in the wiring board side, even if only the capacitor becomes defective due to a short circuit or poor insulation resistance, the entire value-added wiring board has to be discarded. . For this reason, the amount of loss becomes large, and it becomes difficult to manufacture at low cost after all.

  Further, as one method for achieving low resistance and low inductance, an increase in the size of the capacitor (in other words, an increase in the capacity) can be considered. However, in recent wiring boards, conductive circuits are often formed densely over a plurality of layers, and there is not enough space to embed a large capacitor in the first place. In addition, if a large capacitor is buried by force, the degree of freedom in forming a conductor circuit is reduced, and there is a possibility that the formation of the conductor circuit becomes extremely difficult.

  The present invention has been made in view of the above problems, and its object is to provide a structure including a semiconductor element, a capacitor, and a substrate, which is excellent in noise removal capability, and is inexpensive and easy to manufacture, a semiconductor element, a relay board, An object of the present invention is to provide a structure including a substrate.

  Another object of the present invention is to provide a capacitor, a capacitor with a semiconductor element, a substrate with a capacitor, a relay board, a relay board with a semiconductor element, and a board with a relay board, which are suitable for realizing the above-mentioned excellent structure. Is to do.

  Means for solving the above problems include a semiconductor element having a surface connection terminal, a substrate having a surface connection pad, and mounting on the first surface on which the semiconductor element is mounted and on the surface of the substrate. And a plurality of conductor pillars penetrating the first surface and the second surface and electrically connected to the surface connection terminals and the surface connection pads. There is a structure including a semiconductor element, a capacitor, and a substrate, which is characterized by including a capacitor.

  Further, in order to realize the above-described structure including the semiconductor element, the capacitor, and the substrate, a preferable example is a substantially plate having a first surface on which a semiconductor element having surface connection terminals is to be mounted and a second surface having a second surface. There is provided a capacitor comprising: a capacitor main body having a shape; and a plurality of conductor columns that penetrate the first surface and the second surface and are to be electrically connected to the surface connection terminal. Furthermore, a first plate on which a semiconductor element having a surface connection terminal is provided, and a first plate on which the semiconductor element is mounted, and a substantially plate-shaped capacitor body having a second surface, and the first surface and the second surface are formed. A capacitor with a semiconductor element, characterized by comprising a capacitor having a plurality of conductor columns that penetrate and are electrically connected to the surface connection terminal, is also suitable. In addition, a substantially plate-shaped capacitor body including a substrate having surface connection pads, and having a first surface and a second surface mounted on the surface of the substrate, the first surface and the second surface are provided. A substrate with a capacitor, comprising a capacitor having a plurality of conductor pillars penetrating therethrough and electrically connected to the surface connection pad, is also suitable.

  Therefore, according to the above-described structure, the capacitor itself has a function as a relay board itself, and is arranged at a position where the relay board should be. That is, the semiconductor element and the capacitor are arranged closer to each other as compared with the conventional structure, and the two are directly connected. For this reason, it is possible to make the wiring (capacitor connection wiring) connecting the semiconductor element and the capacitor very short, or even completely eliminate it. Therefore, noise that enters between the semiconductor element and the capacitor can be extremely reduced, and high reliability can be obtained without causing a malfunction such as a malfunction.

  Further, even if a failure occurs in the capacitor, the capacitor is not buried in the substrate side, so it is sufficient to discard only the capacitor, without disposing the entire substrate. Therefore, compared to the conventional structure in which a capacitor is buried on the substrate side, the amount of loss is small and it is possible to manufacture at low cost. In addition, since the capacitor is not buried on the substrate side, there is no space restriction, and the capacitor can be relatively easily enlarged (increased in capacity), and the substrate can be easily manufactured. Become.

Here, an element having a surface connection terminal is used as the semiconductor element. The surface connection terminal refers to a terminal for electrical connection, which is connected by surface connection. Note that surface connection refers to a case where pads or terminals are formed in a line or lattice (including a staggered shape) on the plane of a connected object, and the pads or terminals are connected to each other. The size and shape of the semiconductor element are not particularly limited, but it is preferable that the semiconductor element is a large-sized semiconductor element having at least one side of 10 mm or more. Further, the coefficient of thermal expansion of the semiconductor element is preferably 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C. Specific examples of such a semiconductor element include a semiconductor integrated circuit chip (IC chip) made of silicon having a thermal expansion coefficient of about 3.0 ppm / ° C.
In the present specification, the term “coefficient of thermal expansion” means a coefficient of thermal expansion (CTE) in a direction (XY direction) orthogonal to the thickness direction (Z direction), and is 0 ° C. to 100 ° C. Mean the value measured by TMA (thermomechanical analyzer). “TMA” refers to thermomechanical analysis, for example, as defined in JPCA-BU01.

  A substrate having surface connection pads is used as the substrate. Examples of the substrate include a substrate on which a semiconductor element and other electronic components are mounted, in particular, a wiring substrate on which a semiconductor element and other electronic components are mounted and provided with a conductor circuit for electrically connecting them. . The material for forming the substrate is not particularly limited, and can be appropriately selected in consideration of cost, workability, insulation, mechanical strength, and the like. Examples of the substrate include a resin substrate, a ceramic substrate, and a metal substrate.

  Specific examples of the resin substrate include an EP resin (epoxy resin) substrate, a PI resin (polyimide resin) substrate, a BT resin (bismaleimide-triazine resin) substrate, and a PPE resin (polyphenylene ether resin) substrate. In addition, a substrate made of a composite material of these resins and organic fibers such as glass fiber (glass woven fabric or glass nonwoven fabric) or polyamide fiber may be used. Alternatively, a substrate made of a resin-resin composite material in which a thermosetting resin such as an epoxy resin is impregnated into a three-dimensional network-like fluororesin base material such as continuous porous PTFE may be used. Specific examples of the ceramic substrate include, for example, a substrate made of a low-temperature firing material such as an alumina substrate, a beryllia substrate, a glass ceramic substrate, and crystallized glass. Specific examples of the metal substrate include, for example, a copper substrate, a copper alloy substrate, a substrate made of a single metal other than copper, and a substrate made of an alloy of a metal other than copper. Most of the resin substrates and ceramic substrates listed here have a thermal expansion coefficient of 5.0 ppm / ° C. or more.

  The surface connection pad refers to a terminal pad for electrical connection, which is connected by surface connection. Such surface connection pads are formed in, for example, a linear shape or a lattice shape (including a staggered shape).

  The capacitor is a so-called via array type capacitor (capacitor) having a capacitor body and a plurality of conductor columns. In this type of capacitor, a first inner layer electrode connected to a first conductor pillar and a second inner layer electrode connected to a second conductor pillar are alternately formed inside a dielectric layer constituting a capacitor body. I have.

  The plurality of conductor pillars penetrate the first surface and the second surface, one end of which is connected to a surface connection terminal, and the other end of which is connected to a surface connection pad. Such a conductive column is formed by providing a columnar conductive material in a through hole formed in the capacitor body. The conductive material is not particularly limited, and includes, for example, a metal containing one or more selected from copper, gold, silver, platinum, palladium, nickel, tin, lead, solder, tungsten, molybdenum, titanium, and the like. be able to. A well-known method can be used to form the conductive pillar, and examples thereof include filling of a paste containing a conductive metal, plating of a conductive metal, and press-fitting of a pin-shaped conductive metal material. In the case where conductive pillars are formed by filling conductive paste into the through holes of the ceramic substrate, a method of simultaneously sintering the substrate and the paste (simultaneous firing method) may be adopted, or the substrate may be baked first. After bonding, a method of filling and firing the paste (post firing method) may be adopted.

  The shape of the conductor pillar may be appropriately selected according to the shape of the surface connection terminal or the surface connection pad to be connected. For example, when the surface connection terminal or the surface connection pad is flat, the conductor pillar may have a shape in which the end protrudes from the first surface and the second surface, that is, a bump shape. As for the connection between the conductor pillar and the surface connection terminal, and the connection between the conductor pillar and the surface connection pad, a method using a conductive material such as solder or a conductive resin in a state where both end surfaces are opposed to each other. Can be adopted.

The dielectric layer of the capacitor body is formed using a ceramic material. Suitable ceramic materials include, for _{example, PbTiO 2, BaTiO 3, SrTiO} 3, but there is an oxide-based ceramics such as TiO _2, may be selected non-oxide ceramics (e.g., nitride ceramics, etc.).

  The thermal expansion coefficient of the capacitor body is not limited, but is preferably lower than the thermal expansion coefficient of the substrate and less than 20.0 ppm / ° C., and more preferably less than 10.0 ppm / ° C. The coefficient of thermal expansion of the capacitor body is preferably 2.0 ppm / ° C. or more and less than 20.0 ppm / ° C., and more preferably 2.0 ppm / ° C. or more and less than 10.0 ppm / ° C. In particular, the coefficient of thermal expansion is preferably equal to or larger than the coefficient of thermal expansion of the semiconductor element in the range of 2.0 ppm / ° C. or more and less than 10.0 ppm / ° C. The reason is that if the thermal expansion coefficient of the capacitor body is less than 10.0 ppm / ° C., the difference in thermal expansion coefficient from the semiconductor element becomes sufficiently small, and the effect of thermal stress on the semiconductor element can be sufficiently reduced. . Therefore, for example, when a silicon IC chip having a coefficient of thermal expansion of about 3.0 ppm / ° C. is selected, it is preferable to use a capacitor body having a coefficient of thermal expansion of 3.0 ppm / ° C. or more and less than 5.0 ppm / ° C. It can be said that there is.

  In addition, it is preferable that the capacitor main body has high rigidity (for example, high Young's modulus) as well as low thermal expansion as described above. That is, the rigidity (for example, Young's modulus) of the capacitor body is preferably at least higher than that of the semiconductor element, and specifically, the Young's modulus is preferably 200 GPa or more, particularly 300 GPa or more. The reason is that if a high rigidity is given to the capacitor body, even if a large thermal stress is applied to the capacitor body, the capacitor body can withstand the thermal stress. Therefore, it is possible to prevent warping of the capacitor body itself and cracks at the junction of the semiconductor elements.

  Further, it is more preferable that the capacitor main body not only has the above-described low thermal expansion property and high rigidity but also has high heat radiation property. Here, “high heat dissipation” means that at least heat dissipation (for example, thermal conductivity) is higher than that of the substrate. The reason is that if a capacitor body having high heat dissipation is used, heat generated by the semiconductor element can be quickly transmitted and dissipated, so that thermal stress can be reduced. Therefore, a large thermal stress does not act, and warping of the capacitor body itself and cracks at the joints of the semiconductor elements can be prevented.

  Further, it is preferable that the relay board main body further has an insulating property. The reason is that in the capacitor body having no insulating property, it is necessary to provide an insulating layer on the dielectric layer in advance when forming the conductor pillars and electrodes, but in the capacitor body having the insulating property, it is unnecessary. Therefore, it is possible to avoid a complicated structure and an increase in man-hours.

  In view of the above, it is preferable that the capacitor body is formed using a nitride-based insulating engineering ceramic material, particularly, aluminum nitride, silicon nitride, or a mixed ceramic material of aluminum nitride and silicon nitride. Most preferably, it is formed using This is because the materials listed here have low thermal expansion, high rigidity, high heat dissipation, and insulation. Incidentally, aluminum nitride has a thermal expansion coefficient of about 4.4 ppm / ° C. and a Young's modulus of about 350 GPa. Silicon nitride has a thermal expansion coefficient of about 3.0 ppm / ° C. and a Young's modulus of about 300 GPa.

  Further, as another means for solving the above problems, a semiconductor device having surface connection terminals, a substrate having surface connection pads, and a first surface on which the semiconductor device is mounted, and a concave portion are formed. A substantially plate-shaped relay substrate main body having a second surface mounted on the surface of the substrate, and a plurality of the plurality of terminals penetrating through the first surface and the bottom surface of the concave portion and electrically connected to the surface connection terminal. A relay substrate main body-side conductor column, and a plurality of capacitor-side conductor columns penetrating the front surface and the back surface and electrically connected to the relay substrate body-side conductor column and the surface connection pad. Further, there is provided a structure comprising a semiconductor element, a relay substrate, and a substrate, wherein the structure includes a relay substrate having a capacitor disposed in the recess.

  Further, in order to realize the above-described structure including the semiconductor element, the relay substrate, and the substrate, the first surface on which the semiconductor element having the surface connection terminal is to be mounted, and the concave portion are formed. A substantially board-shaped relay substrate body having a second surface, a plurality of relay substrate body-side conductor pillars that penetrate the first surface and the bottom surface of the recess, and are to be electrically connected to the surface connection terminal; And a plurality of capacitor-side conductor posts penetrating the front and back surfaces and electrically connected to the relay substrate body-side conductor posts, and including a capacitor disposed in the recess. There is a relay board characterized by the following. A substantially plate-shaped relay board main body including a semiconductor element having a surface connection terminal and having a first surface on which the semiconductor element is mounted, and a second surface having a recess formed therein; And a plurality of relay substrate body side conductor pillars penetrating the bottom surface of the concave portion and electrically connected to the surface connection terminal, and having a front surface and a back surface, penetrating the front surface and the back surface, and the relay substrate body side A relay board with a semiconductor element, comprising a relay board having a plurality of capacitor-side conductive pillars electrically connected to the conductive pillars and having a capacitor disposed in the recess, is also suitable. . In addition, there is provided a substrate having surface connection pads, and a substantially plate-shaped relay substrate body having a first surface and a second surface formed with a recess and mounted on the surface of the substrate; A plurality of relay substrate body side conductor pillars penetrating the bottom surface of the concave portion, and has a front surface and a back surface, and is electrically connected to the relay substrate body side conductor pillar and the surface connection pad through the front surface and the back surface. And a relay board having a plurality of capacitor-side conductor pillars and a capacitor disposed in the recess.

  Therefore, according to the above-described structure, since the capacitor is disposed in the recess of the relay board, the semiconductor element and the capacitor are closer to each other than the conventional structure, and as a result, the wiring (capacitor connection) connecting the semiconductor element and the capacitor is formed. Wiring) can be made very short. Therefore, noise that enters between the semiconductor element and the capacitor can be extremely reduced, and high reliability can be obtained without causing a malfunction such as a malfunction.

  Further, even if a failure occurs in the capacitor, since the capacitor is not buried in the substrate side, the relay substrate and the capacitor need only be discarded, and the entire substrate is not discarded. Therefore, compared to the conventional structure in which a capacitor is buried on the substrate side, the amount of loss is small and it is possible to manufacture at low cost. Moreover, since the capacitor is not buried on the substrate side, it is hardly limited by space, making it relatively easy to increase the size (capacity) of the capacitor and manufacturing the substrate. It will be easier.

  Here, as the semiconductor element and the substrate, the same structure as the above-described structure including the semiconductor element, the capacitor, and the substrate can be used.

  The relay board has a substantially board-shaped relay board body. The relay board main body has a first surface and a second surface, and a semiconductor element is mounted on the first surface, and a second surface is mounted on the surface of the substrate. In addition, a concave portion for disposing a capacitor is provided on the second surface of the relay board main body. The number of the concave portions may be singular or plural. The shape and size of the concave portion are not particularly limited as long as the capacitor can be arranged inside. Note that the side surface and the bottom surface of the concave portion opened on the second surface are grasped as a part of the second surface.

  The thermal expansion coefficient of the relay substrate body is preferably lower than the thermal expansion coefficient of the substrate, and specifically, is preferably less than 10.0 ppm / ° C. The thermal expansion coefficient of the main body of the relay board is more preferably 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C., and particularly in the range of 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C. It is better that the value is larger than the coefficient of thermal expansion of the semiconductor element. The reason is that if the thermal expansion coefficient of the relay substrate body is less than 10.0 ppm / ° C. (especially less than 5.0 ppm / ° C.), the difference in thermal expansion coefficient from the semiconductor element can be sufficiently reduced, and the thermal stress on the semiconductor element can be reduced. This is because the effect of the above can be sufficiently reduced. Therefore, for example, when a silicon IC chip having a thermal expansion coefficient of about 3.0 ppm / ° C. is selected, it is preferable to use a relay substrate body having a thermal expansion coefficient of 3.0 ppm / ° C. or more and less than 5.0 ppm / ° C. It can be said that It is more preferable that the relay board body has a lower thermal expansion property than the capacitor. In this case, even if a capacitor having a large thermal expansion coefficient is used, the thermal expansion coefficient of the entire relay substrate can be reduced by using the relay substrate body.

  In addition, it is preferable that the relay board main body has high rigidity (for example, high Young's modulus) as well as low thermal expansion as described above. That is, the rigidity (for example, Young's modulus) of the relay substrate body is preferably higher than at least that of the semiconductor element, and specifically, the Young's modulus is preferably 200 GPa or more, particularly 300 GPa or more. The reason is that if a high rigidity is given to the relay board main body, even if a large thermal stress is applied to the relay board main body, the relay board main body can withstand the thermal stress. Therefore, it is possible to prevent warpage of the relay substrate body itself and cracks at the junction of the semiconductor elements. It is more preferable that the relay substrate body has higher rigidity (for example, higher Young's modulus) than the capacitor. In this case, even if a capacitor having low rigidity is used, it can be reinforced and protected by the relay substrate main body, so that the rigidity of the entire relay substrate can be increased.

  Further, it is more preferable that the relay board main body not only has the above-described low thermal expansion property and high rigidity but also has high heat radiation property. The reason is that if a relay board body having high heat dissipation is used, the heat generated by the semiconductor element can be quickly transmitted and dissipated, so that thermal stress can be reduced. Therefore, a large thermal stress does not act, and it is possible to prevent warpage of the relay substrate body itself and cracks at the joints of the semiconductor elements.

  Further, it is preferable that the relay board main body further has an insulating property. The reason is that, in the case of the relay board body having no insulating property, it is necessary to provide an insulating layer in advance at the time of forming the conductor pillar, but in the case of the relay board body having the insulating property, it is unnecessary. Therefore, it is possible to avoid a complicated structure and an increase in man-hours.

  In view of the above, it is preferable that the relay substrate body be formed using a nitride-based insulating engineering ceramic material, and particularly, aluminum nitride, silicon nitride, or a mixed ceramic of aluminum nitride and silicon nitride. Most preferably, it is formed using a material. This is because the materials listed here have low thermal expansion, high rigidity, high heat dissipation, and insulation.

  Of course, alumina-based ceramic materials also have large thermal expansion compared to nitride-based insulating engineering ceramic materials, but have favorable thermal and mechanical properties, making them suitable as materials for relay board bodies. I have. Alumina-based ceramic materials have the advantage of being less expensive than nitride-based insulating engineering ceramic materials. Further, although it is inferior in mechanical properties to alumina-based ceramic materials, it is also possible to use low-temperature fired ceramics or the like having low thermal expansion as a material for the relay substrate body. It should be noted that the use of a low-temperature fired ceramic material such as glass ceramic or crystallized glass is preferable for achieving a lower resistance of the conductor pillar. The reason is that a conductor pillar can be formed using a good conductor such as copper or silver in the case of a low-temperature fired ceramic material.

  The relay board has a plurality of relay board body-side conductor pillars. The relay substrate main body-side conductor pillar penetrates the first surface and the bottom surface of the recess, one end of which is electrically connected to the surface connection terminal, and the other end of which is electrically connected to the capacitor-side conductor pillar. The relay board penetrates outside the recess forming area (the outer peripheral portion of the recess) on the first surface and the second surface, and one end thereof is electrically connected to the surface connection terminal, and the other end is electrically connected to the surface connection pad. It may further have a relay substrate main body side conductive pillar to be electrically connected.

  Also, the relay board includes a so-called via array type capacitor (capacitor) having a plurality of capacitor-side conductor pillars. Such a capacitor-side conductor pillar is formed so as to penetrate the front and back surfaces of the capacitor, one end of which is connected to the relay substrate body-side conductor pillar, and the other end of which is connected to the surface connection pad.

  The relay substrate body-side conductor pillar and the capacitor-side conductor pillar are formed by providing a pillar-shaped conductive material in a through-hole formed in the relay board body or the capacitor. The conductive material is not particularly limited, and includes, for example, a metal containing one or more selected from copper, gold, silver, platinum, palladium, nickel, tin, lead, solder, tungsten, molybdenum, titanium, and the like. be able to. Further, in forming the relay substrate main body-side conductor pillars and the capacitor-side conductor pillars, well-known methods can be adopted, for example, filling of paste containing conductive metal, plating of conductive metal, pin-shaped conductive metal material And press-fitting. When a conductive paste is filled in the through-hole of the ceramic relay substrate body or the capacitor to form the conductive pillar, a co-firing method or a post-firing method may be employed.

  The shape of the relay substrate body-side conductor pillar may be appropriately selected according to the shape of the surface connection terminal, capacitor-side conductor pillar, and surface connection pad to be connected. The shape of the capacitor-side conductor pillar may be appropriately selected according to the shape of the relay board main body side and the surface connection pad to be connected.

  In addition, as the plurality of relay board main body-side conductor pillars penetrating the first surface and the bottom surface of the concave portion, one end of which is electrically connected to the surface connection terminal and the other end is electrically connected to the capacitor-side conductor pillar. For example, it is preferable that a plurality of relay board main body-side conductor posts for ground and a plurality of relay board main body-side conductor posts for power supply be assigned. Both of these two types of relay substrate body-side conductor pillars are arranged in the recess forming region of the relay substrate body. On the other hand, the first surface and the second surface penetrate outside the concave portion forming region (the outer peripheral portion of the concave portion), and one end thereof is electrically connected to the surface connection terminal, and the other end is electrically connected to the surface connection pad. As the relay substrate body-side conductor pillar, for example, a signal line relay substrate body-side conductor pillar is preferably assigned. The reason for this is that, in general, the surface connection terminals for signal lines are laid out around the surface connection terminal for ground and the surface connection terminal for power supply in the semiconductor element, and the relay board side is made to conform to the layout.

  In this case, it is preferable that the plurality of capacitor-side conductor pillars include a ground-side capacitor-side conductor pillar and a power-source capacitor-side conductor pillar. The ground-side capacitor-side conductor pillar is electrically connected to the grounding relay substrate body-side conductor pillar. The power supply capacitor-side conductor post is electrically connected to the power supply relay board main body-side conductor post.

  A plurality of short conductor columns for ground and a conductor column pitch conversion layer penetrating the first surface are formed inside the relay substrate body, and at least a part of the plurality of short conductor columns for ground is formed. An electrical component may be electrically connected to the ground-side capacitor-side conductor pillar via the conductor pillar pitch conversion layer. Here, the conductor pole pitch conversion layer refers to a layered conductive portion interposed to convert the pitch of the ground capacitor-side conductor columns (center-to-center distance between adjacent ground capacitor-side conductor columns). . One or more conductive pillar pitch conversion layers are formed inside the relay board body. The short conductor pillar for ground means a conductor pillar that does not reach the second surface because it has a shorter length than the conductor pillar on the relay board main body side for ground, which is allocated for ground. . Therefore, the short conductor pillar for ground penetrates only the first surface. The inner ends of at least some of the plurality of short ground conductor pillars are connected to the conductor pillar pitch conversion layer.

  Normally, the pitch of the grounding relay substrate body-side conductor pillars (that is, the center-to-center distance between adjacent grounding relay board body-side conductor pillars) is the pitch of the surface connection terminals of the semiconductor element (the center-to-center distance of the adjacent surface connection terminals). ). Therefore, if an attempt is made to electrically connect the ground relay substrate body-side conductor pillar and the ground capacitor-side conductor pillar without going through this kind of conductor pillar pitch conversion layer, the pitch of the ground capacitor-side conductor pillar is also Similarly, the pitch of the surface connection terminals is restricted. However, if there is such a restriction, it is difficult to obtain an arbitrary capacitance-inductance characteristic, and it may not be possible to impart desired performance to the relay board.

  On the other hand, if at least a part of the plurality of short ground conductor pillars is electrically connected to the ground capacitor-side conductor pillar via the conductor pillar pitch conversion layer, the ground capacitor is basically formed. The degree of freedom when arranging the side conductor pillars increases. Therefore, it is easy to obtain an arbitrary capacitance-inductance characteristic, and it is easy to give a desired performance to the relay board. Further, according to this configuration, it is possible to thin out the capacitor-side conductor posts for ground, in other words, to reduce the density of the capacitor-side conductor posts for ground.

  In addition, a plurality of short conductor pillars for power supply and a conductor pole pitch conversion layer penetrating the first surface are formed inside the relay board main body, and at least a part of the plurality of short conductor pillars for power supply is formed. An electrical component may be electrically connected to the power-supply capacitor-side conductor post via the conductor post pitch conversion layer. Here, the conductor pole pitch conversion layer refers to a layered conductive portion interposed to convert the pitch of the power supply capacitor-side conductor pillars (center-to-center distance between adjacent power supply capacitor-side conductor pillars). . One or more conductive pillar pitch conversion layers are formed inside the relay board body. In addition, the short conductor pillar for power supply means a conductor pillar that does not reach the second surface because the length is shorter than the conductor pillar on the power supply relay substrate main body side allocated for power supply. . Therefore, the short conductor pillar for power supply penetrates only the first surface. The inner end of at least a part of the plurality of short conductor pillars for power supply is connected to the conductor pole pitch conversion layer.

  Usually, the pitch of the power supply relay board main body side conductor pillars (that is, the center-to-center distance between adjacent power supply relay board main body side conductor pillars) is the pitch of the surface connection terminals of the semiconductor element (the center-to-center distance of adjacent surface connection terminals). ). Therefore, if an attempt is made to electrically connect the power supply relay board main body-side conductor pillar and the power supply capacitor-side conductor pillar without using this kind of conductor pillar pitch conversion layer, the pitch of the power supply capacitor-side conductor pillar is also Similarly, the pitch of the surface connection terminals is restricted. However, if there is such a restriction, it is difficult to obtain an arbitrary capacitance-inductance characteristic, and it may not be possible to impart desired performance to the relay board.

  On the other hand, if at least a part of the plurality of short conductor pillars for power supply is electrically connected to the conductor pillar on the capacitor side for power supply through the conductor pole pitch conversion layer, the capacitor for power supply is basically provided. The degree of freedom when arranging the side conductor pillars increases. Therefore, it is easy to obtain an arbitrary capacitance-inductance characteristic, and it is easy to give a desired performance to the relay board. Further, according to this configuration, it is possible to thin out the power supply capacitor-side conductor posts, in other words, to reduce the density of the power supply capacitor-side conductor posts.

  Further, the relay board main body and the capacitor may be integrally formed, and the relay board main body-side conductor pillar and the capacitor-side conductor pillar may be directly connected without the interposition of a protruding electrode. When such an integrated configuration is adopted, the projection electrodes for electrically connecting the relay board main body and the capacitor can be omitted, so that the configuration is simplified. Further, by directly connecting the relay board main body-side conductor pillar and the capacitor-side conductor pillar, it is possible to reduce the resistance of the relay board. The relay board having the integrated relay board body and the capacitor can be manufactured, for example, by laminating ceramic unsintered materials and firing them simultaneously.

  Alternatively, the relay board main body and the capacitor may be separate components, and the relay board main body-side conductor pillar and the capacitor-side conductor pillar may be connected via a protruding electrode. When such a separate structure is employed, the range of selection of materials for forming the relay substrate main body and the capacitor and the range of selection of the method of manufacturing the relay substrate are increased.

[First Embodiment]

  Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing a semiconductor package (structure) 11 of the present embodiment including an IC chip (semiconductor element) 21, a capacitor 31, and a wiring board (substrate) 41. FIG. 2 is a schematic sectional view showing a capacitor 31 constituting the semiconductor package 11. FIG. 3 is a schematic sectional view showing a capacitor with an IC chip (capacitor with a semiconductor element) 61 constituting the semiconductor package 11. FIG. 4 is a schematic cross-sectional view showing a state when the capacitor 61 with an IC chip is mounted on the wiring board 41.

  As shown in FIG. 1 and the like, the semiconductor package 11 of the present embodiment is an LGA (land grid array) including the IC chip 21, the capacitor 31, and the wiring board 41, as described above. The form of the semiconductor package 11 is not limited to the LGA alone, and may be, for example, a BGA (ball grid array), a PGA (pin grid array), or the like. The IC chip 21 having a function as the MPU is a rectangular flat plate of 10 mm square and made of silicon having a thermal expansion coefficient of about 3.0 ppm / ° C. A circuit element (not shown) is formed on the upper surface layer of the IC chip 21. On the other hand, on the lower surface side of the IC chip 21, a plurality of bump-shaped surface connection terminals 22 are provided in a lattice shape.

  The wiring board 41 is a so-called multilayer wiring board, which is formed of a rectangular plate-like member having an upper surface 42 and a lower surface 43 and has a plurality of resin insulating layers 44 and a plurality of conductor circuits 45. In the case of the present embodiment, specifically, the resin insulating layer 44 is formed of an insulating base material obtained by impregnating a glass cloth with an epoxy resin, and the conductive circuit 45 is formed of a copper foil or a copper plating layer. The thermal expansion coefficient of the wiring board 41 is 13.0 ppm / ° C. or more and less than 16.0 ppm / ° C. On the upper surface 42 of the wiring board 41, a plurality of surface connection pads 46 for electrical connection with the capacitor 31 side are formed in a lattice shape. On the lower surface 43 of the wiring board 41, a plurality of surface connection pads 47 for electrical connection with a motherboard (not shown) are formed in a lattice shape. The surface connection pads 47 for connecting the motherboard have a wider pitch than the surface connection pads 46 for connecting the capacitor. Via-hole conductors 48 are provided in the resin insulation layer 44, and via these via-hole conductors 48, conductor circuits 45, surface connection pads 46, and surface connection pads 47 of different layers are electrically connected to each other. . A semiconductor element and other electronic components (both not shown) are mounted on the upper surface 42 of the wiring board 41 in addition to the capacitor 61 with an IC chip shown in FIG.

  As shown in FIGS. 1 and 2, the capacitor 31 is a so-called via array type capacitor, and has a rectangular flat plate-shaped capacitor body having an upper surface 32 (first surface) and a lower surface 33 (second surface). 38. The capacitor body 38 is made of an aluminum nitride substrate having a laminated structure. That is, the capacitor 31 is a multilayer ceramic capacitor. Such an aluminum nitride substrate has a thermal expansion coefficient of about 4.4 ppm / ° C. and a Young's modulus of about 350 GPa. Therefore, the coefficient of thermal expansion of the capacitor body 38 is smaller than the coefficient of thermal expansion of the wiring board 41 and larger than the coefficient of thermal expansion of the IC chip 21. That is, it can be said that the capacitor 31 of the present embodiment has a lower thermal expansion property than the wiring board 41 and has a thermal expansion property closer to that of the IC chip 21. Since the Young's modulus of the aluminum nitride substrate is higher than that of the IC chip 21, the capacitor 31 of the present embodiment has high rigidity.

  A plurality of vias (through holes) penetrating the upper surface 32 and the lower surface 33 are formed in a lattice shape in a capacitor body 38 constituting the capacitor 31. These vias correspond to the positions of the surface connection pads 46 of the wiring board 41. A plurality of conductor pillars 35 made of W (tungsten), which is a kind of high melting point metal, are provided in the via. An upper end surface side bump 36 having a substantially hemispherical shape is provided on the upper end surface of each conductor post 35. These upper end surface side bumps 36 protrude from the upper surface 32 and are connected to the surface connection terminals 22 on the IC chip 21 side. A substantially hemispherical lower end surface side bump 37 is provided on the lower end surface of each conductor post 35. These lower end surface side bumps 37 protrude from the lower surface 33 and are connected to the surface connection pads 46 on the wiring board 41 side.

  Further, in the aluminum nitride substrate constituting the capacitor body 38, the inner electrode 34 is formed in a layered manner via an aluminum nitride layer which is a dielectric layer. More specifically, the conductor pillar 35 is divided into three groups, a first conductor pillar, a second conductor pillar, and a third conductor pillar, and the inner layer electrode 34 is called a first inner layer electrode and a second inner layer electrode. Divided into two groups. The first inner layer electrode and the second inner layer electrode are alternately laminated at a predetermined interval, the first inner layer electrode is connected to the first conductor column, and the second inner layer electrode is connected to the second conductor column. . The third conductor pillar is not connected to any of the inner layer electrodes.

  Therefore, in the semiconductor package 11 having such a structure, the wiring board 41 side and the IC chip 21 side are electrically connected via the conductor pillar 35 of the capacitor 31. Therefore, signals are input and output between the wiring board 41 and the IC chip 21 via the capacitor 31 which also functions as a relay board, and power is supplied to operate the IC chip 21 as an MPU. In this case, the signal is input / output via a third conductor column, and the power is supplied via a first conductor column and a second conductor column. In addition, since the semiconductor package 11 is provided with the capacitor 31, noise superimposed on the power supply potential and the ground potential is reliably removed. Although only one capacitor 31 is provided in the semiconductor package 11 of the present embodiment, the present invention is not limited to this, and a plurality of capacitors 31 may be provided.

  Here, a procedure for manufacturing the semiconductor package 11 having the above structure will be described.

  First, a plurality of aluminum nitride green sheets having vias formed in a lattice at corresponding positions are produced by a well-known ceramic green sheet forming technique. Then, a via penetrating both the front and back surfaces is formed at a predetermined position in each green sheet by punching or the like. Further, a W paste is filled in the via of each green sheet, and a paste filling layer that will later become the conductor pillar 35 is formed. Further, a W paste is printed on one side surface of each green sheet, and a paste print layer having a predetermined pattern to be an inner layer electrode 34 is formed in advance. After laminating and pressing these green sheets, firing (simultaneous firing) is performed at a predetermined temperature in a reducing atmosphere to sinter the aluminum nitride and the W paste. As a result, a capacitor body 38 having the conductor pillar 35 and the inner layer electrode 34 is manufactured. Further, a solder paste is printed and formed on both end surfaces of the conductor pillar 35 of the capacitor body 38. Reflow is performed in this state to melt the solder paste. Then, the solder paste swells in a substantially hemispherical shape, thereby forming the upper end side bumps 36 and the lower end side bumps 37. As a result, the capacitor 31 shown in FIG. 2 is completed.

  Next, the IC chip 21 is mounted on the upper surface 32 of the completed capacitor 31. At this time, the surface connection terminals 22 on the IC chip 21 side and the upper end side bumps 36 on the capacitor 31 side are aligned. Then, by heating and reflowing the upper end side bumps 36, the upper end side bumps 36 and the surface connection terminals 22 are joined. As a result, the capacitor 61 with an IC chip shown in FIG. 3 is completed.

  Next, the lower end surface side bump 37 on the capacitor 31 side and the surface connection pad 46 on the wiring board 41 are aligned (see FIG. 4), and the capacitor 61 with an IC chip is mounted on the wiring board 41. . Then, by heating and reflowing each lower end surface side bump 37, the lower end surface side bump 37 and the surface connection pad 46 are joined. As a result, the semiconductor package 11 shown in FIG. 1 is completed.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the case of the semiconductor package 11 (structure) of the present embodiment, the capacitor 31 itself has a function as a so-called relay board, and is arranged at a position where the relay board should be. That is, as compared with the conventional structure, the IC chip 21 and the capacitor 31 are arranged closer to each other, and the two are directly connected. Therefore, it is possible to almost completely eliminate wiring (capacitor connection wiring) connecting the IC chip 21 and the capacitor 31. Therefore, noise that enters between the IC chip 21 and the capacitor 31 can be extremely reduced, and high reliability can be obtained without causing malfunction such as malfunction.

  (2) Even if a failure occurs in the capacitor 31, since the capacitor 31 is not embedded in the wiring board 41, it is sufficient to discard only the capacitor 31, which entails discarding the entire wiring board 41. Absent. Therefore, compared to the conventional structure in which the capacitor 31 is embedded on the wiring board 41 side, the loss can be reduced and the manufacturing can be performed at low cost. In addition, since the structure is not such that the capacitor 31 is buried on the wiring board 41 side, there is no restriction on the space, and the size (capacity) of the capacitor 31 can be relatively easily increased. 41 also becomes easy to manufacture. Further, if the size of the capacitor 31 is increased, the resistance and the inductance are reduced, so that the noise elimination ability can be improved.

  (3) In this semiconductor package 11, the difference in thermal expansion coefficient from the IC chip 21 is reduced by using the substantially plate-shaped capacitor body 38 having a thermal expansion coefficient of less than 5.0 ppm / ° C. No large thermal stress acts directly on the surface. Therefore, even if the IC chip 21 is large and generates a large amount of heat, cracks and the like hardly occur. Therefore, high reliability can be given to the chip bonding portion and the like in the semiconductor package 11.

In this embodiment, the following modified examples are also conceivable.
(Modification 1)
As shown in FIG. 5, first, the capacitor 31 is joined to the upper surface 42 of the wiring board 41 by soldering or the like, whereby a wiring board with a capacitor 71 (a board with a capacitor) is prepared in advance. After that, the IC chip 21 is bonded to the upper surface 32 of the wiring board 71 with the capacitor to obtain a desired semiconductor package 11.

[Second embodiment]
Hereinafter, a second embodiment of the present invention will be described in detail with reference to FIGS. FIG. 6 is a schematic cross-sectional view illustrating a semiconductor package (structure) 131 of the present embodiment including an IC chip (semiconductor element) 21, an interposer 91 with a built-in capacitor, and a wiring board (substrate) 41. FIG. 7 is a schematic sectional view showing the interposer 91 with a built-in capacitor constituting the semiconductor package 131. FIG. 8 is a schematic sectional view showing an interposer (capacitor with a semiconductor element) 111 with a built-in capacitor with an IC chip constituting the semiconductor package 131. FIG. 9 is a schematic cross-sectional view showing a state when the interposer 111 with a built-in capacitor with an IC chip is mounted on the wiring board 41.

  As shown in FIG. 6 and the like, the semiconductor package 131 of the present embodiment is an LGA (land grid array) including the IC chip 21, the interposer 91 with a built-in capacitor, and the wiring board 41, as described above. Note that the form of the semiconductor package 131 is not limited to LGA alone, and may be, for example, BGA (ball grid array), PGA (pin grid array), or the like. Since the same IC chip 21 and wiring board 41 as those in the first embodiment are used, a detailed description thereof will be omitted.

  As shown in FIGS. 6, 7 and the like, the interposer 91 (relay board) with a built-in capacitor of the present embodiment has a rectangular flat plate-shaped interposer body 98 having an upper surface 92 (first surface) and a lower surface 93 (second surface). (Relay board main body). The interposer body 98 is made of an aluminum nitride substrate having a laminated structure. Such an aluminum nitride substrate has a thermal expansion coefficient of about 4.4 ppm / ° C. and a Young's modulus of about 350 GPa. Therefore, the thermal expansion coefficient of the interposer body 98 is smaller than the thermal expansion coefficient of the wiring board 41 and larger than the thermal expansion coefficient of the IC chip 21. That is, it can be said that the interposer 91 with a built-in capacitor of the present embodiment has a lower thermal expansion than the wiring board 41, and has a thermal expansion closer to that of the IC chip 21. Since the Young's modulus of the aluminum nitride substrate is higher than that of the IC chip 21, the interposer 91 with a built-in capacitor of the present embodiment has high rigidity.

  In the interposer main body 98, a substantially rectangular recess 99 in a plan view is formed so as to open at the lower surface 93. A substantially rectangular capacitor 101 is also arranged in the recess 99 in plan view. The capacitor 101 is fixed in the recess 99 by an adhesive layer 108 made of resin. However, a form without the adhesive layer 108 is also possible.

  A plurality of vias penetrating the upper surface 92 and the lower surface 93 and a plurality of vias 96 penetrating the upper surface 92 and the bottom surface of the concave portion 99 are formed in the interposer main body 98 constituting the interposer 91 with a built-in capacitor in a lattice shape. These vias 96 correspond to the positions of the surface connection pads 46 of the wiring board 41. In the via 96, a relay substrate main body-side conductor pillar 95 made of a pillar-shaped Pb-Sn-based solder is provided. An upper end surface side bump 97 having a substantially hemispherical shape is provided on the upper end surface of each relay substrate body side conductor pillar 95. These upper end surface side bumps 97 protrude from the upper surface 92 and are connected to the surface connection terminals 22 on the IC chip 21 side. On the lower end surface of each relay substrate body side conductor post 95, lower end side bumps 94, 100 having a substantially hemispherical shape are provided. The lower end surface side bump 100 protrudes from the lower surface 93 of the interposer body 98 and is connected to the surface connection pad 46 on the wiring board 41 side. On the other hand, the lower end surface side bump 94 protrudes from the bottom surface of the concave portion 99 and is connected to the upper end surface of the capacitor side conductor pillar 105 on the capacitor 101 side.

  As shown in FIGS. 6 and 7 and the like, the capacitor 101 of the present embodiment is also a via array type capacitor and has a rectangular flat plate-shaped capacitor main body 104 having an upper surface 102 and a lower surface 103. The capacitor body 104 is formed of a barium titanate substrate having a laminated structure. That is, the capacitor 101 is a multilayer ceramic capacitor having a high dielectric body as the capacitor body 104. Although only one capacitor 101 is provided in the semiconductor package 131 of the present embodiment, the present invention is not limited to this, and a plurality of capacitors 101 may be provided.

  A plurality of vias penetrating the upper surface 102 and the lower surface 103 are formed in a lattice shape in a capacitor main body 104 constituting the capacitor 101. In the via, a plurality of capacitor-side conductor pillars 105 made of Pb-Sn are provided. A substantially hemispherical lower end side bump 107 is provided on the lower end surface of each capacitor side conductor pillar 105. These lower end surface side bumps 107 project to the same extent as the lower end surface side bumps 100 and are connected to the surface connection pads 46 on the wiring board 41 side.

  Further, in the barium titanate substrate constituting the capacitor main body 104, an inner layer electrode 106 is formed in a layered manner via a barium titanate layer which is a dielectric layer. More specifically, the capacitor-side conductor pillars 105 are divided into two groups, a first capacitor-side conductor pillar and a second capacitor-side conductor pillar, and the inner layer electrodes 106 are referred to as a first inner layer electrode and a second inner layer electrode. Divided into two groups. The first inner layer electrode and the second inner layer electrode are alternately laminated at a predetermined interval, and the first inner layer electrode is connected to the first capacitor side conductor post, and the second inner layer electrode is connected to the second capacitor side conductor post. It is connected.

  Therefore, in the semiconductor package 131 having such a structure, the wiring board 41 side and the IC chip 21 side are electrically connected via the conductor pillars 95 and 105 of the interposer 91 with a built-in capacitor. Therefore, signals are input and output between the wiring board 41 and the IC chip 21 through the interposer 91 with a built-in capacitor, and power is supplied to operate the IC chip 21 as an MPU. In this case, the signal flows through the conductor board 95 on the relay substrate main body penetrating the upper surface 92 and the lower surface 93 of the interposer main body 98, so that the signal is directly input to and output from the IC chip 21 without flowing through the capacitor 101. On the other hand, power is supplied via the interposer body 98 and the capacitor 101. That is, the power flows through the capacitor-side conductor pillar 105 in the capacitor 101 and also flows through the relay-substrate-body-side conductor pillar 95 that passes through the upper surface 92 of the interposer body 98 and the bottom surface of the recess 99. Since the semiconductor package 131 is provided with the capacitor 101, noise superimposed on the power supply potential and the ground potential is reliably removed.

  Here, a procedure for manufacturing the semiconductor package 131 having the above structure will be described.

  First, the capacitor 101 having the structure shown in FIG. 7 is manufactured in advance according to the ceramic co-firing method described in the first embodiment. However, since barium titanate is used as the ceramic material, conditions suitable for the firing temperature and the like are set. At the same time, the interposer body 98 is manufactured in the following manner.

  That is, a plurality of aluminum nitride green sheets having vias 96 (through holes) formed in a lattice pattern at corresponding positions are produced by a well-known ceramic green sheet forming technique. For a part of the green sheet, a rectangular opening is provided by punching or the like. Such openings will later become recesses 99. Then, the green sheets are stacked and pressed. Furthermore, after a tungsten paste is applied to the inner peripheral surface of the via 96, the green sheet laminate is fired in a reducing atmosphere to produce an interposer body 98 made of an aluminum nitride sintered body. In the interposer body 98, a base metal layer (not shown) mainly containing tungsten is formed on the inner peripheral surface of the via 96. Further, after electroless nickel-gold plating is performed on the underlying metal layer, a 0.9 mm diameter high melting point solder ball made of 90% Pb-10% Sn is placed on the upper end opening of each via 96. This is heated and melted. As a result, the molten high melting point solder moves downward by gravity and is injected into the via 96, and is welded to the metal layer on the inner peripheral surface of the via 96, thereby forming the relay substrate main body-side conductor pillar 95. Further, the upper end surface and the lower end surface of the relay substrate main body side conductor pillar 95 are raised substantially in a hemispherical shape by the action of surface tension, and become the upper end surface side bump 97 and the lower end surface side bumps 94 and 100. As a result, the interposer body 98 having the recess 99 is completed.

  An uncured thermosetting adhesive is applied to the recess 99 of the interposer body 98 thus manufactured, and in this state, the capacitor 101 is disposed in the recess 99 and heated to a predetermined temperature. As a result, the relay substrate main body-side conductor pillars 95 and the capacitor-side conductor pillars 105 are joined via the lower end face side bumps 94 that have been reflowed by heat. Further, by curing the thermosetting adhesive, the capacitor 101 is securely adhered and held in the recess 99. As a result, the interposer 91 with a built-in capacitor shown in FIG. 7 is completed.

  Next, the IC chip 21 is mounted on the upper surface 92 of the completed interposer 91 with a built-in capacitor. At this time, the surface connection terminal 22 on the IC chip 21 side and the upper end surface side bump 97 on the capacitor built-in interposer 91 side are aligned. Then, by heating and reflowing each upper end surface side bump 97, the upper end surface side bump 97 and the surface connection terminal 22 are joined. As a result, the interposer 111 with a built-in capacitor having an IC chip shown in FIG. 8 is completed.

  Next, the lower end side bumps 100 and 107 on the side of the interposer 111 with a built-in capacitor with an IC chip are aligned with the surface connection pads 46 on the side of the wiring board 41 (see FIG. 9). The interposer 111 with a built-in capacitor is mounted. Then, by heating and reflowing the lower end side bumps 100 and 107, the lower end side bumps 100 and 107 and the surface connection pads 46 are joined. As a result, the semiconductor package 131 shown in FIG. 6 is completed.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the case of the semiconductor package 131 (structure) of the present embodiment, the IC chip 21 and the capacitor 101 are closer to each other than in the conventional structure because the capacitor 101 is disposed in the recess 99 of the interposer 91. As a result, the wiring (capacitor connection wiring) connecting the IC chip 21 and the capacitor 101 can be made very short. Therefore, noise that enters between the IC chip 21 and the capacitor 101 can be extremely reduced, and high reliability can be obtained without causing malfunction such as malfunction.

  (2) Even if a failure occurs in the capacitor 101, the capacitor 101 is not embedded in the wiring board 41, so it is sufficient to discard only the interposer 91 with a built-in capacitor, and the entire wiring board 41 is discarded. Is not accompanied. Therefore, compared to the conventional structure in which the capacitor 101 is buried on the wiring board 41 side, the loss can be reduced and the device can be manufactured at low cost. In addition, since the capacitor 101 is not buried in the wiring board 41, the space is not restricted, and the size (capacity) of the capacitor 101 can be relatively easily increased. 41 also becomes easy to manufacture. In addition, if the size of the capacitor 101 is increased, the resistance and the inductance are reduced, so that the noise removing capability can be improved.

  (3) In this semiconductor package 131, the difference in thermal expansion coefficient from the IC chip 21 is reduced by using the substantially plate-shaped interposer body 98 having a thermal expansion coefficient of less than 5.0 ppm / ° C. No large thermal stress acts directly on the surface. Therefore, even if the IC chip 21 is large and generates a large amount of heat, cracks and the like hardly occur. Therefore, high reliability can be imparted to the chip bonding portion and the like in the semiconductor package 131.

In the present embodiment, the following modifications are conceivable.
(Modification 2-1)
That is, as shown in FIG. 10, first, the interposer 91 with a built-in capacitor is joined to the upper surface 42 of the wiring board 41 by soldering or the like, whereby a wiring board 121 with a built-in interposer (a board with a relay board) is prepared in advance. . After that, the IC chip 21 is bonded to the upper surface 92 of the interposer 91 with a built-in capacitor to obtain a desired semiconductor package 131.

(Modification 2-2)
The interposer 91 (relay board) with a built-in capacitor shown in FIG. 6 and the like has a structure in which an interposer main body 98 and a capacitor 101 are formed separately and connected via an adhesive layer 108 and a lower end side bump 94. Was. On the other hand, in the interposer 141 with a built-in capacitor according to the modified example shown in FIGS. 11 and 12, the interposer body 98 and the capacitor 101 are integrally formed. That is, the interposer body 98 and the capacitor 101 are directly connected without interposing the adhesive layer 108 and the lower end surface side bump 94. In this case, since the lower end side bump 94 for electrically connecting the interposer main body 98 and the capacitor 101 can be omitted, the configuration can be simplified. In addition, by directly connecting the relay substrate main body-side conductor pillars 95 and the capacitor-side conductor pillars 105, the resistance of the interposer 141 with a built-in capacitor can be reduced.

  Next, a method of manufacturing the interposer 141 with a built-in capacitor will be described. First, a plurality of alumina green sheets (ceramic unsintered bodies) in which vias 96 (through-holes, holes for forming the first conductor pillars) are provided at corresponding positions in a lattice pattern by a well-known ceramic green sheet forming technique. Make it. For some of these green sheets, a rectangular opening is provided by punching or the like. Such openings will later become recesses 99. These green sheets become the interposer body 98 after sintering. Note that paste (conductive material) such as nickel is filled in advance in each through hole of these green sheets by, for example, printing. The nickel paste in each through hole will later become the relay substrate main body-side conductor pillar 95 or the capacitor-side conductor pillar 105.

  A predetermined number of the green sheets filled with the conductive material are laminated. Next, when laminating and pressing each green sheet having a rectangular opening on the laminate, each time one green sheet is laminated and pressed, a pattern of, for example, a ceramic paste is screen-printed in the opening. Form. The thickness of the ceramic printed layer after drying is substantially the same as the thickness of the green sheet laminated immediately before. The ceramic material to be screen printed later becomes a ceramic dielectric layer. Therefore, a ceramic material that has a higher dielectric constant than alumina after sintering should be selected. In the present embodiment, a slurry that becomes barium titanate after sintering is used as the ceramic material. It is desirable that the ceramic material be capable of being fired simultaneously with the green sheet. Next, a nickel paste layer is formed on the surface of the ceramic material layer already printed by printing a nickel paste (conductive material). At this time, the nickel paste printed on the hole-shaped portion where the ceramic layer is not formed later becomes the conductor pillar 105 of the capacitor portion. The nickel paste layer on the surface of the printed ceramic material layer will later become the inner layer electrode 106.

  Then, after laminating and pressing each green sheet provided with a rectangular opening, repeating printing of a ceramic paste, and printing of a nickel paste to form a laminate, the laminate is fired in an oxidizing atmosphere. That is, a green sheet (ceramic unsintered body), an unsintered ceramic material layer, and an unsintered nickel paste are collectively heated and sintered at the same time.

  According to this manufacturing method, the interposer 141 with a built-in capacitor shown in FIGS. 11 and 12 can be reliably obtained.

[Third Embodiment]
Hereinafter, a third embodiment of the present invention will be described in detail with reference to FIG. FIG. 13 is a schematic cross-sectional view showing a semiconductor package (structure) 181 of the present embodiment including an IC chip (semiconductor element) 21, an interposer 91 with a built-in capacitor, and a wiring board (substrate) 41.

  The interposer 91 with a built-in capacitor of the present embodiment includes a plurality of relay board body side conductor posts 182 for ground and a plurality of conductor board side conductor pillars 183 for power supply inside the interposer body 98. These two types of relay board main body-side conductor pillars 182, 183 are both arranged in the recess forming area of the relay board main body 98. Similarly, a plurality of short conductor pillars 188 for ground and a plurality of short conductor pillars 189 for power supply are arranged in the recess forming region. On the other hand, the plurality of relay board main body-side conductor posts 184 for signal lines are arranged outside the recess forming region (outer peripheral portion of the recess 99) in the relay board body 98, and the two types of relay board main body-side conductor pillars 182, 182 are provided. 183. The pitch between the conductor pillars 182 and 183 on the relay substrate main body side is equal to the pitch between the surface connection terminals 22 of the IC chip 21 and is set to about 100 μm to 250 μm in the present embodiment.

  In the case of the interposer 91 with a built-in capacitor of the present embodiment, the capacitor 101 includes a plurality of capacitor-side conductor posts 192 for ground and a plurality of capacitor-side conductor posts 193 in the capacitor 101. The pitch of these two types of capacitor-side conductor pillars 192, 193 is several times larger than the pitch of the surface connection terminals 22 of the IC chip 21, and is set to about 200 μm to 600 μm in the present embodiment. That is, the capacitor-side conductor columns 192 and 193 have a relatively low density, and are in a state of being thinned out.

  Inside the interposer body 98, a conductor pillar pitch conversion layer 185 formed by printing and firing a tungsten paste is formed. Although the lower ends of the plurality of short conductor pillars 188 are connected to the conductor pole pitch conversion layer 185, they do not reach the bottom of the recess 99. In addition, the plurality of conductor posts 182 on the relay board main body side for ground are not only connected to the conductor post pitch conversion layer 185 but also penetrate through the conductor post pitch conversion layer 185 and the lower ends reach the bottom surface of the recess 99. ing. Further, the lower end of the ground relay substrate main body side conductive column 182 penetrating the conductive column pitch conversion layer 185 is connected to the ground capacitor side conductive column 192 via the lower end surface side bump 94. As a result, the plurality of relay board body side conductor posts 182 for ground, the plurality of short conductor posts 188 for ground, and the conductor posts 192 for ground capacitor are electrically connected to each other via the conductor pole pitch conversion layer 185. ing.

  Further, inside the interposer body 98, another conductor pillar pitch conversion layer 186 is formed. The conductor pole pitch conversion layer 186 is also formed by printing and firing a tungsten paste. Note that the two conductor pillar pitch conversion layers 185 and 186 are arranged at different depth positions. The short ends of the plurality of power supply short conductor columns 189 are connected to the conductor column pitch conversion layer 186, but do not reach the bottom surface of the recess 99. Further, the plurality of power supply relay board main body side conductor pillars 183 are not only connected to the conductor pillar pitch conversion layer 186 but also penetrate the conductor pillar pitch conversion layer 186 so that the lower ends thereof reach the bottom surface of the recess 99. ing. The lower end of the power supply relay substrate main body-side conductor post 183 penetrating the conductor post pitch conversion layer 186 is connected to the power supply capacitor-side conductor post 193 via the lower end surface side bump 94. As a result, the plurality of power supply relay board main body side conductor pillars 183, the plurality of power supply short conductor pillars 189, and the power supply capacitor side conductor pillars 193 are electrically connected to each other via the conductor pillar pitch conversion layer 186. ing.

  In the case of the present embodiment having the above configuration, the degree of freedom when arranging the ground-side capacitor-side conductor pillars 192 and the power-side capacitor-side conductor pillars 193 basically increases. Therefore, it is easy to obtain an arbitrary capacitance-inductance characteristic, and it is easy to provide desired performance to the interposer 91 with a built-in capacitor. Further, according to this configuration, it is possible to thin out the capacitor-side conductor posts 192 for the ground and the capacitor-side conductor posts 193 for the power supply.

  The embodiments of the present invention may be modified as follows without departing from the spirit of the invention. For example, in the second embodiment, the example in which the concave portion 99 is provided at one position substantially at the center of the interposer main body 98 has been described, but the concave portion 99 is not necessarily formed at the substantially center. Further, the concave portions 99 may be provided at a plurality of positions as necessary, and the capacitors 101 may be arranged in the respective concave portions 99 (see FIG. 14). Although not shown, a plurality of capacitors 101 may be arranged in one recess 99. In this case, the capacitors 101 may be stacked and arranged in the thickness direction of the interposer 91, or the capacitors 101 may be arranged and arranged in the surface direction of the interposer 91.

  Next, technical ideas grasped by the above-described embodiment will be listed below.

  (1) having a first surface and a second surface on which a semiconductor element having a thermal expansion coefficient of not less than 2.0 ppm / ° C. and less than 5.0 ppm / ° C. and having a surface connection terminal is to be mounted; Is less than 5.0 ppm / ° C., and a plurality of conductor columns that penetrate the first surface and the second surface and are to be electrically connected to the surface connection terminals. A capacitor characterized by:

  (2) The capacitor according to the technical concept (1), wherein the capacitor body is made of an insulating material.

  (3) The capacitor according to the technical concept (1), wherein the capacitor body is made of a material having a lower thermal expansion coefficient than the substrate.

  (4) The capacitor according to the technical idea (1), wherein the capacitor body is made of a material having higher rigidity than at least silicon.

  (5) The capacitor according to the technical idea (1), wherein the capacitor body is made of a material having a low coefficient of thermal expansion and high rigidity.

  (6) The capacitor according to the technical idea (1), wherein the capacitor body is made of a material having a Young's modulus of 200 GPa or more.

  (7) The capacitor according to the technical concept (1), wherein the capacitor body is made of an insulating ceramic material having a Young's modulus of 200 GPa or more.

  (8) The capacitor according to the technical concept (1), wherein the capacitor body is made of a nitride-based engineering ceramic.

  (9) The capacitor according to the technical concept (1), wherein the capacitor body is formed using aluminum nitride, silicon nitride, or a mixed ceramic material of aluminum nitride and silicon nitride.

  (10) The capacitor according to the technical idea (1), wherein at least one side of the semiconductor element is 10 mm or more.

  (11) A first surface on which a semiconductor element having a surface connection terminal to be mounted having a thermal expansion coefficient of 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C. and a concave portion are formed, and the thermal expansion coefficient is 5 A substantially plate-shaped relay board main body having a second surface of less than 0.0 ppm / ° C., and a plurality of relay boards that penetrate the first surface and the bottom surface of the concave portion and are to be electrically connected to the surface connection terminal. A main body-side conductor pillar, a plurality of capacitor-side conductor pillars having a front surface and a back surface, penetrating the front surface and the back surface, and being electrically connected to the relay substrate body-side conductor pillar, and arranged in the recess; A relay board comprising: a capacitor;

  (12) The relay board according to the technical idea (11), wherein the relay board body is made of an insulating material.

  (13) The relay board according to the technical idea (11), wherein the relay board main body is made of a material having a lower thermal expansion coefficient than the substrate.

  (14) The relay board according to the technical concept (11), wherein the relay board body is made of a material having higher rigidity than at least silicon.

  (15) The relay board according to the technical idea (11), wherein the relay board body is made of a material having a low coefficient of thermal expansion and high rigidity.

  (16) The relay board according to the technical concept (11), wherein the relay board body is made of a material having a Young's modulus of 200 GPa or more.

  (17) The relay board according to the technical concept (11), wherein the relay board body is made of an insulating ceramic material having a Young's modulus of 200 GPa or more.

  (18) The relay board according to the technical concept (11), wherein the relay board body is made of a nitride engineering ceramic.

  (19) The relay substrate according to the technical concept (11), wherein the relay substrate body is formed using aluminum nitride, silicon nitride, or a mixed ceramic material of aluminum nitride and silicon nitride.

  (20) The relay board according to the technical idea (11), wherein at least one side of the semiconductor element is 10 mm or more.

  (21) The technical idea characterized in that the relay substrate main body and the capacitor are integrally formed, and the relay substrate main body-side conductor pillar and the capacitor-side conductor pillar are directly connected without the interposition of a projecting electrode. The relay board according to 11).

  (22) a substantially plate-shaped relay board body having a first surface on which a semiconductor element having a surface connection terminal is mounted, and a substantially plate-shaped relay substrate body having a second surface; and the surface connection penetrating the first surface and the second surface. A plurality of relay substrate body-side conductor pillars connected to the terminals, and a plurality of capacitor-side conductor pillars having a front surface and a back surface, penetrating the front surface and the back surface, and being connected to the relay substrate body-side conductor pillars. A method of manufacturing a relay substrate including a capacitor arranged in a concave portion formed on the second surface side, wherein a step of producing a ceramic green body having the concave portion and a first conductor column forming hole; A step of filling a conductive material in the first conductor column forming hole to form a non-sintered relay substrate main body-side conductor column, and filling a ceramic material in the concave portion of the ceramic unsintered body; An unsintered ceramic material that will later become the relay board body Forming a body layer, forming a second conductor pillar forming hole in the unsintered ceramic dielectric layer, filling the second conductor pillar forming hole with a conductive material, A step of forming a capacitor-side conductor pillar, and the unsintered ceramic green body, the unsintered ceramic dielectric layer, the unsintered relay substrate body-side conductor pillar, and the unsintered capacitor side A method of heating the conductor pillars at a time and simultaneously sintering them at the same time.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor package (structure) according to a first embodiment including an IC chip (semiconductor element), a capacitor, and a wiring board (substrate). FIG. 2 is a schematic cross-sectional view showing a capacitor constituting the semiconductor package. FIG. 2 is a schematic cross-sectional view illustrating a capacitor with an IC chip (a capacitor with a semiconductor element) that constitutes a semiconductor package. FIG. 2 is a schematic cross-sectional view showing a state when a capacitor with an IC chip is mounted on a wiring board. FIG. 6 is a schematic cross-sectional view showing a state in which an IC chip is mounted on a wiring board with capacitors (substrate with capacitors) in a modification of the first embodiment. FIG. 1 is a schematic sectional view showing a semiconductor package (structure) according to an embodiment including an IC chip (semiconductor element), an interposer with a built-in capacitor (relay substrate), and a wiring substrate (substrate). FIG. 2 is a schematic cross-sectional view showing an interposer with a built-in capacitor constituting a semiconductor package. FIG. 2 is a schematic cross-sectional view showing an interposer with a built-in capacitor with an IC chip (a relay board with a semiconductor element) constituting a semiconductor package. FIG. 4 is a schematic cross-sectional view showing a state when an interposer with a built-in capacitor with an IC chip is mounted on a wiring board. FIG. 13 is a schematic cross-sectional view showing a state in which an IC chip is mounted on a wiring board with a built-in capacitor interposer (a board with a relay board) in a modification of the second embodiment. FIG. 14 is a schematic cross-sectional view showing a semiconductor package (structure) according to another modified example of the second embodiment including an IC chip (semiconductor element), an interposer with a built-in capacitor (relay substrate), and a wiring substrate (substrate). FIG. 2 is a schematic cross-sectional view showing an interposer with a built-in capacitor constituting a semiconductor package. FIG. 13 is a schematic cross-sectional view showing a semiconductor package (structure) according to still another modified example of the second embodiment including an IC chip (semiconductor element), an interposer with a built-in capacitor (relay substrate), and a wiring substrate (substrate). FIG. 7 is a schematic cross-sectional view showing a semiconductor package (structure) according to another embodiment including an IC chip (semiconductor element), an interposer with a built-in capacitor (relay substrate), and a wiring substrate (substrate).

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 11 ... Semiconductor package as a structure which consists of a semiconductor element, a capacitor, and a board 21 ... IC chip as a semiconductor element 22 ... Surface connection terminals 31, 101 ... Capacitor 32 ... First surface (of the capacitor body) 33 ... (Capacitor body) ) Second surface 35 ... conductor pillar 38 ... capacitor body 41 ... wiring board as substrate 46 ... surface connection pad 61 ... capacitor with IC chip as capacitor with semiconductor element 71 ... wiring board with capacitor as substrate with capacitor 91 ... Interposer with built-in capacitor as relay board 92 ... First surface (of relay board main body) 93 ... Second surface (of relay board main body) 95 ... Conductor post on the relay board main body 98 ... Capacitor interposer main body as relay board main body 99 ... Recesses 102 ... Surface (of capacitor) 103 ... (Condensation) Back surface 105: capacitor-side conductor pillar 111: interposer with built-in capacitor with IC chip as relay board with semiconductor element 121: wiring board with interposer with built-in capacitor as substrate with relay board 131, 181: semiconductor element, relay board and board Semiconductor package 182 (for ground) relay substrate body-side conductor pillar 183 (for power supply) relay substrate body-side conductor pillar 185,186 ... conductor pillar pitch conversion layer 188 ... ground short conductor pillar 189 ... Short conductor pillar for power supply 192 ... Conductor side for capacitor side (for ground) 193 ... Conductor side for capacitor side (for power supply)

Claims (10)

A substantially plate-shaped capacitor body having a first surface and a second surface on which a semiconductor element having surface connection terminals is mounted;
A capacitor comprising: a plurality of conductor pillars penetrating the first surface and the second surface and connected to the surface connection terminal. A semiconductor element having a surface connection terminal; and
A substantially plate-shaped capacitor body having a first surface and a second surface on which the semiconductor element is mounted; and a plurality of conductor pillars penetrating the first surface and the second surface and connected to the surface connection terminals. A capacitor with a semiconductor element, comprising: a capacitor having: Comprising a substrate having surface connection pads, and
A substantially plate-shaped capacitor body having a first surface and a second surface mounted on the surface of the substrate; and a plurality of conductors penetrating the first surface and the second surface and connected to the surface connection pads. A substrate with a capacitor, comprising a capacitor having a pillar. A semiconductor element having a surface connection terminal,
Comprising a substrate having surface connection pads, and
A substantially plate-shaped capacitor body having a first surface on which the semiconductor element is mounted and a second surface mounted on the surface of the substrate; and the surface connection terminal penetrating the first surface and the second surface. A structure comprising a semiconductor element, a capacitor and a substrate, comprising: a capacitor having a plurality of conductor pillars connected to the surface connection pad. A substantially plate-shaped relay board main body having a first surface on which a semiconductor element having a surface connection terminal is mounted, and a second surface having a recess formed therein;
A plurality of relay substrate body-side conductor pillars that penetrate the first surface and the bottom surface of the concave portion and are connected to the surface connection terminals;
It has a front surface and a back surface, has a plurality of capacitor side conductor pillars penetrating the front surface and the back surface and connected to the relay substrate body side conductor pillar, and includes a capacitor arranged in the recess. Relay board.   Inside the relay substrate body, a plurality of ground short conductor pillars and conductor pillar pitch conversion layers penetrating the first surface are formed, and at least a part of the plurality of ground short conductor pillars is formed. 6. The relay board according to claim 5, wherein the relay board is electrically connected to the ground capacitor-side conductor pillar via the conductor pillar pitch conversion layer.   Inside the relay substrate body, a plurality of short conductor pillars for power supply and a conductor pole pitch conversion layer penetrating the first surface are formed, and at least a part of the plurality of short conductor pillars for power supply is formed. The relay board according to claim 5, wherein the relay board is electrically connected to the power supply capacitor-side conductor pillar via the conductor pillar pitch conversion layer. A semiconductor element having a surface connection terminal; and
A substantially plate-shaped relay board main body having a first surface on which the semiconductor element is mounted and a second surface on which a concave portion is formed, and penetrating the bottom surface of the first surface and the concave portion and connected to the surface connection terminal; A plurality of relay substrate body-side conductor pillars, and a plurality of capacitor-side conductor pillars having a front surface and a back surface, penetrating the front surface and the back surface, and being connected to the relay substrate body-side conductor pillar. A relay board with a semiconductor element, comprising: a relay board having a capacitor disposed in the relay board. Comprising a substrate having surface connection pads, and
A substantially plate-shaped relay substrate body having a first surface and a second surface formed with a recess and mounted on the surface of the substrate, and a plurality of relay substrate body conductors penetrating through the first surface and the bottom surface of the recess. And a plurality of capacitor-side conductor pillars having a pillar, a front surface and a back surface, penetrating the front surface and the back surface, and being connected to the relay substrate body-side conductor pillar and the surface connection pad, and arranged in the recess. A board with a relay board, comprising: a relay board having a capacitor. A semiconductor element having a surface connection terminal,
Comprising a substrate having surface connection pads, and
A substantially plate-shaped relay board body having a first surface on which the semiconductor element is mounted and a second surface formed with a concave portion and mounted on the surface of the substrate, and penetrating the bottom surface of the first surface and the concave portion. A plurality of relay substrate main body-side conductor pillars connected to the surface connection terminals, and a front surface and a back surface, penetrating the front surface and the back surface, and being connected to the relay substrate body-side conductor pillars and the surface connection pads A structure comprising a semiconductor element, a relay substrate, and a substrate, comprising: a relay substrate having a plurality of capacitor-side conductor pillars and having a capacitor disposed in the recess.

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