JP2004300570A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board hardly causing the dispersion and reaction between a barrier metal layer and a Cu plating layer or an Au plating layer thereafter, capable of remarkably reducing the connection failure due to the shortage of solder wetting at a metal terminal pad and the probability of the fault generation such as peeling/breaking by arranging between the Cu coating layer and the Au plating layer of the metal terminal pad the barrier metal layer capable of effectively suppressing the constituent dispersion between the Cu coating layer and the Au plating layer. <P>SOLUTION: In the metal terminal pads 10, 110, 17 and 117, the Cu plating layer 52, the barrier metal layer 20 and the Au plating layer 54 are arranged in this order from a first main surface CP on a wiring board 1. A Ni-B based electroless Ni plating layer or a platinum group metal based electroless plating layer is used as the barrier metal layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a wiring board.

JP-A-2002-4098 JP-A-6-330336 JP-A-2003-13248 "Evaluation of Pb-free solder balls produced by uniform droplet spray method" Hitachi Metals Technical Report Vol. 18 (2002) p. 43 "Development of Highly Reliable Sn-Ag Lead-Free Solder" R & D Review, Toyota Central R & D Laboratories, Vol. 35 No. 2 (2000) p. 39

  Among multi-layer wiring boards used for connecting chips such as ICs or LSIs, those called organic package boards include a wiring laminated portion in which dielectric layers and conductive layers made of a polymer material are alternately laminated. A plurality of metal terminal pads for flip-chip connection or motherboard connection (for example, by BGA or PGA) are arranged on the first main surface formed of the dielectric layer of the wiring laminated portion. These metal terminal pads are electrically connected via vias to an inner conductor layer located in the wiring laminated portion. The inner conductor layer and the via are generally made of a Cu-based metal having good conductivity, and the metal terminal pad is also formed as a Cu plating layer in a main body portion connected to the metal terminal pad. However, since the solder for connecting to the chip or the mother board is in contact with the metal terminal pad, Au plating is applied to improve the bonding strength with the solder and the wettability.

  By the way, the Cu plating layer forming the main body of the metal terminal pad is not so good in corrosion resistance. If the surface is covered with an oxide layer or the like, the adhesion of the Au plating layer may be deteriorated. In addition, there is a problem that Cu rises from the Cu plating layer to the Au plating layer surface by diffusion due to heating during reflow or the like, and the Au plating layer surface is covered with an oxide layer of Cu, so that solder wettability and solder jointability are significantly impaired. There is. In addition, the Sn component of the solder diffuses into the Cu plating layer via the Au plating layer, and tends to form a brittle Cu-Sn-based intermetallic compound layer. Particularly, when thermal stress or the like is applied, the Cu-Sn-based There is a problem that separation easily occurs between the compound layer and the underlying portion of the Cu plating layer. In particular, in a metal terminal pad for BGA (Ball Grid Allay) for connecting a substrate to a motherboard via a solder ball, the pad area is large and thermal stress is easily applied, so that the above-described problem is likely to occur.

  Therefore, a pad structure in which a Ni plating layer having good adhesion to Cu is formed as a barrier metal layer after a Cu plating layer is formed, and an Au plating layer is formed on the Ni plating layer is widely used. . There are two types of methods for forming the Ni plating layer: a method using electrolytic Ni plating and a method using electroless Ni plating (Patent Document 1). However, in the pad forming step using electrolytic Ni plating, conductive paths (tie bars) for plating connected to the pads are formed in a complicated and complicated manner on the dielectric layer surface (pad forming surface) on which the pads are formed. There is a need. In this method, the space for inserting the plating tie bar must be secured between the pads, so that the arrangement interval of the pads cannot be reduced beyond a certain value. There is a problem that becomes large. On the other hand, in the case of using electroless Ni plating, the above-mentioned problem does not occur because the plating tie bar is unnecessary, and even for a plurality of pads that are insulated from each other on the dielectric layer, immersion in the plating solution is performed. There is an advantage that the Ni plating layer can be easily formed.

  However, since a phosphate compound such as sodium hypophosphite is used as a reducing agent in an electroless Ni plating bath generally used for plating a pad of a wiring board, the obtained Ni plating layer has a thickness of 4 to 8%. It is possible to obtain only those containing a relatively large amount of P by mass. If a large amount of P is contained in the Ni plating layer, at the time of solder reflow, a Ni-based layer in which P is concentrated by P co-precipitated with Ni or the like is formed, impairing wettability with solder, and poor connection. May occur. Further, the Ni-Sn alloy layer formed by the reaction between Sn and Ni on the solder side may be formed in contact with the Ni-based layer in which P is concentrated, and peeling / breaking at the interface between these layers may occur. There is also a problem that such a situation is likely to occur.

  An object of the present invention is to dispose a barrier metal layer between a Cu plating layer and an Au plating layer of a metal terminal pad that can effectively suppress component diffusion between the Cu plating layer and the Au plating layer. Diffusion and reaction between the metal layer and the Cu plating layer or the Au plating layer hardly occur, and as a result, a wiring board that can greatly reduce the probability of occurrence of failures such as poor connection due to insufficient solder wetting of metal terminal pads and peeling / breaking. To provide.

Means for Solving the Problems and Effects of the Invention

  The wiring board according to the present invention includes a wiring laminated portion in which dielectric layers and conductive layers made of a polymer material are alternately laminated so that the first main surface is formed by the dielectric layer; A plurality of metal terminal pads arranged on the first main surface formed of the dielectric layer of the first, the metal terminal pad, the Cu plating layer is arranged on the first main surface side, the other outermost layer portion Has a structure in which an Au plating layer is disposed, and a barrier metal layer is interposed between the Cu plating layer and the Au plating layer. The barrier metal layer suppresses diffusion of Cu from the Cu plating layer to the surface of the Au plating layer due to diffusion. In addition, a solder component (particularly, in the case of a solder containing Sn such as a Pb-Sn-based solder, the Sn component) Plays a role in suppressing diffusion to the Cu plating layer via the Au plating layer.

  The first aspect of the wiring board of the present invention is characterized in that an electroless Ni plating layer having a P content of 3% by mass or less is disposed as the barrier metal layer disposed on the metal terminal pad. By setting the P content of the electroless Ni plating layer used as the barrier metal layer to 3% by mass or less, the wettability of the solder to the metal terminal pad (particularly, Sn-Pb-based solder) is greatly improved, so that the connection failure etc. Is less likely to occur. Further, even if the Ni-Sn alloy layer is formed by the reaction between Sn and Ni on the solder side, defects such as peeling and breakage are less likely to occur, and a high-strength bonded state can be easily obtained. The phosphorus content of the electroless Ni plating layer is desirably 1% by mass or less, and more desirably the detection limit or less.

  In this case, a Ni-B-based electroless Ni plating layer can be used as the electroless Ni plating layer. Ni-B electroless Ni plating is a non-phosphoric acid bath using a borohydride compound as a reducing agent, and can significantly reduce the P concentration of the Ni plating layer. In the Ni-B electroless Ni plating, hydrogen gas is generated during a reduction reaction of Ni deposition, and when this hydrogen gas is taken into the Ni plating layer, hydrogen occluded during solder reflow is released, Bubbles and blisters may be generated between the solder joints. In this case, it is preferable to perform baking for dehydrogenation after forming the Ni-B-based electroless Ni plating and before entering the solder reflow step. This baking is desirably performed at a temperature equal to or higher than the solder reflow temperature.

  A second aspect of the wiring board of the present invention is characterized in that a platinum group metal-based electroless plating layer is disposed as the barrier metal layer disposed on the metal terminal pad. The barrier metal layer made of a platinum group metal-based electroless plating layer has an effect of blocking the diffusion of Cu from the Cu plating layer to the surface of the Au plating layer, and the Cu plating layer side of the Au component of the solder component (particularly, the Sn component). Has a particularly good diffusion blocking effect. As a result, the wettability of solder (particularly, Sn-Pb-based solder) to the metal terminal pads is improved, and the occurrence rate of defects such as poor connection can be significantly reduced. Further, even if the Ni-Sn alloy layer is formed by the reaction between Sn and Ni on the solder side, defects such as peeling and breakage are less likely to occur, and a high-strength bonded state can be easily obtained. Further, when the Ni-B-based electroless Ni plating according to the first aspect of the present invention is used, as described above, the occluded hydrogen is released at the time of solder reflow, and bubbles and swelling are generated between the solder and the solder connection part. Although there is a concern, in the case of the platinum group metal-based electroless plating layer, there is no fear of occurrence of the problem because hydrogen is not generated during the plating reaction. Further, the platinum group metal-based electroless plating layer has extremely good corrosion resistance, and also has improved adhesion with the Cu plating layer and the Au plating layer.

  As the platinum group metal-based electroless plating layer constituting the barrier metal layer, a layer containing any of Ru, Rh, Pd, Os, Ir and Pt as a main component (a component having the highest mass content) can be adopted. Specifically, a barrier metal layer made of an electroless Pd plating layer is relatively inexpensive, easy to form, and excellent in performance, so that it can be suitably used in the present invention. On the other hand, the barrier metal layer composed of the electroless Ir plating layer, the electroless Pt plating layer, the electroless Rh plating layer, and the electroless Ru plating layer is slightly more expensive than the electroless Pd plating layer, but is more excellent in corrosion resistance. In some cases, the adhesion to the underlying Cu plating layer or the upper Ni plating layer can be further enhanced. Further, the electroless Pt plating layer, the electroless Rh plating layer, and the electroless Ru plating layer have a smaller diffusion coefficient with respect to Cu than the electroless Pd plating layer, and the barrier effect may be further enhanced.

  A third aspect of the wiring board of the present invention is a Ni-P-based electroless Ni plating layer in contact with the Cu plating layer as the barrier metal layer disposed on the metal terminal pad, and the Ni-P-based electroless Ni plating layer. And a P barrier electroless metal plating layer disposed between the Au plating layer and preventing or suppressing P diffusion from the Ni-P based electroless Ni plating layer to the Au plating layer. I do. According to this configuration, since the Ni-P-based electroless Ni plating layer that has already been used is used, the effect of blocking the diffusion of Cu from the Cu plating layer to the surface of the Au plating layer and the Au plating layer of the solder component (particularly, the Sn component) are used. The effect of blocking diffusion to the Cu plating layer after passing through can be ensured without any problem. Then, between the Ni-P-based electroless Ni plating layer and the Au plating layer, P barrier electroless metal plating for preventing or suppressing P diffusion from the Ni-P-based electroless Ni plating layer to the Au plating layer. Since the layers are arranged, even if a P-concentrated layer is formed, it is isolated from the Au plating layer by the P-barrier electroless metal plating layer. Performance can be greatly improved, and the rate of occurrence of problems such as poor connection can be reduced. Further, even if the Ni-Sn alloy layer is formed by the reaction between Sn and Ni on the solder side, defects such as peeling and breakage are less likely to occur, and a high-strength bonded state can be easily obtained.

  The P barrier electroless metal plating layer can be constituted by a Ni-B based electroless Ni layer. Since the Ni plating layers are formed, the adhesion to the Ni-P-based electroless Ni plating layer is good.

  Further, the P barrier electroless metal plating layer may be a platinum group metal-based electroless plating layer. The barrier metal layer made of a platinum group metal-based electroless plating layer has an effect of blocking the diffusion of Cu from the Cu plating layer to the surface of the Au plating layer, and the Cu plating layer side of the Au component of the solder component (particularly, the Sn component). Has a particularly good diffusion blocking effect. Further, since no hydrogen is generated during the plating reaction, there is no fear of the occurrence of the problem. Further, the platinum group metal-based electroless plating layer has extremely good corrosion resistance, and also has improved adhesion with the Cu plating layer and the Au plating layer. As the platinum group metal-based electroless plating layer, a layer containing any of Ru, Rh, Pd, Os, Ir and Pt as a main component (a component having the highest mass content) can be adopted. Specifically, an electroless Ir plating layer or an electroless Pd plating layer can be suitably used in the present invention.

  A fourth aspect of the wiring board according to the present invention includes, as the barrier metal layer disposed on the metal terminal pad, a Ni—B-based electroless Ni plating layer in contact with the Cu plating layer, An Ni-P-based electroless metal plating layer that is disposed between the Au-plated layer and thinner than the Ni-B-based electroless Ni-plating layer is disposed. By using Ni-B-based electroless Ni plating, the wettability of solder (particularly, Sn-Pb-based solder) to the auxiliary terminal pads is greatly improved, as in the first aspect of the present invention. Less likely to occur. Further, even if the Ni-Sn alloy layer is formed by the reaction between Sn and Ni on the solder side, defects such as peeling and breakage are less likely to occur, and a high-strength bonded state can be easily obtained. Further, as described above, by interposing the Ni-P-based electroless metal plating layer between the Ni-P-based electroless Ni plating layer and the Au plating layer, hydrogen absorbed in the Ni-B-based electroless Ni plating layer during the solder reflow is released. However, since the Ni-P-based electroless Ni plating layer that does not release hydrogen is interposed between the solder connection portion and the Au plating layer, bubbles and the like remain at the interface with the solder connection portion. No worries. Further, since the Ni-P-based electroless metal plating layer is formed thinner than the Ni-B-based electroless Ni plating layer, the degree of formation of the P-enriched layer is small, and there is little concern about poor solder wetting or poor adhesion. From this viewpoint, it is desirable that the thickness of the Ni—P-based electroless metal plating layer is adjusted to 2 μm or less, preferably 1 μm or less (the lower limit is set to, for example, 0.5 μm or more so that the above-described effect becomes remarkable). Do).

  A metal terminal pad (for example, a metal terminal pad for BGA) connected to a terminal pad on the motherboard side via a solder ball has a large pad area and is likely to be subjected to thermal stress. The effect is particularly remarkable.

  When the Ni plating layer directly contacts the Au plating layer, the Au plating layer is preferably an electroless reduced Au plating layer. The present inventor has conducted a detailed study and found that when a conventional substitutional Au plating is applied on the Ni plating layer, a very thin oxide film is formed between the substitutional Au plating layer and the Ni plating layer. . It is considered that the interface between the oxide film and the solder was easily peeled off due to the low adhesion strength between the oxide film and the solder in the conventional configuration.

  In the electroless displacement Au plating, potassium borohydride or dimethylamine borane is used as a reducing agent, and at least at the beginning of the reaction, a plating metal is deposited by a substitution reaction with a base metal on the side to be plated. In order for the substitution reaction to proceed, the underlying metal Ni needs to be eluted into the plating bath, but this elution is caused by the plating bath contacting the exposed portion of the underlying metal not covered by the plating metal. Occur. At this time, an oxide film is formed on the surface of the base metal by contact with the aqueous plating bath. On the other hand, since the plating metal deposited on the periphery goes around and grows on the oxide film, the oxide film tends to remain at the interface between the formed plating layer and the base metal. However, if the electroless reduced Au-based plating is employed as in the present invention, an oxide film is unlikely to remain at the interface with the Ni plating layer during the Au plating, so that even after the solder connection, the solder and the Ni plating layer are in contact with each other. Adhesion between them can be increased, and peeling at the interface with the solder can be greatly suppressed.

  Next, in recent years, so-called Pb-free solder, which does not contain Pb (or even contains up to 3% by mass), has been used instead of the conventional Sn-Pb eutectic solder due to the problem of environmental pollution. It has become. Most of Pb-free solders are mainly composed of Sn as in the conventional eutectic solder, but contain Ag, Cu, Zn, Bi, etc. as sub-components instead of Pb used in eutectic solder. I do. An eclectic solder is also used in which the main component of the subcomponent is composed of these elements, but some Pb is left. Since Pb-free solder has poor ductility compared to Sn-Pb eutectic solder, interface peeling at solder joints is more likely to occur.

  A commonly used Sn-Pb eutectic solder has a eutectic composition of Sn-38% by mass Pb, and has a melting point of 183 ° C. The melting point (liquidus) of the alloy increases even if the composition shifts to the Pb-rich side or the Sn-rich side. Simple Sn metal is equivalent to a simple reduction of all Pb from eutectic solder, but its melting point is 232 ° C, which is almost 50 ° C higher than the melting point of eutectic solder. difficult.

  Therefore, for Pb-free solder, a eutectic component other than Pb is searched for based on Sn. The conditions are that the effect of lowering the melting point is as large as possible, and that the price is low or the amount of addition is small even if somewhat expensive, that the solderability and flowability are good, and that the corrosion resistance is high. It is excellent. However, the types of subcomponents having these components in a well-balanced manner are unexpectedly limited, and are only a few elements such as Zn, Bi, Ag, and Cu. The Sn-Zn system has a eutectic point near 15% by mass Zn, and the melting point of the composition is reduced to about 195 ° C. However, Zn has a problem in corrosion resistance. Usually, the addition amount is about 7 to 10% by mass, but in a binary system near the composition, the melting point decreases only to about 215 ° C. Therefore, the melting point is adjusted by adding 1 to 5% by mass of Bi, but it is difficult to finally obtain a melting point of less than 200 ° C. Further, Bi is expensive and is a strategic substance, so that the supply stability is also difficult.

  On the other hand, Ag and Cu alone have a much higher melting point than Sn, but Sn-Ag-based materials have a Sn melting point of around 5% by mass Ag and Sn-Cu-based materials have a melting point of around 2% by mass Cu. There is a eutectic point on the side. The Ag-Cu system is also a eutectic system, and the melting point can be further reduced by using a ternary eutectic of Sn-Ag-Cu. However, both the Sn-Ag system and the Sn-Cu system have a binary eutectic temperature of about 220 ° C., and it is impossible to lower the melting point to 200 ° C. or less even if a ternary eutectic system is employed. . In the case of a Sn-Ag alloy, the recommended composition from the viewpoint of lowering the melting point has an Ag content of 3% by mass or more and 6% by mass or less with respect to Sn. Similarly, in the case of a Sn—Cu alloy, the Cu content is 1% by mass or more and 3% by mass or less with respect to Sn. Further, in the case of a Sn-Ag-Cu alloy, Ag + Cu is 3% by mass or more and 6% by mass or less, and Cu / (Ag + Cu) is 0.1% or more and 0.5 or less by mass ratio.

  As is clear from the above discussion, when an attempt is made to form a solder ball using a Sn alloy having a significantly reduced Pb content from Sn-Pb eutectic solder, the melting point of the solder becomes a high-temperature solder ball exceeding 200 ° C. (The upper limit is 232 ° C. for Sn alone). For example, even in Pb-free solders having various compositions listed in Table 1 of Non-Patent Document 2, the melting points (liquidus temperatures) Ts are all 200 ° C. or higher. From the viewpoint of environmental protection, the Sn alloy constituting the high-temperature solder ball has a Pb content of 5% by mass or less (more preferably 1% by mass or less, and still more preferably an unavoidable impurity level. Except that Pb is not contained as much as possible).

  In this case, the higher the solder joining temperature, the easier the formation of the compound between Sn and Ni becomes, and this is disadvantageous from the viewpoint of the solder joining strength. However, if the present invention is adopted, it is not necessary to worry at all about the decrease in the bonding strength due to the formation of the P-rich layer, so that the margin of the reduction in the strength due to the formation of the compound can be widened and a highly reliable solder bonding structure can be obtained. be able to. This effect is particularly remarkable when the high-temperature solder balls are directly bonded to the metal terminal pads.

Embodiment of the Invention

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 3 schematically shows a cross-sectional structure of a wiring board 1 according to one embodiment of the present invention. The wiring board has a predetermined pattern on both surfaces of a plate-like core 2 made of a heat-resistant resin plate (for example, a bismaleimide-triazine resin plate) or a fiber-reinforced resin plate (for example, a glass fiber-reinforced epoxy resin). Core conductor layers M1 and M11 forming the wiring metal layer are respectively formed. These core conductor layers M1 and M11 are formed as surface conductor patterns that cover most of the surface of the plate-like core 2, and are used as power supply layers or ground layers. On the other hand, a through-hole 12 formed by a drill or the like is formed in the plate-shaped core 2, and a through-hole conductor 30 that connects the core conductor layers M1 and M11 to each other is formed on the inner wall surface. The through hole 12 is filled with a resin filling material 31 such as an epoxy resin.

  On the upper layers of the core conductor layers M1 and M11, first via layers (build-up layers: dielectric layers) V1 and V11 made of the photosensitive resin composition 6 are formed, respectively. Further, first conductive layers M2 and M12 each having a metal wiring 7 are formed on the surface thereof by Cu plating. The core conductor layers M1 and M11 and the first conductor layers M2 and M12 are connected to each other by vias 34. Similarly, second via layers (build-up layers: dielectric layers) V2 and V12 using the photosensitive resin composition 6 are formed on the first conductor layers M2 and M12, respectively. On the surface thereof, second conductor layers M3 and M13 having metal terminal pads 8 and 18 are formed. The first conductor layers M2, M12 and the second conductor layers M3, M13 are interconnected by vias 34, respectively. As shown in FIG. 3, the via 34 includes a via hole 34h, a via conductor 34s provided on the inner peripheral surface thereof, a via pad 34p provided on the bottom surface so as to be electrically connected to the via conductor 34s, and a via pad 34p. And a via land 341 projecting outward from the peripheral edge of the opening of the via conductor 34h.

  On the first main surface MP1 of the plate-shaped core 2, the core conductor layer M1, the first via layer V1, the first conductor layer M2, and the second via layer V2 form a first wiring laminated portion L1. Further, on the second main surface MP2 of the plate-shaped core 2, the core conductor layer M11, the first via layer V11, the first conductor layer M12, and the second via layer V12 form a second wiring laminated portion L2. . In each case, the dielectric layers and the conductor layers are alternately laminated so that the first main surface CP is formed by the dielectric layer 6. Metal terminal pads 10 to 17 are formed respectively. The metal terminal pads 10 on the first wiring laminated portion L1 side constitute solder lands which are pads for flip-chip connection of an integrated circuit chip or the like. Further, the metal terminal pads 17 on the second wiring laminated portion L2 side are used as back surface lands (pads) for connecting the wiring substrate itself to a motherboard or the like by a pin grid array (PGA) or a ball grid array (BGA). Things. FIG. 4 shows an example in which the metal terminal pad 17 is configured as a BGA pad, and is formed of a solder ball (for example, a high-temperature solder such as a Pb-Sn alloy having a hypoeutectic composition or a Pb-free solder described in detail above). It is connected to the terminal pad 41 on the motherboard MB side via 140 via a solder connection layer 42 (for example, made of a eutectic Pb-Sn alloy).

  As shown in FIG. 1, the solder lands 10 are arranged in a grid at substantially the center of the first main surface of the wiring board 1, and the chip mounting portion 40 is formed together with the solder bumps 11 (FIG. 3) formed thereon. Has formed. Further, as shown in FIG. 2, the back lands 17 in the second conductor layer M13 are also arranged in a grid pattern. Then, on each of the second conductor layers M3 and M13, solder resist layers 8 and 18 (SR1 and SR11) made of a photosensitive resin composition are formed, respectively. In each case, an opening is formed in a one-to-one correspondence with each land in order to expose the solder land 10 or the back surface land 17.

  The via layers V1, V11, V2, V12 and the solder resist layers 8, 18 are manufactured, for example, as follows. That is, a photosensitive adhesive film obtained by forming a photosensitive resin composition varnish into a film is laminated (laminated), and a transparent mask (for example, a glass mask) having a pattern corresponding to the via hole 34h is overlaid and exposed. The film portion other than the via hole 34h is cured by this exposure, while the via hole 34h remains uncured. If this is dissolved in a solvent and removed, the via hole 34h can be easily formed in an intended pattern. (A so-called photo via process).

  FIG. 5 shows the solder lands 10 to the back lands 17 (hereinafter referred to collectively as metal terminal pads 10 and 17) of the wiring board according to the first embodiment of the present invention. The following description shows a specific example, in which the P content of the Cu plating layer 52 and the barrier metal layer is 3% by mass or less from the first main surface CP side of each of the wiring laminated portions L1 and L2. The Ni plating layer 121 (thickness: 2 μm or more and 7 μm or less) and the Au plating layer 54 (by electroless Au plating: 0.03 μm or more and 0.1 μm or less) are stacked in this order.

The electroless Ni plating layer 53 is a Ni-B-based electroless Ni plating layer. A bath containing Ni sulfate as a plating metal source and a borohydride compound (eg, NaBH ₄ or the like) added as a reducing agent is used. After the formation of the Ni-B-based electroless Ni plating layer 53, baking of dehydrogenation may be performed, for example, at a temperature near the solder reflow temperature or slightly higher (up to about + 50 ° C.).

  The first main surface CP of each of the wiring laminated portions L1 and L2 is covered with solder resist layers 8 and 18, and the inner peripheral edges of the openings of the solder resist layers 8 and 18 correspond to the metal terminal pads 10 and 17. It protrudes inward from the outer peripheral edge of the main surface. The outer peripheral edge 52p of the Cu plating layer 52 is in direct contact with the solder resist layers 8, 18, and the metal terminal pads 10, 17 are subjected to surface roughening. The electrolytic Ni plating layer 53 of the metal terminal pads 10 and 17 is covered with the Au plating layer 54 only in regions located inside the openings 8a and 18a of the solder resist layers 8 and 18.

  FIG. 6 shows a specific example of the metal terminal pads 10 and 17 of the wiring board according to the second embodiment of the present invention. The barrier metal layer is formed of a platinum group metal-based electroless plating layer 21. (Other structures are the same as those in FIG. 5). The platinum group metal-based electroless plating layer 21 is an electroless Pd plating layer (may be an electroless Ir plating layer, an electroless Pt plating layer, an electroless Rh plating layer, or an electroless Ru plating layer), The length is 0.05 to 1 μm (for example, 0.1 μm). A bath containing, for example, a chloride of Pd (or Ir, Pd, Rh, Ru) as a plating metal source and adding sodium hypophosphite or hydrazine as a reducing agent is used.

  FIG. 7 shows a specific example of the metal terminal pads 10 and 17 of the wiring board according to the third embodiment of the present invention, in which the barrier metal layer is made of a Ni—P-based electroless Ni plating layer in contact with the Cu plating layer 52. 22 (thickness: 2 μm or more and 7 μm or less) and a Ni-B-based electroless metal plating layer for a P barrier disposed between the Ni-P-based electroless Ni plating layer 22 and the Au plating layer 54. It is composed of an electroless Ni plating layer 121 (thickness: 0.05 μm or more and 2 μm or less, for example, 1 μm) (other structures are the same as in FIG. 5). The Ni—B-based electroless Ni plating layer 20 prevents or suppresses the diffusion of P from the Ni—P-based electroless Ni plating layer 22 to the Au plating layer 54. FIG. 8 shows a Ni-B-based electroless Ni plating layer 20 as a P barrier electroless metal plating layer of FIG. 7 replaced with a platinum group metal-based electroless plating layer 21 (an electroless Ir plating layer or an electroless Pd layer). (Plating layer).

  FIG. 9 shows a specific example of the metal terminal pads 10 and 17 of the wiring board according to the fourth embodiment of the present invention, in which the barrier metal layer is made of a Ni—B-based electroless Ni plating layer in contact with the Cu plating layer 52. 121 (thickness: 2 μm or more and 7 μm or less) and thinner than the Ni—B-based electroless Ni plating layer 121 disposed between the Ni—B-based electroless Ni plating layer 121 and the Au plating layer 54. It is composed of a Ni-P-based electroless metal plating layer 22 (thickness: 0.05 μm or more and 2 μm or less, for example, 1 μm) (other structures are the same as in FIG. 5). By interposing the thin Ni-P-based electroless metal plating layer 22 between the Ni-P-based electroless Ni plating layer 121 and the Au plating layer 54, even if hydrogen absorbed in the Ni-B-based electroless Ni plating layer 121 is released during solder reflow, Since the Ni-P-based electroless metal plating layer 22 blocks hydrogen, there is no fear that air bubbles and the like remain at the interface with the solder connection portion. Further, since the Ni-P-based electroless metal plating layer 22 is thin, the degree of formation of the P-enriched layer is small, and there is little concern about poor solder wetting or poor adhesion.

  In any of the above embodiments, as shown in FIG. 10, a solder ball 140 can be directly bonded to the metal terminal pad 17. In this case, as shown in step 3, the solder ball 140 'is placed on the pad 17, and in this state, as shown in step 4, the solder ball 140 is set to a temperature higher than the melting point of the solder constituting the ball. What is necessary is just to heat and fuse | melt, and just to bond to the pad 17.

  Also, instead of solder balls made of hypoeutectic solder, Sn-Ag-Cu alloy (for example, Sn-3 mass% Ag-0.5 mass% Cu), Sn-Cu alloy (for example, Sn-2 mass% Cu), The melting point of a Sn alloy such as a Sn-Ag-Pb alloy, a Sn-Zn alloy (for example, Sn-10 mass% Zn), and a Sn-Zn-Bi alloy (for example, Sn-8 mass% Zn-3 mass% Bi). A high-temperature solder ball having a liquidus temperature of 200 ° C. or more can also be used.

  When the solder balls 140 are joined, the outermost Au plating layer 54 originally formed on the pad 17 is melted and absorbed by the solder, and the underlying Ni plating layer 53 and the solder balls 140 come into contact with each other. As shown in FIG. 5, FIG. 7, and FIG. 9, when the Au plating layer 54 is in contact with the Ni plating layer 53 (121, 22) as shown in FIG. By forming a layer, the adhesion between the solder ball 140 and the Ni plating layer 53 can be greatly increased. The electroless reduction type Au plating is a kind of autocatalytic electroless Au plating in which a substitution reaction with the underlying Ni metal is not mainly performed. Examples of the water-soluble Au salt serving as an Au metal source used in the Au plating bath include dicyano Au (I) salts such as sodium dicyano Au (I) and ammonium dicyano Au (I); tetracyano Au (III) acid Tetracyano Au (III) salts such as potassium, sodium tetracyano Au (III), ammonium tetracyano Au (III); Au (I) cyanide, Au (III) cyanide; DichloroAu (I) salt; TetrachloroAu (III) acid compounds such as chloroAu (III) acid and sodium tetrachloroAu (III); Au sulfites such as Au ammonium sulfite, Au potassium sulfite and Au sodium sulfite; Au oxide, Au hydroxide and These include alkali metal salts, but are not limited thereto. Preferably, the water-soluble Au compound is potassium dicyano Au (I), potassium tetracyano Au (III), sodium tetrachloroau (III), ammonium ammonium sulfite, potassium potassium sulfite, and sodium sodium sulfite. As the water-soluble Au compound, only one kind may be used, or two or more kinds may be mixed. It is appropriate to contain these water-soluble Au compounds as Au ions, for example, at 0.1 to 10 g / L, preferably 1 to 5 g / L. If the concentration is less than 0.1 g / L, the plating reaction is slow or difficult to occur, whereas if the concentration is more than 10 g / L, the effect corresponding thereto is not significantly improved and it is not economical. .

  The complexing agent stably holds Au ions in the plating bath but does not substantially dissolve nickel in the plating bath. Such complexing agents include, for example, known chelating agents such as ethylenediaminetetraacetic acid, Au nitrites disclosed in Patent Literature 2, and further, a phosphonic acid group or An organic phosphonic acid having a plurality of salts thereof or a salt thereof is exemplified. The complexing agent is used in a range of, for example, 0.005 to 0.5 mol / L, preferably 0.02 to 0.2 mol / L. In particular, it is preferable to contain it in an amount equal to or more than the mole of Au ions contained in the plating bath. It is also effective to add the polyethyleneimine disclosed in Patent Document 3 to the Au plating bath in order to suppress the formation of the oxide film.

Specific bath compositions are exemplified below:
Gold potassium cyanide: 2 g / L (as gold ion)
Ethylenediaminetetramethylenephosphonic acid: 0.15 mol / L
Polyethyleneimine (molecular weight 2000): 5 g / L
pH: 7.0

  Hereinafter, the reason why the use of the above-described reduced electroless Au plating layer as the Au plating layer can significantly increase the bonding strength of the solder ball 140 to the pad 17 will be described.

  In FIG. 11, when an Au plating layer is formed on the Ni plating layer 53 as a conventional substituted Au plating layer 54 ', the substitution reaction between Au in the plating bath and Ni on the Ni plating layer 53 side is covered by the deposited Au. The plating bath comes in contact with the exposed portion of the uncovered base Ni, and the process proceeds as Ni elutes into the bath. At this time, as shown in the lower left of the figure, an oxide film 56 is formed on the surface of the Ni plating layer 53 by contact with an aqueous plating bath. On the other hand, since the Au deposited on the periphery goes around and grows on the oxide film 56, the oxide film 56 remains at the interface between the formed Au plating layer 54 'and the Ni plating layer.

  When the solder ball 140 is joined to the pad 17 thus formed, as shown in FIG. 13, the Au plating layer 54 'melts into the molten solder ball 140, and the Ni plating layer 53 and the solder 140 come into contact with each other. . The Ni component in the Ni plating layer 53 penetrates the thin oxide film 56 and diffuses to the solder 140 side, reacts with the Sn component to form a somewhat brittle Ni-Sn compound layer 140c, and forms the Au plating layer 54 '. Is in contact with the oxide film 56 formed on the lower side. Since the adhesion strength between the oxide film 56 and the Ni—Sn compound layer 140c is low, the bonding strength with the solder 140 tends to decrease.

  However, as shown in FIG. 12, the use of the Au plating layer 54 made of a reduced electroless Au plating layer suppresses the formation of an oxide film, and can increase the bonding strength between the Ni plating layer 53 and the solder ball 140. .

FIG. 1 is a plan view showing an embodiment of a wiring board of the present invention. FIG. FIG. 2 is a diagram illustrating an example of a cross-sectional structure of a wiring board according to the present invention. The figure which shows the connection structure by a BGA pad typically. FIG. 2 is a schematic cross-sectional view showing a main part of a metal terminal pad according to the first embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing a main part of a metal terminal pad according to a second embodiment of the present invention. FIG. 9 is a schematic cross-sectional view illustrating a main part of a metal terminal pad according to a third embodiment of the present invention. FIG. 13 is a schematic cross-sectional view illustrating a main part of another example of the metal terminal pad according to the third embodiment of the present invention. FIG. 9 is a schematic cross-sectional view illustrating a main part of a metal terminal pad according to a fourth embodiment of the present invention. Explanatory drawing which shows the process of directly joining a solder ball. Explanatory drawing which shows the process of forming an Au plating layer in comparison with substitution Au plating and reduction Au plating. FIG. 4 is a diagram for estimating and explaining an effect generation mechanism of reduced Au plating. The figure explaining the influence which the Ni-Sn compound layer has on the joining strength with solder.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Wiring board 6 Dielectric layer 7 Inner conductor layer 8, 18 Solder resist layer 8a, 18a Opening L1, L2 Wiring laminated part CP First main surface 10, 17 Metal terminal pad 34 Via 51 Plating base conductive layer
52 Cu plating layer 53 Ni plating layer 20, 21, 22, 121 Barrier metal layer 54 Au plating layer

Claims (16)

As the first main surface is formed of a dielectric layer, a wiring laminated portion in which dielectric layers made of a polymer material and a conductive layer are alternately laminated, and the dielectric layer of the wiring laminated portion Having a plurality of metal terminal pads arranged on the first main surface formed,
The metal terminal pad has a structure in which a Cu plating layer is disposed on the first main surface side and an Au plating layer is disposed on the outermost layer, and a barrier is provided between the Cu plating layer and the Au plating layer. A wiring board comprising an electroless Ni plating layer having a P content of 3% by mass or less as a metal layer.   The wiring board according to claim 1, wherein the electroless Ni plating layer is a Ni-B-based electroless Ni plating layer. As the first main surface is formed of a dielectric layer, a wiring laminated portion in which dielectric layers made of a polymer material and a conductive layer are alternately laminated, and the dielectric layer of the wiring laminated portion Having a plurality of metal terminal pads arranged on the first main surface formed,
The metal terminal pad has a structure in which a Cu plating layer is disposed on the first main surface side and an Au plating layer is disposed on the outermost layer, and a barrier is provided between the Cu plating layer and the Au plating layer. A wiring board, wherein a platinum group metal-based electroless plating layer is disposed as a metal layer.   The wiring board according to claim 3, wherein the platinum group metal-based electroless plating layer is an electroless Pd plating layer.   The wiring board according to claim 3, wherein the platinum group metal-based electroless plating layer is any one of an electroless Ir plating layer, an electroless Pt plating layer, an electroless Rh plating layer, and an electroless Ru plating layer. As the first main surface is formed of a dielectric layer, a wiring laminated portion in which dielectric layers made of a polymer material and a conductive layer are alternately laminated, and the dielectric layer of the wiring laminated portion Having a plurality of metal terminal pads arranged on the first main surface formed,
The metal terminal pad has a structure in which a Cu plating layer is disposed on the first main surface side and an Au plating layer is disposed on the outermost layer, and a barrier is provided between the Cu plating layer and the Au plating layer. The metal layer is a Ni-P-based electroless Ni plating layer in contact with the Cu-plated layer, and is disposed between the Ni-P-based electroless Ni-plated layer and the Au-plated layer, and the Ni-P-based electroless A wiring board, comprising: a P barrier electroless metal plating layer for preventing or suppressing P diffusion from a Ni plating layer to the Au plating layer.   The wiring board according to claim 6, wherein the electroless metal plating layer for a P barrier is a Ni-B-based electroless Ni layer.   The wiring board according to claim 6, wherein the P barrier electroless metal plating layer is a platinum group metal-based electroless plating layer. As the first main surface is formed of a dielectric layer, a wiring laminated portion in which dielectric layers made of a polymer material and a conductive layer are alternately laminated, and the dielectric layer of the wiring laminated portion Having a plurality of metal terminal pads arranged on the first main surface formed,
The metal terminal pad has a structure in which a Cu plating layer is disposed on the first main surface side and an Au plating layer is disposed on the outermost layer, and a barrier is provided between the Cu plating layer and the Au plating layer. As a metal layer, a Ni-B-based electroless Ni plating layer that is in contact with the Cu-plated layer, and is disposed between the Ni-B-based electroless Ni-plated layer and the Au-plated layer; A wiring board, comprising the Ni-P-based electroless metal plating layer thinner than the Ni plating layer.   The wiring board according to claim 9, wherein the thickness of the Ni—P-based electroless metal plating layer is 2 μm or less.   The Ni plating layer directly in contact with the Au plating layer, and the Au plating layer is an electroless reduced Au plating layer, any one of claims 1, 2, 4, 5, 6, 7, 9, and 10. 2. The wiring board according to claim 1.   The wiring board according to any one of claims 1 to 10, wherein the metal terminal pad is connected to a terminal pad on the motherboard side via a solder ball.   13. The wiring board with a solder member according to claim 12, wherein the solder ball is a high-temperature solder ball made of a Sn alloy having a liquidus temperature of 200 ° C. or higher.   14. The wiring board with a solder member according to claim 13, wherein the high-temperature solder balls are directly bonded to the metal terminal pads.   15. The wiring board with a solder member according to claim 14, wherein the high-temperature solder balls are made of a SnAg-based alloy or a SnCu alloy.   The wiring board with a solder member according to claim 14, wherein the high-temperature solder member is made of a Sn alloy having a Pb content of 5% by mass or less.

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