JPH08191126A - Manufacture of circuit board with i/o pin - Google Patents

Abstract

PURPOSE: To reduce the effect of impurities, specially lead, in a reaction metal layer, which cause reduction in the bonding strength of an I/O pin, by a method wherein a surface metal layer is formed on the reaction metal layer, which consists of an electroless Ni plated film formed on the surface of the conductor of a circuit board, and the I/O pin is connected with the circuit board via both metal layers of the reaction metal layer and the surface metal layer. CONSTITUTION: The surface of a conductor 2 of a ceramic circuit board is degreased, an activation treatment is performed and an electroless Ni-B plated film is formed on a a reaction metal layer 5. Then, an electroless Au plated film is formed as a surface metal layer 9 and the layers 5 and 9 are formed into junction metal layers. After this, an inter-diffusion is made to perform between the surface of the conductor 2, the plated film 5 and the plated film 9 by a heat treatment of the board and the adhesion between the junction metal layers is increased. After this heat treatment, an I/O pin 1 mounted previously with an Au-Ge brazing metal 3 is positioned on a metal layer formed on a board conductor part 6 and thereafter, the pin 1 is heated to a junction temperature and the I/O pin formed with an Ni-Ge intermetallic compound film is connected with the board.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electronic circuit board having I / O pins.

[0002]

2. Description of the Related Art Conventionally, a multilayer ceramic circuit board is assembled by mounting semiconductor elements, I / O pins, etc. on terminal pads provided on both sides of the ceramic board, and connecting a cooling section, a sealing section, etc. Be done. For these assembling, it is necessary to perform the joining without melting other solder materials in the assembling process. Therefore, a joining technique having a temperature hierarchy using a plurality of brazing materials having different melting points is used. Since the I / O pins and the ceramic circuit board are joined first in this assembly process, the I / O pin soldering material should have a melting point higher than the melting point of the solder material used in the subsequent assembly process. Must be selected.
Also, in the process of cooling from the brazing temperature to room temperature after joining the I / O pins, it is necessary to avoid the problems of ceramic destruction of the joint due to heat shrinkage stress of the brazing material and deterioration of product reliability due to residual stress. . These conditions and soft brazing filler metals (183 ° C to 320 ° C) used for other joining of electronic circuit components.
The bonding method of the I / O pin in consideration of the bonding temperature condition of Pb—Sn alloy having a melting point of ℃ is disclosed in Japanese Patent Application No. 12430/1989.
No. 4 specification. That is, 356 ° C to 45
A gold-germanium alloy having a high melting point of 0 ° C. is I
Can be effectively used as a brazing material for / O pins. According to this joining method, low residual stress, high strength connection and high reliability of the ceramic substrate can be obtained.

Further, a metal layer is formed on the conductor surface of the circuit board in order to properly connect the I / O pins to the multilayer ceramic circuit board. As the metal layer material, a method of providing a nickel or gold layer on a molybdenum conductor portion of a substrate is described in the prior art as described in JP-A-1-1060. As a metal film forming method, a sputtering method and a plating method are known. The characteristic of the sputtered film is that it is dense and has high adhesiveness to the underlying layer, but it has a drawback that the cost is high because a pattern separation step is required. The feature of the plating method is that it can form a film at low cost, but it requires a step of obtaining an adhesive force with the conductor surface on the substrate. Among the plating methods, electroplating provides a high-purity coating, but if electrodes or wiring that replaces it cannot be attached to each pattern to be plated, it may not be possible to form a film on an electrically independent pattern. is there. On the other hand, the electroless plating method has the drawback that impurities other than the target metal are simultaneously deposited, but it is the lowest cost process because it can uniformly form a film on a complicated and fine independent pattern.
For the above reasons, the electroless plating method was used for forming the metal layer on the conductor surface which is a fine pattern on the circuit board. Here, electroless nickel plating used for electronic parts is typically electroless nickel-boron alloy plating and electroless nickel-phosphorus alloy plating. Comparing the two, electroless nickel-boron alloy plating having a high melting point, good solderability, and low temperature plating was used.
This plated film provides a nickel film having a relatively high purity with a boron content of 0.5 wt% or less. However, since a commercially available solution is used for electroless nickel-boron alloy plating, the necessary component in the plating solution, that is, lead added as a stabilizer (actually as a lead compound), is not formed in the plating film at the same time as the film formation. Will be taken into. Similarly,
Lead (actually a lead compound) is also added to the activation treatment liquid for starting the electroless nickel-boron alloy plating reaction for the purpose of stabilizing the liquid. Therefore, the plating film produced with this commercially available solution contains lead impurities originating from the activation treatment solution and the electroless nickel-boron alloy plating solution. A surface metal layer was formed on the reaction metal layer by electroless gold plating.

By combining the above-mentioned conventional techniques, a nickel / gold layer formed on the surface of a conductor on a ceramic substrate was formed, and an attempt was made to bond I / O pins by using a gold-germanium brazing material. As a result, this circuit element is assembled in the next step, modified,
The I / O pin bonding strength was insufficient to withstand several times of attachment / detachment with the circuit board for repair or other reasons. As a result of investigating the cause, it was found that the impurities contained in the electroless nickel-boron alloy plating layer had a great influence on the strength reduction between the I / O pin and the substrate. Among the impurities, it has been found that a trace amount of lead in the electroless nickel-boron alloy plating film is the cause of lowering the bonding strength.

[0005]

According to the above conventional technique,
I / O pins were pinned using a gold-germanium brazing material to the nickel / gold bonding metal layer formed on the conductor surface on the circuit board requiring multi-layer bonding. These I / O
As a result of performing a tensile test on the pins and evaluating the bonding strength, a defective phenomenon of breaking at the bonding interface between the electroless nickel-boron alloy plating layer on the substrate and the brazing material occurred. By analysis,
It has been found that the deterioration of the bonding strength is caused by segregation of the bonding interface of lead impurities contained in the electroless nickel-boron alloy plating layer. Therefore, sufficient strength cannot be obtained for insertion / removal of the I / O pin connector, which is an obstacle to the assembly process and reliability during use.

The object of the present invention is to newly define the film thickness of the surface metal layer which absorbs impurities, especially lead, in the reaction metal layer which causes a decrease in I / O pin junction strength, and the film thickness of the reaction metal layer. Especially.

[0007]

In order to solve the above problems, it is necessary to reduce the influence of impurities, especially lead, in the reaction metal layer which causes a decrease in the bonding strength of the I / O pin.
As described above, the lead compound is added for the purpose of stabilizing the electroless plating solution. Therefore, the plating film produced with the commercially available solution contains lead impurities originating from the activation treatment solution and the nickel-boron alloy plating solution. Therefore, even if the electroless nickel-boron alloy plating film contains lead impurities, it is necessary that the bonding strength is not adversely affected. The solution means of the present invention is to define the optimum film thickness of each metal layer for stabilizing the impurities contained in the reaction metal layer, that is, the nickel-boron alloy plating film, especially lead in the pinning step. The composition of the reaction metal layer / surface metal layer is composed of an electroless nickel-boron alloy plating film / electroless gold plating film or an electroless nickel-boron alloy plating film / electroless palladium plating film. The conventional purpose of this surface metal layer is to prevent oxidation of the reaction metal layer and to secure solder wettability. In the present invention, the respective ranges of film thickness at which the effect is most exhibited are defined so that the surface metal layer has a role of stabilizing impurities contained in the reaction metal layer, particularly lead.

[0008]

According to the conventional method of joining the circuit board and the I / O pin, the joining strength is lowered due to the impurities in the reaction metal layer, especially lead. In order to solve this problem, the film thickness of each metal layer formed on the conductor surface of the circuit board is specified. I /
The O pin attachment process is roughly divided into two heat treatment processes, namely, a heat treatment process for improving adhesion with each metal layer and an I / O pin attachment process. The former enhances adhesion by mutually diffusing the conductor surface of the substrate and each metal film. When the film thickness composition of the reaction metal layer / surface metal layer is properly specified, the mutual diffusion of each layer (conductor surface-nickel, nickel-gold) that enhances the adhesion, and at the same time, the component of the surface metal layer is the electroless nickel plating film. The lead impurities contained in lead-gold alloy or lead-
It can be solid-solved or alloyed in the form of a palladium alloy. Similarly, gold or palladium may stabilize lead in the heat treatment step of I / O pin attachment. However, if the thickness of the reaction metal layer / surface metal layer is not sufficient to stabilize lead and lead that is incompatible with nickel metal is present in the plated film in an unstable form, lead impurities will Behaves like.
Pb impurity atoms are present in pairs with energetically stable vacancies rather than in the Ni lattice. The Pb impurity atom and vacancy pair gather together with the nickel-gold interdiffusion in the heat treatment step and move to the bonding interface under the Ni-Ge layer while growing and form a void. Along with segregation of lead to the joint interface, the voids sometimes accumulate and cracks occur. This is the cause of the decrease in bonding strength.

As described above, the film thicknesses of the reaction metal layer and the surface metal layer are regulated, and the impurities, especially lead are stabilized by mutual diffusion during the heat treatment. That is, the present invention not only protects the reaction metal layer and secures the solder wettability with respect to the surface metal layer, but also defines the film thickness that has the role of stabilizing impurities, especially lead, and defines the I / O pin bonding interface. It is characterized by eliminating lead segregation to the steel and obtaining high bonding strength and reliability.

[0010]

【Example】

(Embodiment 1) Regarding the embodiment of the present invention, a circuit board and I / O
The pin joining method will be described below with reference to FIG. No. 1 in FIG. No. 1 is I / O pin, No. No. 2 is a conductor portion in the ceramic substrate, No. 3 is gold-germanium (hereinafter Au-Ge
Brazing filler metal, No. 4 is nickel-germanium (hereinafter Ni-G) produced by diffusion bonding when I / O pins are attached.
a metal compound layer, No. 5 is electroless nickel
Boron alloy (hereinafter referred to as Ni-B) plating film reactive metal layer, No. No. 6 is a conductor portion on the surface of the circuit board. 7 is a through hole. First, a method of forming the circuit board and the I / O pin bonding metal layer used in the experiment of the present invention will be described. FIG. 2A shows an explanatory view of the circuit board before the formation of the I / O pin joining metal layer, and FIG. 2B shows an illustration of the I / O pin joining conductor portion on the board surface. FIG. 3 is a process drawing of a metal layer for joining I / O pins. FIG. 3A is a sectional view of the conductor portion and through hole of the substrate shown in FIG. 2B, and the substrate is a ceramic circuit substrate. As a pretreatment, the conductor surface was soft-etched with an alkaline solution, neutralized with an acid, and degreased. Next, activation treatment was performed using a solution containing a lead compound as a stabilizer (FIG. 3 (b)). Then, an electroless Ni-B plating film (No. 5) was formed as a reactive metal layer (see FIG. 3).
(c)), an electroless Au plating film (No.
9) was formed (FIG. 3 (d)) to form a bonding metal layer. After the film formation, the conductor surface / electroless Ni—B plating film / electroless Au plating film is mutually diffused by heat treatment of the substrate to improve the adhesion between the joining metal layers (FIG. 3 (e)). After the heat treatment, I / O pins on which Au-Ge brazing material is mounted in advance
After positioning on the metal layer formed on the board conductor portion (FIG. 3 (f)), it was heated to the bonding temperature. At the same time that the Au-Ge brazing material wets and spreads on the surface of the joining metal layer, electroless Ni-B
I / O by diffusing into the plating layer to form a Ni-Ge metal compound
The pins are connected to the substrate.

The tensile strength of the I / O pin was measured in order to evaluate the bonding state between the I / O pin connected in the above process and the conductor portion on the substrate. When the joining condition is good, the I / O pin joint part (brazing part) does not break, and the I / O pin itself breaks at a certain strength (about 5 kg / pin) or more. I / O
The condition is that the joint strength of the brazed part per pin is higher than the tensile strength of the material of the I / O pin shaft part. Therefore, the bond strength was evaluated from Table 1 as the interface rupture rate, that is, the value obtained by dividing the number of I / O pins that caused interface rupture at a certain strength or less by the total number of I / O pins subjected to the tensile test. Three
It was shown to.

[0012]

[Table 1]

[0013]

[Table 2]

[0014]

[Table 3]

As a comparative example, No. 1 in Table 1 was used. When the bonding strength of the I / O pin was evaluated by bonding to the film structure of the conventional method shown in 1, the interfacial fracture rate was 100%, which was an extremely low value. Analysis of the cause of the low bonding strength revealed that lead was segregated on the fracture surface of the I / O pin where interface fracture occurred.

I / O pin joint failure when using the prior art,
That is, the mechanism of deterioration of the bonding strength due to Pb segregation is inferred. The compatibility of each metal used for joining with Pb was considered from the phase diagram of the alloy. 4 and 5 are the Ni-Pb binary phase diagram and the Ge-Pb binary phase diagram (Thaddeus B. Massalski, Ed .; BINARY ALLOY, respectively).
PHASE DIAGRAMS, 1986). As can be seen from this state diagram, Pb is solid-dissolved in an extremely small amount of Ni in the joining temperature region (around 400 ° C.), but is not solid-soluted at room temperature. Similarly, from the Ge-Pb binary system phase diagram, it can be seen that Pb does not form a solid solution with Ge at a temperature near the bonding temperature to room temperature. It can be seen that the impurity Pb does not exist as a stable metal compound or alloy with respect to the bonding material metal under the temperature condition for forming the circuit board. In this way, Ni, Ge
If lead impurities, which are incompatible with metals, are present in the joint material, lead segregation occurs as follows after I / O pinning.
This is because the Pb impurity atom having an atomic radius 1.4 times larger than that of Ni is more energetically stable when it is present in a pair with the vacancy than in the Ni lattice. FIG.
FIG. 6 is an enlarged schematic view of a cross section of the micro-joint portion of the joint portion shown in FIG. The Pb impurity atom and vacancy pairs gather at the time of diffusion bonding in the heat treatment step, move to the bonding interface under the Ni—Ge layer while growing, and form a void. Along with the segregation of lead (No. 12), the voids are sometimes accumulated to generate cracks (No. 13). When the bond strength of the I / O pin is measured, fracture occurs at the bond interface thus brittle. This is the cause of the decrease in I / O pin joint strength.

The reason why gold as the surface metal layer component can effectively stabilize lead impurities in the reaction metal layer by defining the film thickness of the reaction metal layer / surface metal layer is shown below. FIG. 7 is a phase diagram of the Au-Pb binary system (Thaddeus B. Massalski,
Ed .; BINARY ALLOY PHASEDIAGRAMS, 1986). As can be seen from this state diagram, while the I / O pin junction temperature rises to the heat treatment temperature and cools to room temperature, Au solid-dissolves lead and forms a metal compound or alloy. The Au of the surface metal layer diffuses during the heat treatment to form a solid solution with the impurity Pb or forms an alloy with the impurity Pb to form a stable Au-Pb alloy. Au in the Au-Ge brazing agent for I / O pinning also plays a similar role.

The reason for defining the thickness of the bonding metal layer will be described. In the plating film formed under a certain condition, a certain amount of the total of Pb originating from the activation treatment agent existing at the bottom of the plating film and Pb originating from the plating solution uniformly existing in the plating film having a certain thickness. It is included. The minimum amount of gold that stabilizes the Pb impurities until they do not adversely affect the junction, that is, the minimum gold plating film thickness, corresponds to this Pb impurity amount. Therefore, the minimum value of the Au plating film thickness that stabilizes the Pb impurities under a certain heat treatment condition is determined. Next, the maximum value of the film thickness of the reactive metal layer is determined because the thicker the film, the less stable lead is for the following two reasons.
Lead from the activation treatment agent that forms the core of electroless plating is
It exists at the interface between the conductor surface and the electroless Ni-B plating film.
When the temperature condition and the time condition are the same, the diffusion distances of the gold and lead impurities of the surface metal layer component in the heat treatment process are constant. The thicker the electroless Ni-B plating film, the lower the possibility that lead existing at the bottom of the plating film will completely alloy with gold. Another reason is that the lead derived from the plating solution is uniformly present in the electroless Ni-B plating film, so that the thicker the plating film is, the larger the total amount of lead impurities is and the gold cannot completely stabilize the lead. . For these reasons, the effect of preventing interfacial segregation by forming a Pb-Au alloy and sufficiently stabilizing it is effective only when the structure of the reaction metal layer / surface metal layer has an optimum film thickness.

As described above, in order to improve the bonding strength, in addition to protecting the reaction metal layer and ensuring the solder wettability so as not to cause Pb segregation at the bonding interface, I /
As the role of the surface metal layer that absorbs impurities, especially Pb, at the time of O-pin bonding, the effective Au plating film thickness is defined, and the optimum Ni film is formed by changing the film thickness corresponding to the amount of lead in the Ni-B plating plating film. -Defining the B plating film thickness is an effective means.

For example, the electroless Ni-B plating film thickness is set to 3.
The bonding strength of the I / O pin was measured while keeping the Pb impurity amount in the film constant at 5 μm, that is, by changing the electroless Au plating film thickness. Table 1 shows the results. In addition,
The electroless Ni-B plating film thickness and the electroless Au plating film thickness represent the plating film thickness formed in the process drawings, FIG. 2 (c) and FIG. 2 (d), respectively. When the electroless Au plating thickness is 0.05 μm in the case of the conventional method, the interface fracture rate is as high as 76%, when the electroless Au plating thickness is 0.5 μm, it is 21%, and when the Au plating thickness is 1 μm or more, it is 0%. Therefore, if the electroless Au plating thickness is 1 μm or more, no interface breakage occurs. Therefore, if the electroless Au plating film thickness is 1 μm or more, the electroless Ni—B plating film can be protected and solder wettability can be secured, and the P content in the electroless Ni—B plating film of 3.5 μm can be ensured.
It was found that it absorbs b and is effective in preventing interfacial rupture of I / O pins.

Next, the case where the electroless Au plating film thickness is constant will be described. As described above, Pb in the electroless Ni-B plating film is mixed from i) Pd activation treatment liquid and ii) plating liquid. Since i) has the optimum treatment time, the amount of Pb mixed from the activation treatment agent is constant. Since the optimum amount of Pb compound which is a stabilizer in the plating solution is determined as a plating solution component, Pb mixed in from ii) is taken into the plating film almost uniformly. By changing the film thickness, the total Pb amount in the plating film changes. So, for example,
Electroless Au plating film thickness is 1.0 μm and electroless Ni-
Table 2 shows the results of measuring the bonding strength by changing the amount of Pb contained in the B plating film. When the electroless Ni-B plating film thickness was 2.0 μm or less, no interface rupture occurred. However, even if the electroless Au plating film thickness is 1.0 μm or more, the interface fracture rate increases when the electroless Ni—B plating film thickness is 2.2 μm or more. Therefore, electroless Ni-B
It was found that if the plating film thickness is 2.2 μm or less, that is, if the amount of Pb contained in the film is 1.0 μm, the Au plating film of 1.0 μm absorbs Pb and is effective in preventing the interface breakage of the I / O pin. It was For comparison, pure Ni containing no Pb is used.
The evaluation results of joining the I / O pins to the plate are shown in Table 3, and the joining state was sufficient regardless of the thickness of the electroless gold plating film. By this experiment, Pb in the electroless Ni-B plating film
It has been clarified that the impurities contribute to the deterioration of the bonding strength.

As described above, even if Pb impurities are present in the electroless Ni-B plating film, the surface metal layer, that is, Pb impurities can be absorbed so that sufficient bonding strength can be secured without causing interface rupture. The gold plating film was regulated to have an appropriate thickness to improve the bonding strength.

As described above, according to the embodiment, the segregation of lead to the joint interface, which is the cause of the decrease in joint strength, is eliminated, and high strength is obtained.
I / O pin connection was achieved. Therefore, using this method, I / O pins were joined to the ceramic circuit board and a series of assembling was performed.

(Example 2) Next, the same measurement was performed using an electroless palladium plating film as a metal in place of gold which is a noble metal. That is, using an electroless Ni-B plated film as a reactive metal layer and an electroless palladium plated film as a surface metal layer on the surface of a substrate conductor, I / O pins are joined with an Au-Ge brazing material to improve the joint strength. It was measured. As a result, it was found that the same result as the gold plating film was obtained as the surface metal layer, and that it could be used as a plating film that can replace gold plating and reduce costs.

As described above, according to the present embodiment, the segregation of lead to the bonding interface, which is the cause of the decrease in the bonding strength, was eliminated, and high-strength I / O pin bonding was achieved. Therefore, using this method, I / O pins were joined to the ceramic circuit board and a series of assembling was performed.

[0026]

According to the present invention, a surface metal layer that absorbs lead, which is an impurity in the reaction metal layer, is provided on the surface of the bonding electrode, and the thickness of the surface metal layer is regulated. Segregation of lead to the interface can be eliminated. therefore,
This is a new joining method that can prevent the interface rupture between the circuit board and the I / O pin joint. As a result, a high bonding strength between the circuit board and the I / O pin can be obtained, so that the packaging structure of the ceramic circuit board having a temperature hierarchy can be highly reliable and the productivity can be improved. Further, the cost can be reduced by the plating method used for forming the joining metal layer and the selection of the surface metal layer material.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a joint portion in which a circuit board and an I / O pin are joined by using a circuit board with an I / O pin of the present invention and a method for manufacturing the same.

FIG. 2 is a schematic view of a circuit board before attaching I / O pins of the present invention (a).
And explanatory drawing of the conductor part formed in the surface.

FIG. 3 is an explanatory view schematically showing a step of forming a bonding metal on a conductor surface on a circuit board before I / O pin attachment according to the present invention.

FIG. 4 is a nickel-lead binary phase diagram according to the present invention.

FIG. 5 is a phase diagram of a germanium-lead binary system according to the present invention.

FIG. 6 is a cross-sectional view of a joint portion when an I / O pin is joined to a metal layer formed on a conductor surface of a circuit board by a conventional method.

FIG. 7 is a gold-lead binary system phase diagram according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... I / O pin, 2 ... Circuit board, 3 ... Gold-germanium brazing material, 4 ... Nickel-germanium metal compound layer, 5 ... Electroless nickel-boron alloy plating reaction metal layer, 6 ... Substrate surface conductor part, 7 … Through holes.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] April 6, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a joint portion in which a circuit board and an I / O pin are joined by using a circuit board with an I / O pin of the present invention and a method for manufacturing the same.

FIG. 2 is a schematic view of a circuit board before attaching I / O pins of the present invention (a).
And (b) an explanatory view of a conductor portion formed on the surface thereof.

FIG. 3 is an explanatory view schematically showing a step of forming a bonding metal on a conductor surface on a circuit board before I / O pin attachment according to the present invention.

FIG. 4 is a nickel-lead binary phase diagram according to the present invention.

FIG. 5 is a phase diagram of a germanium-lead binary system according to the present invention.

FIG. 6 is a cross-sectional view of a joint portion when an I / O pin is joined to a metal layer formed on a conductor surface of a circuit board by a conventional method.

FIG. 7 is a gold-lead binary system phase diagram according to the present invention.

[Explanation of reference numerals] 1 ... I / O pin, 2 ... Circuit board, 3 ... Gold-germanium brazing material, 4 ... Nickel-germanium metal compound layer, 5 ... Electroless nickel-boron alloy plating reaction metal layer, 6 ... Substrate Surface conductor, 7 ... through hole.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Setsuo Ando 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd.Institute of Industrial Science and Technology, Hitachi, Ltd. (72) Inventor Takayoshi Watanabe 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Ltd. Production Engineering Laboratory, Hitachi, Ltd. (72) Inventor Toshihiko Ota 1 Horiyamashita, Horiyamashita, Hadano-shi, Kanagawa Hitachi General Computer Division

Claims (4)

[Claims] 1. A method for joining an I / O pin and a circuit board,
(1) A reaction metal layer is formed by an electroless nickel plating film on the conductor surface of the circuit board, and (2) oxidation of the reaction metal layer and I / O pins are joined on the reaction metal layer. A surface metal layer that plays three roles of ensuring wettability with the brazing filler metal and absorbing impurities that are contained in the reaction metal layer and cause a decrease in bonding strength, and (3) the reaction metal layer and A method for manufacturing a circuit board with I / O pins, comprising bonding I / O pins to a circuit board via the surface metal layer. 2. The method for manufacturing a circuit board according to claim 1, wherein the brazing material is a gold-germanium alloy. 3. The method for manufacturing a circuit board with I / O pins according to claim 1, wherein the surface metal layer is made of gold or palladium, and an electroless plating method is used as a forming method thereof. 4. The conductor of the circuit board according to claim 1, wherein the reaction metal layer / the surface metal layer is composed of nickel / gold or nickel / palladium, and the laminated metal film is heat-treated. At the same time as improving the adhesion to the surface, some or all of the trace amount of impurities contained in the electroless nickel plating film are impurities-gold alloy or impurities-
A method for manufacturing a circuit board with I / O pins, which obtains high strength I / O pin bonding by alloying in the form of a palladium alloy.