JP2004297075A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a thin film transistor having enhanced reliability. <P>SOLUTION: A thin film transistor comprising a first gate electrode layer having a tapered part, a gate electrode having a second gate electrode layer narrower than the first gate electrode layer, a channel forming region, a lightly doped impurity region overlapping the gate electrode, a lightly doped impurity region not overlapping the gate electrode, and a semiconductor layer having a heavily doped impurity region is fabricated. Off current can thereby be decreased and deterioration of characteristics can be suppressed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a thin film transistor (hereinafter, referred to as a TFT) and a circuit including the thin film transistor. For example, the present invention relates to a configuration of an electro-optical device typified by a liquid crystal display panel as a semiconductor device and an electronic device equipped with such an electro-optical device as a component. Note that in this specification, a semiconductor device generally means a device that functions by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are also semiconductor devices.

  In recent years, an active matrix type liquid crystal display device in which a circuit is formed by a TFT using a crystalline silicon film has attracted attention. This is to realize a high-definition image display by controlling the electric field applied to the liquid crystal in a matrix by a plurality of pixels arranged in a matrix.

  In such an active matrix type liquid crystal display device, as the resolution becomes higher such as XGA or SXGA, the number of pixels alone exceeds one million. A driver circuit for driving all of them is very complicated and formed by many TFTs.

  Specifications required for an actual liquid crystal display device (also referred to as a liquid crystal panel) are strict, and high reliability must be secured for both pixels and drivers in order for all pixels to operate normally. In particular, when an abnormality occurs in the driver circuit, a defect called a line defect occurs in which pixels in one column (or one row) are completely annihilated.

  However, it is said that a TFT using a crystalline silicon film is still less reliable than a MOSFET (transistor formed on a single crystal semiconductor substrate) used for an LSI or the like in terms of reliability. Unless this weakness is overcome, it is increasingly viewed that it is difficult to form an LSI circuit with TFTs.

  Known structures for improving the reliability of the TFT include GOLD (Gate Overlapped Light-Doped Drain) and LATID (Large-Tilt-Angle Implanted Drain). The feature of these structures is that the LDD region and the gate electrode overlap with each other, whereby the impurity concentration in the LDD region can be reduced, the effect of relaxing the electric field increases, and the hot carrier resistance increases. Increase.

  For example, in Non-Patent Document 1, a GOLD structure TFT is realized using a sidewall formed of silicon.

M. Hatano, H. Akimoto, and T. Sakai, IEDM97 TECHNICAL DIGEST, p523-526, 1997

  However, the GOLD structure disclosed in the same paper has a problem that the off-state current (current flowing when the TFT is in an off-state) is larger than that of a normal LDD structure, and a countermeasure for the problem is required.

  An object of the present invention is to solve the drawbacks of the GOLD structure TFT, reduce the off-current, and provide a TFT having high hot carrier resistance. It is another object of the present invention to realize a highly reliable semiconductor device including a semiconductor circuit in which a circuit is formed using such a TFT.

  In order to solve the above-described problem, a thin film transistor according to the present invention includes, in addition to an n-type or p-type first impurity region functioning as a source or drain region in a semiconductor layer where a channel is formed, a channel and a first impurity region. There are impurity regions (second and third impurity regions) having the same conductivity type as the two types of first impurity regions between the one impurity region. These second and third impurity regions have a lower impurity concentration that determines the conductivity type than the first impurity region, and function as high-resistance regions.

  The second impurity region is a low-concentration impurity region overlapping the gate electrode with the gate insulating film interposed therebetween, and has a function of increasing hot carrier resistance. On the other hand, the third impurity region is a low-concentration impurity region that does not overlap with the gate electrode, and has a function of preventing an increase in off-state current.

  Note that a gate electrode is an electrode which intersects with a semiconductor layer with a gate insulating film interposed therebetween, and is an electrode for forming a depletion layer by applying an electric field to the semiconductor layer. In the gate wiring, a portion intersecting the semiconductor layer with the gate insulating film interposed therebetween is a gate electrode.

  Further, in the present invention, the film thickness of the gate electrode linearly decreases from the central flat portion toward the outside around the gate electrode. Since the impurity imparting the conductivity type is added to the second impurity region through the tapered portion of the gate electrode, the concentration gradient reflects the inclination of the side surface of the gate electrode (change in film thickness). That is, the impurity concentration added to the second impurity region increases from the channel formation region toward the first region.

  In the present invention, in another gate electrode configuration, a first gate electrode in contact with a gate insulating film and a second gate electrode formed over the first gate electrode are stacked. In this structure, the angle formed by the first gate electrode with the side surface or the gate insulating film is a taper having a value in a range of 3 degrees or more and 60 degrees or less. On the other hand, the width of the second gate electrode in the channel length direction is smaller than that of the first gate electrode.

  Also in the above-described thin film transistor having a stacked gate electrode, the impurity concentration distribution in the second impurity region reflects a change in the thickness of the first gate electrode, and the impurity concentration varies from the channel formation region to the first region. To increase.

  The thin film transistor according to the present invention has two types of low-concentration impurity regions in the semiconductor layer, and thus has reliability comparable to or higher than that of a MOSFET.

(Advantages of Thin Film Transistor of the Present Invention) With reference to FIG. 34, advantages of the present invention will be described in comparison with characteristics of a conventional TFT.

  As described above, the present invention forms two types of low-concentration impurities in a semiconductor layer, that is, a second impurity region (a gate overlap type LDD region) and a third impurity region (a non-gate overlap type LDD region). There is a feature.

  FIG. 34A is a schematic diagram of an n-channel TFT without an LDD region, and FIG. 34B shows its electric characteristics (gate voltage Vg vs. drain current Id characteristics). Similarly, FIGS. 34 (C) and (D) show the case of a normal LDD structure, FIGS. 34 (E) and (F) show the case of a so-called GOLD structure, and FIGS. 34 (G) and (H) show Shows the case of the n-channel TFT of the present invention.

In the drawings, n ⁺ indicates a source region or a drain region, channel indicates a channel formation region, and n ⁻ indicates a low-concentration impurity region having a lower impurity concentration than n ⁺ . Id indicates a drain current, and Vg indicates a gate voltage.

  As shown in FIGS. 34A and 34B, when there is no LDD, the off current (the drain current when the TFT is in the off state) is high, and the on current (the drain current when the TFT is in the on state) and Off current is likely to deteriorate.

  On the other hand, by forming a non-gate overlap type LDD, off-state current can be considerably suppressed, and deterioration of both on-state current and off-state current can be suppressed. However, the deterioration of the ON current is not completely suppressed. (FIGS. 34 (C) and (D))

  The TFT structure (GOLD structure) having only an overlap type LDD in which the LDD region overlaps with the gate electrode (FIGS. 34E and 34F) is different from the conventional LDD structure in that the ON current is deteriorated. It has a structure that focuses on suppressing noise.

  In this case, the deterioration of the on-state current can be sufficiently suppressed, but there is a problem that the off-state current is slightly higher than that of a normal non-overlap type LDD structure. The paper described in the conventional example employs this structure, and the present invention recognizes the problem that the off-state current is high and seeks a structure to solve the problem.

  Then, as shown in FIGS. 34G and 34H, the structure of the present invention includes an LDD region (second impurity region) overlapping the gate electrode and an LDD region (third impurity region) not overlapping the gate electrode. Impurity region) was formed in the semiconductor layer. By employing this structure, it is possible to reduce the off-current while maintaining the effect of suppressing the deterioration of the on-current.

  The present applicant has guessed why the off-state current is increased in the case of the structure shown in FIGS. 34 (E) and (F) as follows. When the n-channel TFT is in the off state, a negative voltage such as minus several tens of volts is applied to the gate electrode. If a positive voltage of plus several tens of volts is applied to the drain region in that state, an extremely large electric field is formed at the drain-side end of the gate insulating film.

  At this time, holes are induced in the LDD region, and a current path is formed by minority carriers connecting the drain region, the LDD region, and the channel formation region. This current path is expected to cause an increase in off-state current.

  The present applicant has considered that in order to cut off such a current path halfway, it is necessary to form another resistor, that is, a third impurity region LDD region at a position that does not overlap with the gate electrode. The present invention relates to a thin film transistor having such a configuration and a circuit using the thin film transistor.

  By implementing the present invention, the reliability of the TFT can be improved, and particularly, the reliability of the n-channel TFT can be improved. Therefore, it is possible to ensure the reliability of the channel FT having high electrical characteristics (especially high mobility) for which strict reliability is required. At the same time, a semiconductor circuit having high reliability and excellent electrical characteristics can be formed by forming a CMOS circuit by combining an n-channel TFT and a p-channel TFT with excellent characteristic balance.

  Further, according to the present invention, since the number of catalytic elements used for crystallization of a semiconductor can be reduced, a semiconductor device with less instability can be realized. Moreover, since the step of reducing the catalytic element is performed simultaneously with the formation and activation of the source region and the drain region, the throughput does not decrease.

  In addition, by improving the reliability of a circuit formed by TFTs as described above, it is possible to ensure the reliability of all semiconductor devices including an electro-optical device, a semiconductor circuit, and electronic devices.

An embodiment of the present invention will be described with reference to FIGS.

[Embodiment 1]
In this embodiment, the present invention is applied to a TFT. The manufacturing process of the present embodiment will be described with reference to FIGS.

  First, a base film 101 is formed over the entire surface of the substrate 100, and an island-shaped semiconductor layer 102 is formed over the base film 101. An insulating film 103 serving as a gate insulating film is formed over the entire surface of the substrate 100 so as to cover the semiconductor layer 102. (Fig. 1 (A))

  As the substrate 100, a glass substrate, a quartz substrate, a crystalline glass substrate, a stainless steel substrate, or a resin substrate such as polyethylene terephthalate (PET) can be used.

  The base film 101 is a film for preventing impurities such as sodium ions from diffusing from the substrate into the semiconductor layer 102 and for improving the adhesion of the semiconductor film formed over the substrate 100. As the base film 101, a single-layer or multilayer film of an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used.

  The method of forming the base film 101 is not limited to the CVD method and the sputtering method. When a heat-resistant substrate such as a quartz substrate is used, an amorphous silicon film is formed and thermally oxidized to form a silicon oxide film. A forming method can also be used.

  The base film 101 is not limited to the above-described inorganic insulating film, and a conductive film such as a metal or an alloy such as silicide such as tungsten silicide, chromium, titanium, titanium nitride, or aluminum nitride. A multilayer film stacked on the upper layer can be used as a base film.

  The material and crystallinity of the semiconductor layer 102 may be appropriately selected in accordance with characteristics required for the TFT. It is possible to use amorphous silicon, amorphous silicon germanium, amorphous germanium, or crystalline silicon, crystalline germanium, or crystalline silicon germanium obtained by crystallizing these amorphous semiconductor films by laser irradiation or heat treatment. it can. The thickness of the semiconductor layer 102 may be 10 to 150 nm.

  The insulating film 103 is a film constituting a gate insulating film of a TFT, and is a single-layer film or a multilayer film of an inorganic insulating film of silicon oxide, silicon nitride, or silicon nitride oxide. For example, in the case of a stacked film, a two-layer film of a silicon nitride oxide film and a silicon oxide film, a stacked film in which a silicon nitride film is sandwiched between silicon oxides, and the like are used.

  As a means for forming the insulating film 103, a chemical vapor deposition method (CVD) such as a plasma CVD method or an ECRCVD method, or a physical vapor deposition method (PVD) such as a sputtering method may be used.

  A first conductive film 104 and a second conductive film 105 which form a gate electrode (gate wiring) are formed over the insulating film 103. (FIG. 1 (B))

  The first conductive film 104 forms a first gate electrode (first gate wiring) 108 having a tapered portion. Therefore, a material that can easily perform taper etching is desired. For example, a material containing chromium (Cr) or tantalum (Ta) as a main component (composition ratio is 50% or more), and n-type silicon containing phosphorus are typically used. Alternatively, a material containing titanium (Ti), tungsten (W), molybdenum (Mo), or the like as a main component can be used. Further, not only a single-layer film of these materials but also a multilayer film can be used. For example, a three-layer film in which a tantalum film is sandwiched between tantalum nitride (TaN) films can be used.

  The second conductive film 105 is a film constituting the second gate electrode (second gate wiring) 109, and is made of aluminum (Al), copper (Cu), chromium (Cr), tantalum (Ta), and titanium (Ti). , Tungsten (W), a material containing molybdenum (Mo) as a main component (composition ratio of 50% or more), or a material such as n-type silicon or silicide containing phosphorus. However, in the patterning of the first conductive film and the second conductive film, it is necessary to select a material having an etching selectivity.

  For example, as the first conductive film 104 / the second conductive film 105, n-type Si / Ta, n-type Si / Ta-Mo alloy, Ta / Al, Ti / Al, WN / W, TaN / Ta, etc. A combination can be selected. Another index for selecting a material is resistivity. It is desired that the second conductive film 105 be a material having as low a resistivity as possible, that is, a material having a lower sheet resistance than at least the first conductive film 104. This is because a contact is made between the second gate wiring and the upper wiring in order to connect the gate wiring and the upper wiring. The thickness of the first conductive film 104 is 10 to 400 nm, the thickness of the second conductive film is 10 to 400 nm, and the total thickness is 200 to 500 nm.

  Next, a resist mask 106 is formed over the second conductive film 105. The second conductive film 105 is etched using the resist mask 106 to form a second gate electrode 109. For the etching, isotropic wet etching may be used. In the case where an etching selectivity with the first conductive film 104 can be obtained, dry etching can be used. (Fig. 1 (C))

  Using the same resist mask 106, the first conductive film 104 is anisotropically etched (so-called tapered etching) to form a first gate electrode (first gate wiring) 108. In addition, a new resist mask can be formed for this etching.

  By this etching, as shown in FIG. 3, the taper angle θ between the side surface of the gate electrode 108 and the gate insulating film 103 is set to a value in the range of 3 degrees or more and 60 degrees or less. The taper angle θ is preferably in the range of 5 degrees or more and 45 degrees or less, and more preferably in the range of 7 degrees or more and 20 degrees or less. The smaller the angle θ is, the smaller the change in the thickness of the tapered portion of the gate electrode 108 is, and accordingly, the change in the n-type or p-type impurity concentration is moderated at the portion that intersects the tapered portion of the semiconductor layer. be able to.

  As shown in FIG. 3, the taper angle θ can be defined as tan θ = HG / WG using the width WG and the thickness HG of the tapered portion.

  The resist mask 106 is removed, and impurities of a predetermined conductivity type (n-type or p-type) are added to the semiconductor layer 102 using the gate electrodes 108 and 109 as a mask. As an addition method, an ion implantation method or an ion doping method can be used. The n-type impurity is an impurity serving as a donor, and is a Group 15 element for silicon and germanium, and is typically phosphorus (P) or arsenic (As). The p-type impurity is an impurity serving as an acceptor, and is a Group 13 element for silicon and germanium, and is typically boron (B).

Here, phosphorus is added by an ion doping method to form n ⁻ -type impurity regions 111 and 112. In this addition step, the concentration distribution of the n-type impurities in the n ⁻ -type second impurity regions 124 and 125 and the n ⁻ -type third impurity regions 126 and 127 is determined. In this specification, the term “n ⁻ type” means that the concentration of an impurity serving as a donor is lower and the sheet resistance is higher than that of an n ⁺ type. (Fig. 2 (A))

Since phosphorus is added to the n ⁻ -type impurity regions 111 and 112 through the tapered portion of the first gate electrode 108, the concentration gradient is as shown in FIG. To reflect changes. That is, when attention is paid to a depth at which an arbitrary concentration is obtained in the concentration distribution of phosphorus in the depth direction, the concentration gradient has a profile reflecting the inclination of the tapered portion of the gate electrode.

Further, as described later, the concentration gradient of the n ⁻ -type impurity regions 111 and 112 also depends on the acceleration voltage during doping. In the present invention, in order to allow phosphorus to pass through the tapered portion of the first gate electrode 108 and the insulating film 103, the doping acceleration voltage needs to be set as high as 40 to 100 keV. Further, with this acceleration voltage, phosphorus can pass through a portion where the thickness of the tapered portion of the gate electrode 108 is 100 nm or less.

In FIG. 2A, a region overlapping with the first gate electrode 108 in the n ⁻ -type impurity regions 111 and 112 is indicated by hatching and a white background. This is because phosphorus is added to the white background. This does not mean that the region is not formed, but as described above, it can be intuitively understood that the phosphorus concentration distribution in this region reflects the film thickness of the tapered portion of the first gate electrode 108. That's because This is the same in other drawings of this specification.

  Next, a resist mask 120 is formed to cover the gate electrodes 108 and 109. The length of the third impurity region is determined by the mask 120. Via the resist mask 120, phosphorus, which is an n-type impurity, is again added to the semiconductor layer 102 by an ion doping method. (FIG. 2 (B))

Phosphorus is selectively added to the n ⁻ -type impurity regions 111 and 112 that are not covered with the resist mask 120, so that n ⁺ -type first impurity regions 122 and 123 are formed. In addition, the region 121 covered with the second gate electrode 109 becomes a channel formation region because phosphorus is not added in the addition step of FIGS. 2A and 2B.

Further, in the n ⁻ -type impurity regions 111 and 112, regions to which phosphorus is not added in the adding step of FIG. 2B are low-concentration impurity regions 124 to 127 having higher resistance than the source / drain regions.

The low-concentration impurity regions 124 and 125 overlapping (overlapping) with the first gate electrode 108 are n ⁻ -type second impurity regions, and the low-concentration impurity regions not overlapping with the first electrode 108 are The n ⁻ -type third impurity regions 126 and 127 are formed.

  Note that before the addition step in FIG. 2B, the insulating film 103 may be etched using the gate wiring as a mask to partially expose the surface of the semiconductor layer 102.

  As shown in FIG. 4, the second impurity regions 124 can be classified into four types. FIG. 4 is divided into FIGS. 4 (A) to 4 (D) in order to distinguish between them, and ADs are attached to 121 and 124. Although not shown in FIG. 4, the other second impurity region 125 formed symmetrically with the gate electrode 109 interposed therebetween is similar to the region 124.

  As shown in FIG. 4A, the concentration of phosphorus in the second impurity region 124A is inversely proportional to the change in the thickness of the tapered portion of the first gate electrode 108, and the concentration of phosphorus in the third impurity region 126A It decreases almost linearly toward the channel forming region 121A. That is, when the phosphorus concentration of the second impurity region 124A is averaged in the depth direction, the averaged phosphorus concentration increases from the channel forming region 121A toward the third impurity region 126A.

  In this case, in the third impurity region 126A, the phosphorus concentration averaged in the thickness direction becomes substantially uniform in the region 126A. Further, since no phosphorus is added to the semiconductor layer covered by the second gate electrode 109, this region becomes the channel formation region 121A, and the channel length LA is equal to the width of the second gate electrode 109 in the channel length direction. Become.

  Further, in the case where the acceleration voltage is set higher than that in the case of FIG. 4A in the phosphorus addition step of FIG. 2A, the channel formation is performed in the second impurity region 124B as shown in FIG. 4B. Phosphorus is also added to the junction with the region 121B. Also in this case, the channel formation region 121B is a region covered with the second gate electrode 109, and the channel length LB is the width of the second gate electrode 109 in the channel length direction. Further, even when the acceleration voltage is the same as that in FIG. 4A, the second impurity region 124B can be formed even when the taper angle is small or the thickness of the tapered portion is small.

  When the acceleration voltage is further increased, as shown in FIG. 4C, in the second impurity region 124C, the phosphorus concentration averaged in the film thickness direction can be made uniform. In this case, the channel length LC is the width of the second gate electrode 109 in the channel length direction.

  When the accelerating voltage is set lower than that in the case of FIG. 4A in the phosphorus adding step of FIG. 2A, phosphorus is applied to the tapered portion of the first gate electrode 108 as shown in FIG. Since only the portion having a small thickness can be passed through, the second impurity region 124D becomes narrower than that in FIG.

   In the second impurity region 124D, the concentration of phosphorus averaged in the depth direction gradually decreases from the third impurity region 126D toward the channel formation region 121D as in FIG. However, in the case of FIG. 4D, unlike FIG. 4A, the junction between the second impurity region 124D and the channel formation region 121D exists below the tapered portion of the first gate electrode 108. For this reason, the channel length LD is wider than the width of the second gate electrode 109 in the channel length direction.

  Note that even when the acceleration voltage is the same as that in FIG. 4A, even when the taper angle is large or the thickness of the first gate electrode 108 is large, the second impurity region 124D in FIG. Can be formed.

  When the impurity is added by the plasma doping method as described above, the impurity may pass through a portion having a thickness of 100 nm or less in the tapered portion of the first gate electrode 108 to form the second impurity region 124. Therefore, by adjusting the thickness of the first conductive film 104 (the thickness of the portion where the thickness of the first gate electrode 108 is the largest) and the taper angle θ, the channel length and the second It is possible to control the length of the impurity region.

Here, the length (channel length direction) of the first impurity regions 122 and 123 is 2 to 20 μm (typically 3 to 10 μm). The concentration of an impurity (in this case, phosphorus) that imparts conductivity to the semiconductor layer is 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ (typically, 1 × 10 ^{20 to} 5 × 10 ²⁰ atoms / cm 3). ³ ). The first impurity regions 122 and 123 are low-resistance regions for electrically connecting a source wiring or a drain wiring to a TFT, and serve as a source region or a drain region.

The length of the second impurity regions 124 and 125 is 0.1 to 1 μm (typically 0.1 to 0.5 μm, preferably 0.1 to 0.2 μm), and the concentration of phosphorus is 1 ×. 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ (typically 5 × 10 ^{15 to} 5 × 10 ¹⁶ atoms / cm ³ , preferably 1 × 10 ¹⁶ to 2 × 10 ¹⁶ atoms / cm ³ ) Since the impurity is added through the first gate electrode 108, the concentration of phosphorus is lower than that of the first and third impurity regions.

The length of the third impurity regions 126 and 127 is 0.5 to 2 μm (typically 1 to 1.5 μm), and the concentration of phosphorus is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ³ ( Typically, it is 1 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ , preferably 5 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms / cm ³ ).

In addition, the channel formation region 121 is an intrinsic semiconductor layer, and a region containing no impurity (phosphorus) added to the first impurity region or boron at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ . It is the area that includes. Boron is an impurity for controlling the threshold voltage and for preventing punch-through, and other elements that can produce the same effect can be substituted with boron. In that case, the concentration is the same as that of boron.

   One low-concentration impurity region (third impurity regions 126 and 127) which does not overlap with the gate electrode is formed between the first impurity regions 122 and 123 and the second impurity regions 124 and 125. Two or more impurity regions having different impurity concentrations may be formed in the portion. In the present invention, an impurity region having a lower impurity (phosphorus) concentration than the first impurity regions 122 and 123, ie, the first impurity region, is provided between at least the first impurity regions 122 and 123 and the second impurity regions 124 and 125. It is sufficient that at least one impurity region having a higher resistance than the impurity regions 122 and 123 exists. Of course, it is also important that this high-resistance impurity region (third impurity region) does not overlap with the gate electrode.

  After forming the first impurity regions 122 and 123, the resist mask 120 is removed. By heat treatment, phosphorus added to the semiconductor layer 102 is activated. In the activation step, not only heat treatment but also light annealing using laser or infrared lamp light can be performed.

  Next, an interlayer insulating film 130 made of silicon oxide or the like is formed. In the gate insulating film 103 and the interlayer insulating film, contact holes reaching the first impurity regions 122 and 123 and the second gate wiring 109 are formed. Then, a source electrode 131, a drain electrode 132, and an extraction electrode for a gate wiring (not shown) are formed.

[Embodiment 2]
A manufacturing process of the TFT of the present embodiment will be described with reference to FIGS. This embodiment is a modification of the first embodiment, in which the structure of the gate electrode (gate wiring) is modified, and the other main structure is the same as that of the first embodiment.

  In the first embodiment, the gate electrode has a structure in which two gate electrodes having different widths are stacked. However, in the present embodiment, the upper second electrode is omitted and only the first gate electrode having a tapered portion is used. Form electrodes.

  First, a base film 141 is formed over the entire surface of the substrate 140, and an island-shaped semiconductor layer 142 is formed over the base film 141. An insulating film 143 serving as a gate insulating film is formed over the entire surface of the substrate 140 so as to cover the semiconductor layer 142. (FIG. 5 (A))

  A conductive film 144 forming a gate electrode (gate wiring) is formed over the gate insulating film 143. It is desired that the conductive film 144 be made of a material that can be easily tapered. For example, a material containing chromium (Cr) or tantalum (Ta) as a main component (composition ratio is 50% or more), and n-type silicon containing phosphorus are typically used. Alternatively, a material containing titanium (Ti), tungsten (W), molybdenum (Mo), or the like as a main component can be used. Further, not only a single-layer film of these materials but also a multilayer film can be used. For example, a three-layer film in which a tantalum film is sandwiched between tantalum nitride (TaN) films can be used. The thickness of the conductive film 144 is 200 to 500 nm. (FIG. 5 (B))

  Next, a resist mask 145 is formed over the conductive film 144. The conductive film 144 is etched using the mask 145 to form a gate electrode (gate wiring) 146. (FIG. 5 (C))

  By this etching, as shown in FIG. 3, the taper angle θ at which the side surface of the gate electrode 146 forms the gate insulating film has a value in the range of 3 degrees or more and 60 degrees or less. The taper angle θ is preferably 5 degrees or more and 45 degrees or less, and more preferably 7 degrees or more and 20 degrees or less.

In a state where the resist mask 145 is present, a predetermined conductivity type (n-type or p-type) impurity is added to the semiconductor layer 142. Here, phosphorus is added by an ion doping method to form n ⁻ -type impurity regions 148 and 149. In this adding step, n ^- the second impurity regions 154 and 155 of the mold, n ^- third concentration distribution of the impurity regions 156 and 157 of the mold is determined. As described later, a region covered with the resist mask 145 becomes a channel formation region 151. (FIG. 6 (A))

  Since the second gate electrode does not exist, this adding step requires a mask for preventing phosphorus from being added to a region of the semiconductor layer 142 where a channel is to be formed. Although the resist mask 145 used for etching the conductive film 144 is used as such a mask, it can be newly formed for adding an impurity.

  Next, the resist mask 145 is removed, and a resist mask 150 is formed to cover the gate electrode 146. Since phosphorus, which is an n-type impurity, is added to the semiconductor layer 142 again by the ion doping method via the resist mask 150, the length of the third impurity region is determined by the resist mask 150. Note that before the addition step, the insulating film 143 may be etched using the gate wiring 146 as a mask to expose the surface of the semiconductor layer 142. (FIG. 6 (B))

As shown in FIG. 6B, phosphorus is selectively added to n ⁻ -type impurity regions 148 and 149 which are not covered with resist mask 150, so that n ⁺ -type first impurity regions 152 and 153 are formed. Is done.

Further, the region covered with the resist mask 150 maintains the conductivity type and the resistance value as shown in FIG. Therefore, the region 151 previously covered with the resist mask 145 becomes a channel formation region. The region overlapping (overlapping) with the gate electrode 146 becomes the n ⁻ -type second impurity regions 154 and 155, and the region not overlapping with the gate electrode 146 becomes the n ⁻ -type third impurity regions 156 and 157. Become. The second and third impurity regions 154 to 157 are low-concentration impurity regions having higher resistance than the first impurity regions 152 and 153.

  Also in the present embodiment, the second impurity regions 154 and 155 can be classified into the four types shown in FIG. The length in the channel length direction and the impurity concentration of the channel formation region 151 and the first to third impurity regions 152 to 157 are the same as those in the first embodiment. However, the channel length is determined by the resist mask 145 used in the addition step of FIG. 6A in this embodiment instead of the second gate electrode 109 of the first embodiment.

  Since the gate electrode of Embodiment 1 has a laminated structure of electrodes having different shapes, even if the thickness of the first gate electrode 108 is reduced, the resistance can be reduced by increasing the thickness of the second gate electrode 109. However, since the gate electrode 146 of this embodiment is a single-layer electrode having a tapered portion, its thickness is larger than that of the first gate electrode 108.

  Since the length of the width WG (see FIG. 3) of the tapered portion is limited in consideration of the gate electrode width, the impurity concentration distribution of the second impurity regions 154 and 155 should be of the type shown in FIG. Is the most practical.

  One low-concentration impurity region (third impurity regions 156 and 157) that does not overlap with the gate electrode is formed between the first impurity regions 152 and 153 and the second impurity regions 154 and 155. Two or more impurity regions having different impurity concentrations may be formed in the portion. According to the present invention, an impurity region having a lower impurity (phosphorus) concentration and a higher resistance than the first impurity regions 152 and 153 is provided between at least the first impurity regions 152 and 153 and the second impurity regions 154 and 155. It is sufficient that at least one exists.

  After forming the first impurity regions 152 and 153, the resist mask 150 is removed. By heat treatment, phosphorus added to the semiconductor layer 142 is activated. In the activation step, not only heat treatment but also light annealing using laser or infrared lamp light can be performed. However, in order to activate phosphorus in the second impurity regions 154 and 155, heat treatment is necessarily required because the region overlaps with the gate electrode 146.

  Next, an interlayer insulating film 158 made of silicon oxide or the like is formed. In the gate insulating film 143 and the interlayer insulating film 158, contact holes reaching the first impurity regions 152 and 153 and the gate wiring 146 are formed. Then, a source electrode 159, a drain electrode 160, and an extraction electrode of a gate wiring 146 (not shown) are formed.

[Embodiment 3]
The manufacturing process of the TFT of this embodiment will be described with reference to FIGS. This embodiment is also a modification of the first embodiment, which is a modification of the structure of the gate electrode (gate wiring), and other main structures are the same as those of the first embodiment. In FIG. 7, the same reference numerals as those in FIGS. 1 and 2 indicate the same components.

  The gate electrode of the present embodiment has a structure in which a first gate electrode 168 and a second gate electrode 169 are stacked similarly to the first embodiment, but is an example in which the side surface of the first gate electrode 168 is not tapered. In the present embodiment, the film thickness is substantially constant even in the portion where the first gate electrode 168 extends outward from the side surface of the second gate electrode 169.

In the semiconductor layer, through the same addition of phosphorus as in the first embodiment, the channel formation region 161, the n ⁺ -type first impurity regions 162, 163, and the n ⁻ -type second impurity regions 164, 165, n ⁻ Third impurity regions 166 and 167 are formed.

  In the present embodiment, since the thickness of the first gate electrode 168 is constant, the impurity concentration in the second impurity regions 164 and 165 has almost no gradient.

[Embodiment 4]
This embodiment is a modification of the first and second embodiments. In the first and second embodiments, the thickness of the gate electrode at the tapered portion changes almost linearly. In the present embodiment, the thickness of the tapered portion is changed non-linearly.

FIG. 8 shows a modification of the TFT of the first embodiment. 8, the same reference numerals as those in FIG. 2 denote the same components. As shown in FIG. 8, the thickness of the tapered portion of the first gate electrode 170 (gate wiring) is changed nonlinearly. In the semiconductor layer, the channel formation region 171, the n ⁺ -type first impurity regions 172 and 173, and the n ⁻ -type second impurity regions 174, 175 and n ⁻ Third impurity regions 176 and 177 are formed.

FIG. 9 shows a modification of the TFT of the second embodiment. In FIG. 9, the same reference numerals as those in FIG. 6 indicate the same components. As shown in FIG. 9, the thickness of the tapered portion of the gate electrode 180 (wiring) changes nonlinearly. The semiconductor layer is doped with phosphorus in the same manner as in the first embodiment, and the channel formation region 181, the n ⁺ -type first impurity regions 182 and 183, and the n ⁻ -type second impurity regions 184, 185, and n ^{− are} added. Third impurity regions 186 and 187 are formed.

  As shown in the cross-sectional views of FIGS. 8 and 9, the gate electrodes 170 and 180 are formed such that the thickness becomes extremely thin at a portion where the film thickness is slightly shifted from a fixed portion to an end, so that impurities serving as donors and acceptors are removed. It easily passes through the gate electrodes 170 and 180.

  In order to form the tapered portions as shown in the gate electrodes 170 and 180, the conductive film may be etched by a combination of anisotropic etching and isotropic etching.

  Needless to say, the configuration of the TFT described in the first to fourth embodiments can be applied to all the examples of the present invention described below.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Example 1]
In this embodiment, an example in which the present invention is applied to an active matrix type liquid crystal display device will be described.

  FIG. 10 is a schematic configuration diagram of the active matrix type liquid crystal panel of the present embodiment. A liquid crystal panel has a structure in which liquid crystal is sandwiched between an active matrix substrate and a counter substrate, and a voltage corresponding to video data is applied to the liquid crystal by electrodes formed on the active matrix substrate and the counter substrate. , Can display video on the panel.

  In the active matrix substrate 200, a pixel portion 202 using a TFT as a switching element, a gate driver circuit 203 for driving the pixel portion 202, and a source driver circuit 204 are formed over a glass substrate 300. The driver circuits 203 and 204 are connected to the pixel unit 202 by a source wiring and a drain wiring, respectively.

  Further, on the glass substrate 300, a signal processing circuit 205 for processing signals input to the driver circuits 203 and 204 is formed, and further for inputting power and control signals to the driver circuits 203 and 204 and the signal processing circuit 205. Are formed, and the FPC 206 is connected to this external terminal.

  In the counter substrate 210, a transparent conductive film such as an ITO film is formed on the entire surface of the glass substrate. The transparent conductive film is a counter electrode to the pixel electrode of the pixel portion 202. By changing the electric field strength between the pixel electrode and the counter electrode, the orientation of the liquid crystal material is changed, and gray scale display can be performed. Further, an alignment film and a color filter are formed on the counter substrate 210 if necessary.

  FIG. 11A is an equivalent circuit of one pixel of the pixel portion, and FIG. 11B is a top view of the pixel portion 202. FIG. 11C is a top view of a CMOS circuit included in the driver circuits 203 and 204.

  The pixel portion 202 includes a pixel TFT 220 and a storage capacitor 230, and a cross-sectional view thereof corresponds to a cross section taken along a dashed line X-X 'in FIG. The CMOS circuit has an n-channel TFT and a p-channel TFT, and a cross-sectional view thereof corresponds to a cross section taken along a chain line Y-Y 'in FIG. The pixel TFT 220 and the thin film transistor of the CMOS circuit are simultaneously formed on the same glass substrate 300.

  In the pixel portion 202, a gate wiring 350 is formed for each row, and a source wiring 380 is formed for each column. The pixel TFT 220 is formed near the intersection of the gate line 350 and the source line 380. The source region of the pixel TFT 220 is connected to a source line 380, and the drain region is connected to two capacitors, a liquid crystal cell 240 and a storage capacitor 230. (FIG. 11A)

  The liquid crystal cell 240 is a capacitor using liquid crystal as a dielectric with the pixel electrode 390 and the transparent electrode of the counter substrate 210 as an electrode pair, and is electrically connected to the pixel TFT 220 by the pixel electrode 390. The storage capacitor 230 is a capacitor using a common line 360 and a channel region formed in the semiconductor layer of the pixel TFT 220 as an electrode pair and a gate insulating film as a dielectric.

  The manufacturing process of the active matrix substrate of this embodiment will be described with reference to FIGS. 13 and 14 are cross-sectional views illustrating a process for manufacturing a pixel portion. FIGS. 15 and 16 are cross-sectional views illustrating a process for manufacturing a CMOS circuit.

  A glass substrate 300 is prepared. In this embodiment, a 1737 glass substrate manufactured by Cornings Incorporated is used. In contact with the surface of the glass substrate 300, a 200-nm-thick silicon oxide film is formed as a base film 301 by using a TEOS gas as a raw material by a plasma CVD method. Then, the base film 301 is heated at 400 ° C. for 4 hours.

An amorphous silicon film having a thickness of 500 nm is formed over the base film 301 using SiH ₄ diluted with H ₂ gas by a PECVD method. Next, the amorphous silicon film is heated at 450 ° C. for one hour to perform a dehydration treatment. The amount of hydrogen atoms in the amorphous silicon film is 5 atomic% or less, preferably 1% or less. The crystalline (polycrystalline) silicon film 401 is formed by irradiating an excimer laser beam to the amorphous silicon film after the hydrogen removal treatment. The conditions for laser crystallization are as follows: a XeCl excimer laser is used as a laser light source, the laser light is linearly shaped by an optical system, the pulse frequency is 30 Hz, the overlap ratio is 96%, and the laser energy density is 359 mJ / cm ² . . (FIG. 13 (A), FIG. 15 (A))

  As a method for forming the amorphous silicon film, an LPCVD method or a sputtering method can be used in addition to the PECVD method. As a laser for crystallizing amorphous silicon, a continuous wave laser such as an Ar laser may be used in addition to a pulsed laser such as an excimer laser. Further, instead of laser crystallization, a lamp annealing step using a halogen lamp or a mercury lamp, or a heat treatment step at 600 ° C. or higher can be used.

Next, a photoresist pattern (not shown) is formed by using a photolithography process, and the crystalline silicon film 401 is patterned into an island shape using the photoresist pattern to form semiconductor layers 302, 303, and 304. A silicon nitride oxide film is formed as the gate insulating film 305 so as to cover the semiconductor layers 302, 303, and 304. The film formation method was PECVD, and SiH ₄ and NO ₂ were used as source gases. The thickness of the silicon nitride oxide film is 120 nm. (FIG. 13 (B), FIG. 15 (B))

  A stacked film of a phosphorus-containing n-type silicon film 402 and a molybdenum-tungsten alloy (Mo-W) film 403 is formed over the gate insulating film 305 by a sputtering method. The thickness of the silicon film 402 is 200 nm, and the thickness of the Mo-W film 403 is 250 nm. The target material of the Mo—W film 403 had a Mo: W composition ratio of 1: 1. (FIG. 13 (C), FIG. 15 (C))

  A resist mask 405 is formed over the Mo-W film 403. The Mo—W film 403 is wet-etched using the resist mask 405 to form a second gate wiring 352, a second common wiring 362, which is an upper wiring of the gate wiring of the pixel TFT, the common wiring, and the gate wiring of the CMOS circuit. Two gate wirings 372 are formed. (FIG. 13 (D), FIG. 15 (D))

  Using the resist mask 405 again, anisotropic etching using a chlorine-based gas is performed to etch the n-type silicon film 402, and the first gate wiring 351, the second common wiring 361, the first gate wiring 371 is formed. At this time, the angle (taper angle) θ between the side surface of each of the wirings 351, 361, and 371 and the gate insulating film 305 is set to 20 degrees, and a tapered portion is formed on the side. (FIG. 13E, FIG. 15E)

After removing the resist mask 405, phosphorus is added to the semiconductor layers 302 to 304 by ion doping using the wirings 350, 360, and 370 as masks to form n ⁻ -type regions 406 to 413 in a self-aligned manner. In the phosphorus addition step, phosphorus is passed through the tapered portions of the first electrodes 351, 361, 371 (portions outside the side surfaces of the second electrodes 352, 362, 372) and the gate insulating film 305, and For the addition, the acceleration voltage is increased to 90 KeV.

n ^- To determine the phosphorus concentration of the low concentration impurity regions of the mold, and the dose is set to a low concentration, n ^{- -} phosphorus concentration impurity regions 406 to 413 of the types n of the final TFT in type impurity regions 406 to 413 The concentration of phosphorus in a region not intersecting with the electrodes 350, 360, and 370 was set to 1 × 10 ¹⁸ atoms / cm ³ . Phosphine diluted with hydrogen is used as a doping gas.

Next, a resist mask 415 covering the electrodes 350, 360, and 370 is formed. The length of the resist mask 415 extending outside the side surfaces of the first electrodes 351, 361, 371 of each electrode causes the n ⁻ -type low-concentration impurity regions that do not overlap with the first electrodes 351, 361, 371. The length is determined. Here, no resist mask is formed over the semiconductor layer 304 of the CMOS circuit.

Using the resist mask 415, phosphorus is added by an ion doping method. In this addition step, phosphine diluted with hydrogen was used as the doping gas. Further, in order to allow phosphorus to pass through the gate insulating film 305, the acceleration voltage is set to be as high as 80 keV, and the n ⁺ -type impurity regions 313 to 315, 332, 333, 421, and 422 formed in this step are formed. The dose was set such that the phosphorus concentration was 5 × 10 ²⁰ atoms / cm ³ .

In the pixel portion 202, phosphorus is selectively added to the n ⁻ -type impurity regions 406 to 409 of the semiconductor layer 302 to form n ⁺ -type impurity regions 313 to 315. The regions to which phosphorus is not added in the n ⁻ -type impurity regions 406 to 409 function as high-resistance regions, and the n ⁻ -type impurity regions 316 to 319 overlapping with the first gate electrode 351 and the first common electrode are formed. 326, 327 and n ⁻ -type impurity regions 320 to 323, 328 which do not overlap with the first gate electrode 351 and the first common electrode 361. Further, regions 311, 312, and 325 to which phosphorus has not been added in the two phosphorus addition steps are defined as channel formation regions. (FIG. 14A)

The n ⁻ -type impurity regions 316 to 319 have a lower phosphorus concentration than the n ⁻ -type impurity regions 320 to 323, and the phosphorus concentration decreases from the n ⁻ -type impurity regions 320 to 323 toward the channel forming regions 311 and 312. I have.

In the CMOS circuit, phosphorus is also selectively added to the n ⁻ -type impurity regions 410 and 411 of the semiconductor layer 303 of the n-channel TFT, so that n ⁺ -type impurity regions 322 and 323 are formed. On the other hand, in the n ⁻ -type impurity regions 410 and 411, regions to which phosphorus is not added function as high-resistance regions, and the n ⁻ -type impurity regions 334 and 335 overlapping the first gate electrode 371 and the first Are defined as n ⁻ type impurity regions 336 and 337 which do not overlap with the gate electrode 371 of FIG. The region 331 to which phosphorus has not been added in the two phosphorus addition steps is defined as a channel formation region.

The n ⁻ -type impurity regions 334 and 335 have a lower phosphorus concentration than the n ⁻ -type impurity regions 336 and 337, and the phosphorus concentration decreases from the n ⁻ -type impurity regions 336 and 337 toward the channel formation region 331.

Further, in the semiconductor layer 304 of the p-channel TFT, phosphorus is hardly added to a portion where the gate electrode 370 exists, and n ⁺ -type regions 421 and 422 are formed in a portion where the gate electrode 370 does not exist. Thus, an n ⁻ -type impurity region remains below the first gate electrode 371. (FIG. 16A)

  After removing the resist mask 415, a resist mask 416 covering the n-channel TFT is formed. Using the second gate electrode 372 of the p-channel TFT as a mask, the first gate electrode 371 on the semiconductor layer 304 side is thinned by etching to form a third gate electrode 373. (FIG. 14 (B), FIG. 16 (B))

  The taper angle θ between the side surface of the third gate electrode 373 and the gate insulating film 305 was 75 degrees. The taper angle of the third electrode 373 is in a range of 60 degrees or more and 90 degrees or less, and more preferably in a range of 70 degrees or more and 85 degrees or less.

With the resist mask 416 remaining, boron is added to the semiconductor layer 304 by an ion doping method. The gate electrode 372 and 373 functions as a mask, a channel forming region 341, p ⁺ -type impurity regions 342 and 343, p ⁺ -type impurity regions 344 and 345 are formed in a self-aligned manner. Note that the resist mask 416 may be removed and a new resist mask may be formed separately. (FIG. 14 (C), FIG. 16 (C))

In the boron addition step, the acceleration voltage was set to 80 keV, and the dose was set so that the boron concentration of the p ⁺ -type impurity regions 342 to 345 was 3 × 10 ²¹ atoms / cm ³ . By using diborane diluted with hydrogen in the doping gas, although the p ⁺ -type impurity regions 344 and 345 p ⁺ -type impurity regions 342 and 343 and the boron concentration is the same, the phosphorus concentration is low. The concentration distribution of the p ⁺ -type impurity regions 344 and 345 decreases toward the channel formation region 341 in accordance with the change in the thickness of the tapered portion of the first gate electrode 371.

  After removing the resist mask 416, the semiconductor layer is heated at 500 ° C. to activate phosphorus and boron added to the semiconductor layer. Prior to the heat treatment, a protective film 306 made of silicon oxide with a thickness of 50 nm is formed in order to prevent oxidation of the gate wiring 350, the common electrode 360, and the gate wiring 370. (FIG. 14 (D), FIG. 16 (D))

Next, as the interlayer insulating film 307, a 20-nm-thick silicon nitride film and a 900-nm-thick silicon oxide film are stacked by a PECVD method. Contacts reaching the n ⁺ -type impurity regions 313 to 315, the n ⁺ -type impurity regions 332 and 333, the p ⁺ -type impurity regions 342 and 343, and the second gate wiring 372 in the interlayer insulating film 307, the protective film 306, and the gate insulating film 305. Form a hole.

  On the interlayer insulating film 307, a stacked film of titanium (150 nm) / aluminum (500 nm) / titanium (100 nm) is formed by a sputtering method and patterned, and the source wiring 380, the drain electrode 381, the source electrodes 384, 385, A drain electrode 386 is formed. As described above, the circuits 203 to 205 mainly including a CMOS circuit and the pixel portion 202 provided with the pixel TFT 220 and the storage capacitor 230 are manufactured over the same glass substrate 300. (FIG. 14 (E), FIG. 16 (E))

  To complete the active matrix substrate, a flattening film is further formed on the entire surface of the substrate 300. Here, acryl is applied by a spin coating method and baked to form an acrylic film having a thickness of 1 μm. Contact holes for the source electrodes 384 and 385 of the CMOS circuit are opened in the flattening film. A 200-nm-thick titanium film is formed by sputtering and patterned to form source wirings 387 and 388.

  Next, similarly to the first planarizing film, an acrylic having a thickness of 0.5 μm is formed as a second planarizing film. A contact hole for the drain electrode 381 is formed in the first and second planarization films. An ITO film is formed by a sputtering method and is patterned to form a pixel electrode 390 connected to the drain electrode 381. (FIGS. 11B and 11C)

  In this embodiment, a low-concentration impurity region functioning as a high-resistance region is not formed with respect to the p-channel TFT, but there is no problem because the p-channel TFT has high reliability even without the high-resistance region originally. On the contrary, when the high resistance region is not formed, the ON current can be increased, and the characteristics with the n-channel TFT can be balanced, which is convenient.

[Example 2]
This embodiment is a modification of the first embodiment, except that the order of the steps of adding phosphorus and boron is changed, and the rest is the same as the first embodiment. The manufacturing process of this embodiment will be described with reference to FIGS. In FIG. 17, the same reference numerals as those in FIGS. 15 and 16 denote the same components.

  In Example 1, boron was added after phosphorus was added to the semiconductor layer, but in this example, boron is added first.

  In this embodiment, a process for manufacturing a CMOS circuit will be described. However, it goes without saying that this embodiment can be applied to a process for manufacturing an active matrix substrate in which a pixel portion and a driver circuit are integrated as in the embodiment.

  The structure in FIG. 15E is obtained according to the steps described in the first embodiment. Next, the resist mask 405 is removed. FIG. 17A shows this state.

  Next, a resist mask 451 covering the n-channel TFT is formed. Using the resist mask 451, boron is added to the semiconductor layer 304 by an ion doping method. The gate electrodes 371 and 372 function as masks, and the channel formation region 501 and p + -type impurity regions 502 and 503 functioning as source and drain regions are formed in the semiconductor layer 304 in a self-aligned manner.

The acceleration voltage was set to 80 keV, and the dose was set so that the boron concentration of the p ⁺ -type impurity regions 502 and 503 was 3 × 10 ²⁰ atoms / cm ³ . Here, the p ⁺ -type impurity regions 502 and 503 are expected to wrap around boron at the time of doping and have a small thickness on the side of the gate electrode 370, so that they slightly overlap with the lower portion. (FIG. 17B)

After removing the resist mask 451, a resist mask 452 covering the p-channel TFT is formed. Then, phosphorus is added to the semiconductor layer 303 by an ion doping method to form n ⁻ -type low-concentration impurity regions 453 and 454 in a self-aligned manner. The acceleration voltage was set to 90 keV, and the dose was set so that the phosphorus concentration of the n ⁻ -type impurity regions 453 and 454 was 1 × 10 ¹⁸ atoms / cm ³ . In addition, phosphine diluted with hydrogen is used as a doping gas. (FIG. 17C)

Next, the resist mask 452 is removed, and a resist mask 456 covering the entire p-channel TFT and partially covering the n-channel TFT is newly formed. In the n-channel TFT, the length of the mask 456 extending outside the side surface of the first gate electrode 371 determines the length of the n ⁻ -type impurity region which does not overlap with the first gate electrode 371.

  Using a resist mask 456, phosphorus is added by an ion doping method. In this addition step, phosphine diluted with hydrogen was used as the doping gas.

In the CMOS circuit, phosphorus is selectively added to the n ⁻ -type impurity regions 453 and 454 of the semiconductor layer 303 of the n-channel TFT, so that n ⁺ -type impurity regions 512 and 513 are formed. In this step, in order to allow phosphorus to pass through the gate insulating film 305, the acceleration voltage is set to be as high as 80 keV. The dose was set such that the concentration of phosphorus in n ⁺ -type impurity regions 512 and 513 was 5 × 10 ²⁰ atoms / cm ³ .

On the other hand, in the n ⁻ -type impurity regions 453 and 454, the regions to which phosphorus is not added function as high-resistance regions, and the n ⁻ -type impurity regions 514 and 515 overlapping the first gate electrode 371 and the first Are defined as n ⁻ -type impurity regions 516 and 517 not overlapping with the gate electrode 371 of FIG. In addition, the region 511 where phosphorus has not been added in the two phosphorus addition steps is defined as a channel formation region. (FIG. 17D)

Also in this embodiment, the n ⁻ -type impurity regions 514 and 515 overlapping the gate electrode 371 have a lower phosphorus concentration than the n ⁻ -type impurity regions 516 and 517 (and the n ⁺ -type impurity regions 512 and 513), and The concentration decreases toward the channel formation region 511.

  After removing the resist mask 456, a protective film 306 made of silicon oxide having a thickness of 50 nm is formed, and heat treatment is performed to activate phosphorus and boron added to the semiconductor layer. An interlayer insulating film 307 is formed, a contact hole is opened, and a source electrode 384, 385 and a drain electrode 386 are formed. Thus, a CMOS circuit is manufactured. (FIG. 17E)

  In this embodiment, the step of narrowing the first gate electrode of the p-channel TFT can be omitted. Note that before performing the boron addition step of FIG. 17B, the first gate electrode 371 of the p-channel TFT is etched using the second gate electrode 372 as a mask, and the third gate electrode 373 is formed. A forming step can be added.

[Example 3]
In this embodiment, as in Embodiment 2, a manufacturing process in which the order of adding phosphorus and boron is changed will be described. The manufacturing process of this embodiment will be described with reference to FIGS. In FIG. 18, the same reference numerals as those in FIGS. 15 and 16 indicate the same components.

  This embodiment also corresponds to a modification of the second embodiment. In the second embodiment, an n-channel TFT is manufactured by adding phosphorus at a low concentration and then adding boron. In the present embodiment, an example in which boron is added at a high concentration first. It is.

  The structure in FIG. 15E is obtained according to the steps described in the first embodiment. Next, the resist mask 405 is removed. FIG. 18A shows this state.

Next, a resist mask 600 covering the n-channel TFT is formed. Using the resist mask 600, boron is added to the semiconductor layer 304 by an ion doping method. The gate electrodes 371 and 372 function as masks, and the channel formation region 601 and p ⁺ -type impurity regions 602 and 603 functioning as source and drain regions are formed in the semiconductor layer 304 in a self-aligned manner. The doping acceleration voltage was set to 80 keV, and the dose was set so that the boron concentration of the p ⁺ -type impurity regions 602 and 603 was 2 × 10 ²⁰ atoms / cm ³ .

A resist mask 605 that partially covers the entire p-channel TFT and the n-channel TFT is formed. Using the resist mask 605, phosphorus is added by an ion doping method. In this addition step, phosphine diluted with hydrogen was used as the doping gas. Phosphorus is selectively added to the semiconductor layer 303 of the n-channel TFT, and n ⁺ -type impurity regions 606 and 607 are formed. Further, in this step, since the phosphorus is passed through the gate insulating film 305, the acceleration voltage is increased. Increase to 80 keV. (FIG. 18 (C))

After removing the resist mask 605, a resist mask 608 that covers the p-channel TFT is formed. Then, phosphorus is added to the semiconductor layer 303 by an ion doping method. Gate electrode 370 functions as a mask, and channel formation region 611, n ⁻ -type impurity regions 614 and 615, and n ⁻ -type impurity regions 616 and 617 are formed in a self-aligned manner.

The n ⁺ -type impurity regions 612 and 613 function as source / drain regions and reduce the resistance so that the phosphorus concentration becomes 5 × 10 ²⁰ atoms / cm ³ . The n ⁻ -type impurity regions 614 to 617 have a lower phosphorus concentration and higher resistance than the n ⁺ -type impurity regions 612 and 613. The phosphorus concentration of n ⁻ -type impurity regions 616 and 617 not overlapping with first gate electrode 371 is set to 1 × 10 ¹⁸ atoms / cm ³ . (FIG. 18D)

  After removing the resist mask 608, a protective film 306 made of silicon oxide with a thickness of 50 nm is formed, and heat treatment is performed to activate phosphorus and boron added to the semiconductor layer. An interlayer insulating film 307 is formed, a contact hole is opened, and a source electrode 384, 385 and a drain electrode 386 are formed. Thus, a CMOS circuit is manufactured. (FIG. 18E)

  In this embodiment, the resist masks 605 and 608 covering the p-channel TFT are formed in the step of adding phosphorus, but these resist masks 605 and / or 608 can be omitted. In this case, since phosphorus is added to the p + -type impurity regions 602 and 603, it is necessary to add a large amount of boron in consideration of the concentration of phosphorus to be added.

[Example 4]
This embodiment is also a modification of the first embodiment, in which the order of the steps of adding phosphorus and boron is changed, and the main configuration is the same as that of the first embodiment.

  The manufacturing process of this embodiment will be described with reference to FIGS. 19, the same reference numerals as those in FIGS. 15 and 16 indicate the same components.

  The structure in FIG. 15E is obtained according to the steps described in the first embodiment. Next, the resist mask 405 is removed. Then, in the gate wiring 370, a resist mask which covers at least a portion functioning as a gate electrode of the n-channel TFT is formed, and the first gate electrode (wiring) is formed using the second gate electrode (wiring) 372 as an etching mask. ) Etch 371 to form a third gate electrode (wiring).

  That is, the width of at least a portion of the first gate wiring 371 overlapping with the semiconductor layer 304 of the p-channel TFT is reduced to form the third gate electrode 373. (FIG. 19A)

Phosphorus is added to the semiconductor layers 303 and 304 at a low concentration by an ion doping method. The first to third gate electrodes 371 to 373 function as masks, and n ⁻ -type regions 621 to 624 are formed in a self-aligned manner. (FIG. 19B)

Next, a resist mask 630 covering the n-channel TFT is formed. Using the resist mask 630, boron is added to the semiconductor layer 304 at a high concentration by an ion doping method. The first and third gate electrodes 371 and 373 function as a mask, and p ⁺ -type impurity regions 632 and 633 functioning as a channel formation region 631, a source region, and a drain region are formed in the semiconductor layer 304 in a self-aligned manner. . (FIG. 19C)

Next, the resist mask 630 is removed, and a new resist mask 640 that partially covers the entire p-channel TFT and the n-channel TFT is formed. Using the resist mask 640, phosphorus is added at a high concentration by an ion doping method. Phosphorus is selectively added to the n ⁻ -type impurity regions 621 and 622 of the semiconductor layer 303 of the n-channel TFT, so that n ⁺ -type impurity regions 642 and 643 are formed. Further, a region covered with the resist mask 640 includes n ⁻ -type impurity regions 644 and 645 overlapping with the channel formation region 641 and the first gate electrode 371, and n ⁻ not overlapping with the first gate electrode 371. Are defined as type impurity regions 646 and 647. (FIG. 19D)

Also in this embodiment, the n ⁻ -type impurity regions 644 and 645 overlapping the gate electrode 371 have a lower phosphorus concentration than the n ⁻ -type impurity regions 646 and 647 (and the n ⁺ -type impurity regions 642 and 643). The concentration decreases toward the channel formation region 641.

  After removing the resist mask 640, a protective film 306 made of silicon oxide with a thickness of 50 nm is formed, and heat treatment is performed to activate phosphorus and boron added to the semiconductor layer. An interlayer insulating film 307 is formed, a contact hole is opened, and a source electrode 384, 385 and a drain electrode 386 are formed. Thus, a CMOS circuit is manufactured. (FIG. 19E)

  Further, in the present embodiment, the width of the first gate electrode of the p-channel TFT is reduced, but this step can be omitted.

In the present embodiment, in the step of adding phosphorus, the resist masks 630 and 640 covering the p-channel TFT are formed, but these resist masks 630 and / or 640 may be omitted. In this case, since phosphorus is added to the p ⁺ -type impurity regions 632 and 633, it is necessary to add a large amount of boron in consideration of the added phosphorus concentration.

[Example 5]
This embodiment is a modification of the first embodiment, in which the order of the steps of adding phosphorus and boron is changed. The main configuration is the same as that of the first embodiment.

  The manufacturing process of this embodiment will be described with reference to FIGS. 20, the same reference numerals as those in FIGS. 15 and 16 indicate the same components.

  This embodiment corresponds to a modification of the fourth embodiment, and the third gate electrode 373 is formed by narrowing the first gate electrode of the p-channel TFT as in the fourth embodiment. (FIG. 20A)

  Next, a resist mask 650 that partially covers the entire p-channel TFT and the n-channel TFT is formed. Using the resist mask 650, phosphorus is added at a high concentration by an ion doping method to form n-type regions 651 and 652. (FIG. 20 (B))

Next, a resist mask 660 covering the n-channel TFT is formed. Using the resist mask 660, boron is added to the semiconductor layer 304 at a high concentration by an ion doping method. The first and third gate electrodes 371 and 373 function as masks, and channel formation regions 661 and p ⁺ -type impurity regions 662 and 663 that function as source and drain regions are formed in the semiconductor layer 304 in a self-aligned manner. . (FIG. 20 (C))

  Next, the resist mask 660 is removed, and a new resist mask 670 covering the entire p-channel TFT is formed. Phosphorus is added at a low concentration by an ion doping method, and the acceleration voltage is set as high as 90 keV so that the phosphorus passes through the tapered portion of the first gate electrode 371.

As a result, in the semiconductor layer 303 of the n-channel TFT, the channel formation region 671, the n ⁺ -type impurity regions 672 and 673, the n ⁻ -type impurity regions 674 and 675 overlapping with the first gate electrode 371, and the first N ⁻ -type impurity regions 676 and 677 not overlapping with the gate electrode 371 are formed in a self-aligned manner. (FIG. 20 (D))

  After removing the resist mask 670, a protective film 306 made of silicon oxide having a thickness of 50 nm is formed, and heat treatment is performed to activate phosphorus and boron added to the semiconductor layer. An interlayer insulating film 307 is formed, a contact hole is opened, and a source electrode 384, 385 and a drain electrode 386 are formed. Thus, a CMOS circuit is manufactured. (FIG. 20 (E))

  Further, in the present embodiment, the width of the first gate electrode of the p-channel TFT is reduced, but this step can be omitted.

In this embodiment, the resist masks 650 and 670 covering the p-channel TFT are formed in the step of adding phosphorus, but these resist masks 650 and / or 670 can be omitted. In this case, since phosphorus is added to the p ⁺ -type impurity regions 662 and 663, it is necessary to add a large amount of boron in consideration of the concentration of phosphorus to be added.

[Example 6]
This embodiment is a modification of the first embodiment, in which the order of the steps of adding phosphorus and boron is changed, and the other configuration is almost the same as that of the first embodiment.

  Hereinafter, the manufacturing process of this embodiment will be described with reference to FIGS. 21, the same reference numerals as those in FIGS. 15 and 16 indicate the same components.

  This embodiment corresponds to a modification of the fifth embodiment, and the third gate electrode 373 is formed by narrowing the first gate electrode of the p-channel TFT as in the fifth embodiment. (FIG. 21A)

  Further, similarly to the fifth embodiment, a resist mask 680 that partially covers the entire p-channel TFT and the n-channel TFT is formed. Using the resist mask 680, phosphorus is added at a high concentration by an ion doping method to form n-type regions 681 and 682. (FIG. 21 (B))

  Next, the resist mask 680 is removed, and a new resist mask 690 covering the entire p-channel TFT is formed. Phosphorus is added at a low concentration by an ion doping method. The acceleration voltage is set as high as 90 keV so that phosphorus passes through the tapered portion of the first gate electrode 371.

As a result, in the semiconductor layer 303 of the n-channel TFT, n ⁻ -type impurity regions 694 and 675 overlapping with the channel formation region 691, n ⁺ -type impurity regions 692 and 693, and the first gate electrode 371, N ⁻ -type impurity regions 696 and 697 which do not overlap with the gate electrode 371 are formed in a self-aligned manner. (FIG. 21 (C))

Next, after forming a resist mask 700 covering the entire n-channel TFT, boron is added to the semiconductor layer 304 at a high concentration by an ion doping method. The first and third gate electrodes 371 and 373 function as a mask, and p ⁺ -type impurity regions 702 and 703 functioning as a channel formation region 701 and a source region and a drain region are formed in the semiconductor layer 304 in a self-aligned manner. . (FIG. 21D)

  After removing the resist mask 700, a protective film 306 made of silicon oxide having a thickness of 50 nm is formed, and heat treatment is performed to activate phosphorus and boron added to the semiconductor layer. An interlayer insulating film 307 is formed, a contact hole is opened, and a source electrode 384 and a drain electrode 386 are formed. Thus, a CMOS circuit is manufactured. (FIG. 21 (E))

  Further, in the present embodiment, the width of the first gate electrode of the p-channel TFT is reduced, but this step can be omitted.

In the present embodiment, in the step of adding phosphorus, the resist masks 680 and 690 covering the p-channel TFT are formed, but these resist masks 680 and / or 690 can be omitted. In this case, since phosphorus is added to the p ⁺ -type impurity regions 702 and 703, it is necessary to add a large amount of boron in consideration of the added phosphorus concentration.

  As described above, the manufacturing steps of the CMOS circuit are described in Embodiments 2 to 6. However, the present embodiment can be applied to the manufacturing step of the active matrix substrate in which the pixel portion and the driver circuit are integrated as in Embodiment 1. Needless to say.

[Example 7]
In this embodiment, an example of a gate electrode having a tapered portion and a method for forming the gate electrode described in Embodiment 1 and the like will be described.

  First, a gate insulating film made of a silicon nitride oxide film was formed, and a metal laminated film was formed thereover by a sputtering method. In this embodiment, a tungsten target having a purity of 6N or more was used. In addition, a single gas such as argon (Ar), krypton (Kr), xenon (Xe), or a mixed gas thereof may be used as a sputtering gas. The film forming conditions such as sputtering power, gas pressure, and substrate temperature may be appropriately controlled by an operator. The metal laminated film has a tungsten nitride film represented by WNx (where 0 <x <1) as a lower layer and a tungsten film as an upper layer.

The metal laminated film thus obtained contains almost no impurity elements, particularly the oxygen content can be 30 ppm or less, and the electric resistivity is 20 μΩ · cm or less, typically, 6 μ to 15 μΩ. Cm. Further, the stress of the film can be set to −5 × 10 ^{9 to} 5 × 10 ⁹ dyn / cm ² .

  Note that the silicon oxynitride film is an insulating film represented by SiOxNy and refers to an insulating film containing silicon, oxygen, and nitrogen at a predetermined ratio.

  Next, a resist mask pattern (film thickness: 1.5 μm) for obtaining a desired gate wiring pattern is formed.

  Next, in this example, etching was performed using an ICP (Inductively Coupled Plasma) etching apparatus using high-density plasma for patterning of the metal laminated film to form a gate electrode and a gate electrode having a tapered cross section. .

  Here, the plasma generation mechanism of the ICP dry etching apparatus will be described in detail with reference to FIG.

  FIG. 22 shows a simplified structural diagram of the etching chamber. An antenna coil 12 is arranged on a quartz plate 11 above the chamber, and is connected to an RF power source 14 via a matching box 13. Further, an RF power supply 17 is also connected to the lower electrode 15 on the substrate side, which is disposed opposite thereto, via a matching box 16.

  When an RF current is applied to the antenna coil 12 above the substrate, an RF current J flows through the antenna coil 12 in the α direction, and a magnetic field B is generated in the Z direction. The relationship between the current J and the magnetic field B follows the following equation.

μ ₀ J = rotB (μ ₀ is magnetic susceptibility)

  According to Faraday's law of electromagnetic induction represented by the following equation, an induced electric field E is generated in the α direction.

  -∂B / ∂t = rotE

  The electrons are accelerated in the α-direction by the induction electric field E and collide with gas molecules to generate plasma. Since the direction of the induced electric field is the α direction, the probability that charged particles collide with the etching chamber wall or the substrate and lose charge is reduced. Therefore, high-density plasma can be generated even at a low pressure of about 1 Pa. Further, since there is almost no magnetic field B downstream, a high-density plasma region spread in a sheet shape is formed.

  Independent control of plasma density and self-bias voltage by adjusting RF power applied to each of antenna coil 12 (to which ICP power is applied) and lower electrode 15 (to which bias power is applied) on the substrate side Is possible. In addition, different frequencies of RF power can be applied depending on the film to be etched.

  To obtain high-density plasma with an ICP etching apparatus, it is necessary to flow the RF current J flowing through the antenna coil 12 with low loss, and to increase the area, the inductance of the antenna coil 12 must be reduced. For this purpose, an ICP etching apparatus for a multi-spiral coil 22 having an antenna divided as shown in FIG. 23 has been developed. In FIG. 23, 21 is a quartz plate, 23 and 26 are matching boxes, and 24 and 27 are RF power supplies. At the bottom of the chamber, a lower electrode 25 for holding a substrate 28 is provided via an insulator 29.

  In this embodiment, a wiring having a desired taper angle θ was formed by using a multi-spiral coil type ICP etching apparatus among various ICP etching apparatuses.

  In this embodiment, the bias power density of the ICP etching apparatus is adjusted in order to obtain a desired taper angle θ. FIG. 24 is a diagram showing the bias power dependence of the taper angle θ. As shown in FIG. 24, the taper angle θ can be controlled according to the bias power density.

Further, the flow ratio of CF ₄ of the etching gas (mixed gas of CF ₄ and Cl ₂ ) may be adjusted. FIG. 25 is a diagram showing the dependence of the taper angle θ on the flow ratio of CF ₄ . If the flow rate ratio of CF ₄ is increased, the selectivity between tungsten and resist is increased, and the taper angle θ of the wiring can be increased.

Also, it is considered that the taper angle θ depends on the selection ratio between tungsten and resist. FIG. 26 shows the dependence of the selectivity of tungsten and resist on the taper angle θ.

  By appropriately determining the bias power density and the reactant gas flow ratio using the ICP etching apparatus in this manner, the desired taper angle θ = 3 to 60 ° (preferably 5 to 45 °, more preferably 7 to 45 °). 20 °), and a gate electrode and a wiring having an angle of 20 ° were formed.

  Here, the W film is shown as an example. However, when an ICP etching apparatus is used for a generally known heat-resistant conductive material (Ta, Ti, Mo, Cr, Nb, Si, etc.), the end of the pattern can be easily formed. Can be processed into a tapered shape.

Further, a mixed gas of CF ₄ (carbon tetrafluoride gas) and Cl ₂ gas was used as an etching gas used for the dry etching, but is not particularly limited, and for example, C ₂ F ₆ or C ₄ F ₈ It is also possible to use a mixed gas of a selected reactive gas containing fluorine and a gas containing chlorine selected from Cl ₂ , SiCl ₄ , or BCl ₃ .

  In the subsequent steps, according to the first embodiment, the semiconductor device is completed.

  Note that the configuration of this embodiment can be applied to the manufacturing process of the electrode having the tapered portion of the embodiment described in this specification.

Example 8
In the first embodiment, a polycrystalline silicon film crystallized by an excimer laser is used for the semiconductor layer. However, this embodiment shows another crystallization method.

  The crystallization step of this embodiment is a crystallization technique described in Patent Document 1. This crystallization step will be described with reference to FIG.

JP-A-7-130652

  First, a silicon oxide film 1002 is formed as a base film over a glass substrate 1001. An amorphous silicon film 1003 is formed over the silicon oxide film 1002. In this embodiment, the silicon oxide film 1002 and the amorphous silicon film 1003 are continuously formed by a sputtering method. Next, a nickel acetate solution containing 10 ppm by weight of nickel was applied to form a nickel-containing layer 1004. (FIG. 27A)

  In addition to nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), One or more elements selected from elements such as gold (Au) and silicon (Si) may be used.

  Next, after a hydrogen removal step at 600 ° C. for 1 hour, a heat treatment was performed at 450 to 1100 ° C. for 4 to 12 hours (500 ° C. for 4 hours in this embodiment) to form a crystalline silicon film 1005. It has been found that the crystalline silicon film 1005 thus obtained has very excellent crystallinity. (FIG. 27 (B))

  Note that the crystallization step of this embodiment can be applied to the step of forming a semiconductor layer described in this specification.

[Example 9]
This embodiment relates to a crystallization step different from that of the eighth embodiment, and an example in which crystallization is performed using the technique described in Patent Document 2 will be described. The technique described in Patent Document 2 enables selective crystallization of a semiconductor film by selectively adding a catalyst element. A case where the same technology is applied to the present invention will be described with reference to FIG.

JP-A-8-78329

  First, a silicon oxide film 1012 was formed over a glass substrate 1011, and an amorphous silicon film 1013 and a silicon oxide film 1014 were formed continuously over the surface thereof. At this time, the thickness of the silicon oxide film 1014 was set to 150 nm.

  Next, the opening 1015 was selectively formed by patterning the silicon oxide film 1014, and then a nickel acetate solution containing 100 ppm by weight of nickel was applied. The formed nickel-containing layer 1016 was in contact with the amorphous silicon film 1013 only at the bottom of the opening 1015. (FIG. 28A)

  Next, heat treatment was performed at 500 to 650 ° C. for 4 to 24 hours (in this embodiment, 550 ° C. for 14 hours) to crystallize the amorphous silicon film. In this crystallization process, the portion in contact with nickel is first crystallized, and crystal growth proceeds in a direction substantially parallel to the substrate. It has been confirmed crystallographically that it proceeds in the <111> axis direction.

  The crystalline silicon film 1017 thus formed is made up of a collection of rod-like or needle-like crystals, and each rod-like crystal is macroscopically grown in a specific direction, so that the crystallinity is uniform. There is an advantage.

  In addition, in the technology described in the above publication, besides nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt) ), Copper (Cu), gold (Au), silicon (Si), or one or more elements selected therefrom.

  A semiconductor film including a crystal (including a crystalline silicon film and a crystalline silicon germanium film) may be formed using the above-described technique, and may be patterned to form a semiconductor layer including the semiconductor film including a crystal. Subsequent steps may follow the first embodiment. Of course, a combination with Embodiments 2 to 7 is also possible.

  When a TFT is manufactured using a semiconductor film including a crystal crystallized using the technique of this embodiment, high field-effect mobility (mobility) can be obtained, but high reliability has been required. However, by adopting the TFT structure of the present invention, it has become possible to manufacture a TFT making full use of the technology of this embodiment.

[Example 10]
This embodiment shows an example in which a step of removing nickel used for crystallization of a semiconductor shown in Embodiments 8 and 9 using phosphorus after crystallization is performed. In this embodiment, the technique described in Patent Document 3 or Patent Document 4 is used as the method.

JP-A-10-135468 JP-A-10-135469

The technique described in this publication is a technique for removing a catalytic element used for crystallization of an amorphous semiconductor film after crystallization by using a gettering action of phosphorus. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 10 ¹⁷ atms / cm ³ or less, preferably to 1 × 10 ¹⁶ atms / cm ³ .

  The configuration of this embodiment will be described with reference to FIG. Here, an alkali-free glass substrate typified by a Corning 1737 substrate was used. FIG. 29A illustrates a state in which the base film 1022 and the crystalline silicon film 1023 are formed by using the crystallization technique described in Embodiment 2. Then, a silicon oxide film 1024 for a mask is formed on the surface of the crystalline silicon film 1023 to a thickness of 150 nm, an opening is provided by patterning, and a region where the crystalline silicon film is exposed is provided. Then, a step of adding phosphorus was performed to provide a region 1025 to which phosphorus was added to the crystalline silicon film.

  In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 1020 ° C. for 5 to 24 hours, for example, at 600 ° C. for 12 hours, the region 1025 in which phosphorus is added to the crystalline silicon film functions as a gettering site, and The catalytic element remaining in the conductive silicon film 1023 could be segregated in the region 1025 to which phosphorus was added.

Then, the silicon oxide film 1024 for the mask and the region 1025 to which phosphorus is added are removed by etching, so that the concentration of the catalytic element used in the crystallization step is reduced to 1 × 10 ¹⁷ atms / cm ³ or less. It was possible to obtain a crystalline silicon film reduced in size. This crystalline silicon film could be used as it is as the semiconductor layer of the TFT of the present invention shown in the first embodiment.

[Example 11]
In the present embodiment, an example in which the techniques described in Patent Literature 5 or Patent Literature 6 are combined with Embodiments 8 and 9 will be described.

JP-A-10-135468 JP-A-10-135469

The technique described in the publication is a technique for removing nickel used for crystallization of a semiconductor shown in Examples 3 and 4 after crystallization by using a gettering action of a halogen element (typically chlorine). is there. By using this technique, the nickel concentration in the semiconductor layer can be reduced to 1 × 10 ¹⁷ atoms / cm ³ or less (preferably 1 × 10 ¹⁶ atoms / cm ³ or less).

  The configuration of the present embodiment will be described with reference to FIG. First, a quartz substrate 1031 having high heat resistance was used as a substrate. Of course, a silicon substrate or a ceramic substrate may be used. When a quartz substrate is used, there is no contamination from the substrate side even if a silicon oxide film is not provided as a base film.

  Next, a crystalline silicon film (not shown) was formed using the crystallization method of Examples 3 and 4, and was patterned to form semiconductor layers 1032 and 1033. Further, a gate insulating film 1034 made of a silicon oxide film was formed to cover the semiconductor layers. (FIG. 30A)

  After the gate insulating film 1034 was formed, heat treatment was performed in an atmosphere containing a halogen element. In this embodiment, the processing atmosphere is an oxidizing atmosphere in which oxygen and hydrogen chloride are mixed, the processing temperature is 950 ° C., and the processing time is 30 minutes. The processing temperature may be selected from 700 to 1150 ° C (typically 900 to 1000 ° C), and the processing time may be selected from 10 minutes to 8 hours (typically 30 minutes to 2 hours). Just choose. (FIG. 30 (B))

At this time, nickel becomes volatile nickel chloride and is released into the processing atmosphere, and the nickel concentration in the crystalline silicon film is reduced. Therefore, the concentration of nickel contained in the semiconductor layers 1035 and 1036 shown in FIG. 30B was reduced to 1 × 10 ¹⁷ atoms / cm ³ or less.

  A semiconductor layer is formed using the present embodiment having the above-described technique, and the subsequent steps may be performed according to the first and second embodiments. Of course, it has been found that the combination of the crystallization methods of the present embodiment and the embodiment 4 can realize a crystalline silicon film having extremely high crystallinity.

(Knowledge on crystal structure of semiconductor layer)
The semiconductor layer formed in accordance with the above manufacturing process has a crystal structure in which a plurality of needle-shaped or rod-shaped crystals (hereinafter, abbreviated as rod-shaped crystals) are gathered and lined up microscopically. This was easily confirmed by TEM (transmission electron microscopy) observation.

  In addition, although the surface of the semiconductor layer (portion where a channel is formed) is slightly shifted in crystal axis by using electron beam diffraction and X-ray (X-ray) diffraction, the main orientation plane is a {110} plane. It was confirmed. As a result of the applicant's detailed observation of an electron beam diffraction photograph having a spot diameter of about 1.5 μm, diffraction spots corresponding to the {110} plane clearly appear, but each spot has a distribution on a concentric circle. confirmed.

  In addition, the present applicant has observed, by HR-TEM (high-resolution transmission electron microscopy), a crystal grain boundary formed by contact between individual rod-shaped crystals, and confirmed that the crystal lattice at the crystal grain boundary has continuity. . This can be easily confirmed because the observed lattice fringes are continuously connected at the crystal grain boundaries.

  Note that the continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of the planar grain boundary in this specification is “Planar boundary” described in Non-Patent Document 2.

Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol.27, No.5, pp.751-758, 1988

  According to the above paper, planar grain boundaries include twin grain boundaries, special stacking faults, and special twist grain boundaries. This planar grain boundary is characterized by being electrically inactive. In other words, since it is a crystal grain boundary but does not function as a trap that hinders the movement of carriers, it can be considered that it does not substantially exist.

  In particular, when the crystal axis (the axis perpendicular to the crystal plane) is the <110> axis, the {211} twin grain boundary is also called the corresponding grain boundary of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundary, and it is known that the smaller the Σ value is, the better the grain boundary is.

  As a result of observing the crystalline silicon film obtained by carrying out the present invention in detail using a TEM, it was found that most of the crystal grain boundaries (90% or more, typically 95% or more) correspond to # 3 corresponding grains. It was found to be a boundary, that is, a {211} twin grain boundary.

  In a crystal grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110}, and θ is the angle formed by lattice fringes corresponding to the {111} plane, θ = 70.5 ° It is known that sometimes it becomes a corresponding grain boundary of # 3.

  In the crystalline silicon film of this embodiment, the lattice fringes of adjacent crystal grains at the crystal grain boundaries are continuous at exactly an angle of about 70.5 °, and therefore, the crystal grain boundaries are {211} twin crystal boundaries. I came to the conclusion that there was.

  When θ = 38.9 °, a corresponding grain boundary of Σ9 was obtained, but such other crystal grain boundaries also existed.

  Such corresponding grain boundaries are formed only between crystal grains having the same plane orientation. That is, since the crystalline silicon film obtained by carrying out this embodiment has a plane orientation of approximately {110}, such a corresponding grain boundary can be formed over a wide range.

  Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency in the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, it can be considered that the semiconductor thin film having such a crystal structure has substantially no crystal grain boundary.

  It has been confirmed by TEM observation that defects existing in crystal grains have almost disappeared by the heat treatment process at a high temperature of 700 to 1150 ° C. This is apparent from the fact that the number of defects is significantly reduced before and after this heat treatment step.

This difference in the number of defects appears as a difference in spin density by electron spin resonance (ESR). At present, it has been found that the spin density of the crystalline silicon film manufactured according to the manufacturing process of this embodiment is at least 3 × 10 ¹⁷ spins / cm ³ or less (preferably 5 × 10 ¹⁵ spins / cm ³ or less). I have. However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be lower.

  From the above, the crystalline silicon film obtained by performing this example is considered to be a single crystal silicon film or a substantially single crystal silicon film because there is substantially no crystal grain boundary and no crystal grain boundary. Good. The present applicant calls a crystalline silicon film having such a crystal structure a CGS (Continuous Grain Silicon).

  For a description of CGS, reference may be made to the applications of the present applicant in Patent Document 7, Patent Document 8, Patent Document 9, or Patent Document 10.

JP-A-10-294280 JP-A-11-354442 (Japanese Patent Application No. 10-152316) JP-A-11-345767 (Japanese Patent Application No. 10-152308) JP-A-11-191628 (Japanese Patent Application No. 10-152305)

(Knowledge on TFT electrical characteristics)
The TFT manufactured in this example exhibited electrical characteristics comparable to MOSFET. The following data is obtained from a TFT prototyped by the present applicant.

The sub-threshold coefficient as an index of the switching performance (the agility of switching on / off operation) is as small as 60 to 100 mV / decade (typically 60 to 85 mV / decade) for both the n-channel TFT and the p-channel TFT.

(2) The field effect mobility (μFE) as an index of the operation speed of the TFT is 200 to 650 cm ² / Vs (typically 300 to 500 cm ² / Vs) for the n-channel TFT and 100 for the p-channel TFT. ~300cm ² / Vs (typically 150~200cm ² / Vs) as large as.

  (3) The threshold voltage (Vth) as an index of the drive voltage of the TFT is as small as -0.5 to 1.5 V for an n-channel TFT and -1.5 to 0.5 V for a p-channel TFT.

  As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.

(Knowledge on circuit characteristics)
Next, a frequency characteristic of a ring oscillator manufactured using the TFT formed by carrying out this embodiment will be described. The ring oscillator is a circuit in which inverter circuits having a CMOS structure are connected in an odd-numbered stage ring shape, and is used to calculate a delay time per one stage of the inverter circuit. The configuration of the ring oscillator used in the experiment is as follows.
Number of steps: 9 Steps Thickness of gate insulating film of TFT: 30 nm and 50 nm
Gate length of TFT: 0.6μm

  As a result of examining the oscillation frequency with this ring oscillator, it was possible to obtain an oscillation frequency of 1.04 GHz at the maximum value. Further, a shift register, which is one of the TEGs of the LSI circuit, was actually manufactured, and the operating frequency was confirmed. As a result, an output pulse having an operating frequency of 100 MHz was obtained in a shift register circuit having a gate insulating film thickness of 30 nm, a gate length of 0.6 μm, a power supply voltage of 5 V and 50 stages.

  The surprising data of the ring oscillator and the shift register as described above indicates that the TFT of this embodiment has performance (electrical characteristics) comparable or superior to that of the MOSFET.

[Example 12]
This embodiment also relates to a technique for gettering the catalyst element used in the crystallization step.

In the tenth embodiment, it is necessary to form a gettering region 1025 (see FIG. 29) in order to getter the catalytic element in the crystallized silicon. In the gettering region, a TFT cannot be formed, which hinders circuit integration. This embodiment is a gettering method that solves the above problems, the n-channel type TFT n ⁺ -type impurity regions and, using a p ⁺ -type impurity region of the p-channel type TFT in the gettering region.

In the steps described in the first embodiment, phosphorus is present in the n ⁺ -type impurity regions 313 to 315 and the p ⁺ -type impurity regions 332 and 333 at a high concentration of 5 × 10 ²⁰ atoms / cm ³ . (See FIGS. 14 and 16.) Therefore, these regions can be used as gettering regions.

  Therefore, when the semiconductor layers 302 to 304 of the TFT are formed of the crystalline silicon described in Embodiments 3 and 4, the step of activating phosphorus and boron may be used also as the heating step for gettering. For example, in the activation step (see FIG. 14D and FIG. 16D), a treatment temperature of 500 to 650 ° C. (typically 550 to 600 ° C.) for 2 to 24 hours (typically 4 to (12 hours).

In this heat treatment step, nickel remaining in the channel forming regions 311, 312, 325, 331, and 341 of each TFT diffuses toward the n ⁺ -type impurity region and the p ⁺ -type impurity region by the action of phosphorus. Captured.

Therefore, the concentration of nickel (catalyst) in n ⁺ -type impurity regions 313 to 315 and p ⁺ -type impurity regions 332 and 333 is 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm ³ (typically 1 × 10 ¹⁸ to 5 × 10 ¹⁹ atoms / cm ³ ), while the nickel concentration of the channel formation regions 311, 312, 325, 331, and 341 is 2 × 10 ¹⁷ atoms / cm ³ or less (typically 1 × 10 ¹⁴ to ³ × 10 ¹⁹ atoms / cm ³ ). 5 × 10 ¹⁶ atoms / cm ³ ).

In order to obtain the effect of this embodiment, the n ⁺ -type impurity regions 313 to 315 and the p ⁺ -type impurity regions 332 and 333 have a phosphorus or arsenic concentration of at least 1 × 10 ¹⁹ atoms / cm ³ or more ( Preferably, it is set to 1 × 10 ^{20 to} 5 × 10 ²¹ atoms / cm ³ ).

Example 13
This embodiment is a modification of the CMOS circuit of the first embodiment. Using FIG. The structure of the TFT of this embodiment will be described. 31A to 31D, the same reference numerals indicate the same components. In addition, the manufacturing steps of this embodiment may be the same as those of Embodiments 1 and 2, and the detailed description is omitted.

  FIG. 31A is a modification of the first embodiment, in which the second gate electrode (wiring) is omitted, and the gate electrode (wiring) is formed using only the electrode (wiring) having a tapered portion. .

  A base film 901 made of silicon oxide is formed on the entire surface of the substrate 900. On the base film 901, island-shaped semiconductor layers of an n-channel TFT and a p-channel TFT are formed. A gate insulating film 905 is formed over the entire surface of the substrate 900 so as to cover the island-shaped semiconductor layers. Further, a protective film 906 made of silicon nitride and an interlayer insulating film 907 are formed to cover the TFT, and a source electrode 941, 942 and a drain electrode 943 are formed on the interlayer insulating film 907.

  A gate wiring (gate electrode) 933 is formed across the semiconductor layer with the gate insulating film 905 interposed therebetween. The side surface of the gate wiring 931 is formed in a tapered shape. Here, it was formed of chromium having a thickness of 250 nm. Further, a portion intersecting with the semiconductor layer of the p-channel type TFT is reduced in width to form a second gate electrode 933A.

Example 1 was applied to the method of adding phosphorus and boron to the semiconductor layer. In the semiconductor layer of the n-channel type TFT, channel formation regions 911A, n ⁺ -type impurity regions 912A and 913A, n ⁻ -type impurity regions 914A and 915A overlapping the gate electrode 931A, and n ⁻ -type not overlapping the gate electrode 931A. Impurity regions 916A and 917A are formed.

The n ⁻ -type impurity regions 914A and 915A and the n ⁻ -type impurity regions 916A and 917A have a lower phosphorus concentration than the n ⁺ -type impurity regions 912A and 913A. The junction between n ⁻ -type impurity regions 914A and 915A and channel formation region 911A exists below the tapered portion of gate electrode 931A, and the concentration of n ⁻ -type impurity regions 914A and 915A increases toward channel formation region 911A. is decreasing.

On the other hand, a channel formation region 921A, p ⁺ -type impurity regions 922A and 923A, and p ⁺ -type impurity regions 924A and 925A are formed in the semiconductor layer of the p-channel TFT. The p ⁺ -type impurity regions 924A and 925A have a lower phosphorus concentration and the same boron concentration as the p ⁺ -type impurity regions 922A and 923A.

  FIG. 31B is a modification of the second and third embodiments, in which the second electrode is omitted and the gate electrode is formed only of an electrode having a tapered portion.

  In FIG. 31B, the gate electrode 931B is formed in a tapered shape in both the n-channel TFT and the p-channel TFT. Here, it was formed of chromium having a thickness of 250 nm.

Example 2 was applied to the step of adding phosphorus and boron to the semiconductor layer. In the semiconductor layer of the n-channel TFT, n ⁻ -type regions 914B and 915B overlapping the channel formation region 911B, n ⁺ -type impurity regions 912B and 913B, and the gate electrode 931B, and n ⁻ -type not overlapping the gate electrode 931B are provided. Impurity regions 916B and 917B are formed.

The n ⁻ -type impurity regions 914B and 915B and the n ⁻ -type impurity regions 916B and 917B have a lower phosphorus concentration than the n ⁺ -type impurity regions 912B and 913B. The junction between n ⁻ -type impurity regions 914B and 915B and channel formation region 911B exists below the tapered portion of gate electrode 931. The concentration of n ⁻ -type impurity regions 914B and 915B increases toward channel formation region 911B. is decreasing.

On the other hand, a channel formation region 921B and p ⁺ -type impurity regions 922B and 923B are formed in a semiconductor layer of the p-channel TFT in a self-aligned manner using the gate electrode 931B as a mask.

  FIG. 31C is an example in which the taper etching of the first gate electrode is omitted in the first embodiment.

  The gate wiring includes a first gate wiring 931C and a second gate wiring 932C having a smaller width in the channel length direction than the first gate wiring 931C. Note that, at a portion where the first gate wiring 931C intersects with the semiconductor layer of the p-channel TFT, a third gate electrode 933C having a reduced width is formed using the second gate wiring 932C as a mask.

In the semiconductor layer of the n-channel TFT, n ⁻ -type regions 914C and 915C overlapping the channel formation region 911C, n ⁺ -type impurity regions 912C and 913C, and the gate electrode 931C, and n ⁻ -type not overlapping the gate electrode 931C. Impurity regions 916C and 917C are formed.

The n ⁻ -type impurity regions 914C and 915C and the n ⁻ -type impurity regions 916C and 917C have a lower phosphorus concentration than the n ⁺ -type impurity regions 912C and 913C.

On the other hand, a channel formation region 921C, p ⁺ -type impurity regions 922C and 923C, and p ⁺ -type impurity regions 924C and 925C are formed in the semiconductor layer of the p-channel TFT. The p ⁺ -type impurity regions 924C and 925C have a lower phosphorus concentration than the p ⁺ -type impurity regions 922C and 923C.

  FIG. 31D shows an example in which the fourth gate wiring covering the surface of the gate wiring is formed in the first embodiment.

  In the CMOS circuit, a boron addition process is performed according to the process of the first embodiment. Next, instead of forming the protective film 906 made of silicon nitride, a metal film made of chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), or these elements is used. An alloy as a main component or a conductive material such as silicide is formed and patterned to form a fourth gate wiring 934D. After that, activation may be performed.

  With this structure, a gate wiring in which the second gate wiring 932D is surrounded by the first gate wiring 931D (including the third gate electrode 933D) and the fourth gate wiring 934D can be obtained.

In this case, the semiconductor layer of the n-channel TFT overlaps with the channel formation region 911D, the n ⁺ impurity regions 912D and 913D, and the n ⁻ impurity regions 914D and 915D overlapping the gate electrode 931D and the gate electrode 931D. not n ^- -type impurity regions 916d, although 917D is formed, the n ^- -type impurity regions 914D, 915d is a portion intersecting the first and fourth gate electrodes, n ^- -type impurity regions 916d, 917D does not cross the fourth gate electrode 934D.

The advantage of this structure is particularly effective when phosphorus is hardly added to the semiconductor layer below the first gate electrode 931D. As shown in FIG. 31D, the fourth gate electrode 934D is allowed to overlap the n ⁻ -type impurity region even if the n ⁻ -type regions 914D and 915D hardly overlap the first gate electrode 931D. Therefore, it is possible to surely form the n ⁻ -type impurity region overlapping with the gate electrode.

On the other hand, a channel formation region 921D, p ⁺ -type impurity regions 922D and 923D, and p ⁺ -type impurity regions 924D and 925D are formed in the semiconductor layer of the p-channel TFT. The p ⁺ -type impurity regions 924D and 925D have a lower phosphorus concentration than the p ⁺ -type impurity regions 922D and 923D. In this case, the n ⁻ -type impurity region and the fourth gate electrode 934D overlap. In the case where a problem occurs in off-state current characteristics or breakdown voltage, when forming the fourth gate wiring 934D, the fourth gate wiring 934D should not be formed at a portion that intersects with the semiconductor layer of the p-channel TFT. What should I do?

[Example 14]
Various liquid crystals other than the nematic liquid crystal can be used for the liquid crystal display device described in this specification. For example, the liquid crystal disclosed in Non-Patent Document 3, Non-Patent Document 4, Non-Patent Document 5, and Patent Document 11 can be used.

1998, SID, "Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability" by H. Furue et al. 1997, SID DIGEST, 841, "A Full-Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time" by T. Yoshida et al. 1996, J. Mater. Chem. 6 (4), 671-673, "Thresholdless antiferroelectricity in liquid crystals and its application to displays" by S. Inui et al. U.S. Pat.No. 5,594,569

  Using a ferroelectric liquid crystal (FLC) exhibiting an isotropic phase-cholesteric phase-chiral smectic C phase transition series, a cholesteric phase-chiral smectic C phase transition is performed while applying a DC voltage, and the cone edge is moved almost in the rubbing direction. FIG. 41 shows the electro-optical characteristics of the matched monostable FLC. The display mode using the ferroelectric liquid crystal as shown in FIG. 41 is called “Half-V switching mode”. The vertical axis of the graph shown in FIG. 41 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. The “Half-V switching mode” is described in detail in Non-Patent Documents 6 and 7.

Terada et al., "Half-V Switching Mode FLCD", Proceedings of the 46th Joint Lecture on Applied Physics, March 1999, p. 1316 Yoshihara et al., "Time-Division Full-Color LCD with Ferroelectric Liquid Crystal", Liquid Crystal Vol. 3, No. 3, page 190.

  As shown in FIG. 41, it can be seen that when such a ferroelectric mixed liquid crystal is used, low voltage driving and gradation display are possible. A ferroelectric liquid crystal exhibiting such electro-optical characteristics can be used in the liquid crystal display device of the present invention.

  A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and a drive voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) has been found. Have been.

  In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitor is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

  Since low-voltage driving is realized by using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, low power consumption is realized.

[Example 15]
The TFT of the present invention can be applied not only to the liquid crystal display device shown in Embodiment 1, but also to any semiconductor circuit. That is, the present invention may be applied to a microprocessor such as a RISC processor or an ASIC processor, or may be applied to a high-frequency circuit for a portable device (cellular phone, PHS, mobile computer) from a signal processing circuit such as a D / A converter. .

  Further, it is also possible to realize a semiconductor device having a three-dimensional structure in which an interlayer insulating film is formed on a conventional MOSFET and a semiconductor circuit is formed thereon using the TFT of the present invention. As described above, the present invention can be applied to all semiconductor devices using LSIs at present. That is, the present invention may be applied to SOI structures (TFT structures using a single crystal semiconductor thin film) such as SIMOX, Smart-Cut (registered trademark of SOITEC), and ELTRAN (registered trademark of Canon Inc.).

  Further, the semiconductor circuit of the present embodiment can be realized by using a configuration composed of any combination of Embodiments 1 to 13.

[Example 16]
In this embodiment, an example in which an active matrix EL (electroluminescence) display device is manufactured by using the present invention will be described.

  FIG. 35A is a top view of an EL display device using the present invention. In FIG. 35A, reference numeral 4010 denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, and 4013 denotes a gate side driver circuit. The respective driver circuits reach the FPC 4017 via wirings 4014 to 4016 and are connected to external devices. Is connected to

  At this time, a cover material 6000, a sealing material (also referred to as a housing material) 7000, and a sealing material (a second sealing material) 7001 are provided so as to surround at least the pixel portion, preferably, the driving circuit and the pixel portion.

  FIG. 35B shows a cross-sectional structure of the EL display device of this embodiment. A driving circuit TFT (here, a combination of an n-channel TFT and a p-channel TFT is provided on a substrate 4010 and a base film 4021). A CMOS circuit is illustrated.) 4022 and a TFT 4023 for a pixel portion (however, here, only a TFT for controlling current to an EL element is illustrated). These TFTs may use a known structure (top gate structure or bottom gate structure).

  The present invention can be used for the TFT 4022 for the driving circuit and the TFT 4023 for the pixel portion.

  When the driving circuit TFT 4022 and the pixel portion TFT 4023 are completed by using the present invention, a transparent conductive film electrically connected to the drain of the pixel portion TFT 4023 is formed on an interlayer insulating film (flattening film) 4026 made of a resin material. A pixel electrode 4027 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.

  Next, an EL layer 4029 is formed. The EL layer 4029 may have a stacked structure or a single-layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low-molecular materials and high-molecular (polymer) materials. When a low molecular material is used, an evaporation method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

  In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light of different wavelengths for each pixel using a shadow mask, color display is possible. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, and any method may be used. Needless to say, a monochromatic EL display device can be used.

  After forming the EL layer 4029, the cathode 4030 is formed thereon. It is desirable to remove moisture and oxygen existing at the interface between the cathode 4030 and the EL layer 4029 as much as possible. Therefore, it is necessary to devise a method of continuously forming the EL layer 4029 and the cathode 4030 in a vacuum or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation can be performed by using a multi-chamber method (cluster tool method) film forming apparatus.

  In this embodiment, a stacked structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used as the cathode 4030. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by an evaporation method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. The wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and is connected to the FPC 4017 via the conductive paste material 4032.

  In order to electrically connect the cathode 4030 and the wiring 4016 in the region indicated by 4031, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These may be formed at the time of etching the interlayer insulating film 4026 (when forming a contact hole for a pixel electrode) or at the time of etching the insulating film 4028 (when forming an opening before forming an EL layer). When the insulating film 4028 is etched, etching may be performed at a time up to the interlayer insulating film 4026. In this case, if the interlayer insulating film 4026 and the insulating film 4028 are the same resin material, the shape of the contact hole can be made good.

  A passivation film 6003, a filler 6004, and a cover material 6000 are formed so as to cover the surface of the EL element thus formed.

Further, a sealing material 7000 is provided inside the cover material 6000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

  At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000. As the filler 6004, PVC (polyvinyl chloride), an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

  Further, a spacer may be included in the filler 6004. At this time, the spacer may be made of a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

  In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure. Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

  In addition, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 6004, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or mylar films.

  Note that the cover material 6000 needs to have a light-transmitting property depending on the light emission direction (light emission direction) from the EL element.

  The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 7000 and the sealing material 7001 and the substrate 4010. Although the wiring 4016 has been described here, the other wirings 4014 and 4015 are electrically connected to the FPC 4017 under the sealing material 7000 and the sealing material 7001 in the same manner.

[Example 17]
In this embodiment, an example in which an EL display device having a mode different from that in Embodiment 16 is manufactured using the present invention will be described with reference to FIGS. 35 (A) and 35 (B) indicate the same parts, and thus description thereof will be omitted.

  FIG. 36A is a top view of the EL display device of this embodiment, and FIG. 36B is a cross-sectional view taken along line AA ′ of FIG. 36A.

  According to the seventeenth embodiment, a passivation film 6003 is formed to cover the surface of the EL element.

  Further, a filler 6004 is provided so as to cover the EL element. The filler 6004 also functions as an adhesive for bonding the cover material 6000. As the filler 6004, PVC (polyvinyl chloride), an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

  Further, a spacer may be included in the filler 6004. At this time, the spacer may be made of a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

  In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure. Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

  In addition, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 6004, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or mylar films.

  Note that the cover material 6000 needs to have a light-transmitting property depending on the light emission direction (light emission direction) from the EL element.

  Next, after bonding the cover material 6000 with the filler 6004, the frame material 6001 is attached so as to cover the side surface (exposed surface) of the filler 6004. The frame material 6001 is bonded by a sealing material (functioning as an adhesive) 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

  The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 6002 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.

[Example 18]
The present invention can be used in an active matrix EL display panel having a configuration as in Embodiments 16 and 17. In Embodiments 17 and 18, light is emitted downward. In this embodiment, an example of a more detailed sectional structure of the pixel portion is shown in FIG. 37, an upper surface structure is shown in FIG. The figure is shown in FIG. 37, 38 (A) and 38 (B) use the same reference numerals, so they may be referred to each other. In this embodiment, an example of upward irradiation is shown, but it goes without saying that an EL display device can be manufactured by applying the structure of the pixel portion of this embodiment to Embodiments 17 and 18.

  In FIG. 37, a switching TFT 3502 provided on a substrate 3501 is formed using the NTFT of the present invention (see Examples 1 to 13). In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However, the double gate structure has a structure in which two TFTs are substantially connected in series, and has an advantage that an off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. Further, it may be formed using the PTFT of the present invention.

  The current control TFT 3503 is formed using the NTFT of the present invention. At this time, the drain wiring 3035 of the switching TFT 3502 is electrically connected to the gate electrode 3037 of the current controlling TFT by a wiring 3036. Gate electrodes 3039a and 3039b of the switching TFT 3502 extend from the gate wiring 3039. Note that although the drawing is complicated, FIG. 38A shows only one layer of the gate wiring 3039 and the gate electrodes 3037, 3039a, and 3039b, but actually has two layers as shown in FIG.

  At this time, it is very important that the current control TFT 3503 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows, and is also an element having a high risk of deterioration due to heat or deterioration due to hot carriers. Therefore, the structure of the present invention in which the LDD region is provided on the drain side of the current controlling TFT so as to overlap the gate electrode via the gate insulating film is extremely effective.

  In this embodiment, the current control TFT 3503 is illustrated as having a single gate structure, but may have a multi-gate structure in which a plurality of TFTs are connected in series. Further, a structure may be employed in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency. Such a structure is effective as a measure against deterioration due to heat.

  As shown in FIG. 38A, a wiring serving as a gate electrode 3037 of the current control TFT 3503 overlaps with a drain wiring 3040 of the current control TFT 3503 via an insulating film in a region denoted by 3504. At this time, a capacitor is formed in a region indicated by 3504. This capacitor 3504 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 3503. Note that the drain wiring 3040 is connected to a current supply line (power supply line) 3601 and a constant voltage is constantly applied.

  A first passivation film 3041 is provided over the switching TFT 3502 and the current control TFT 3503, and a planarization film 3042 made of a resin insulating film is formed thereon. It is very important to flatten the step due to the TFT using the flattening film 3042. Since an EL layer to be formed later is extremely thin, light emission failure may be caused by the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming it so that the EL layer can be formed as flat as possible.

  Reference numeral 3043 denotes a pixel electrode (a cathode of an EL element) made of a highly reflective conductive film, which is electrically connected to the drain of the current controlling TFT 3503. As the pixel electrode 3043, a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof is preferably used. Of course, a stacked structure with another conductive film may be employed.

  In addition, a light emitting layer 3045 is formed in a groove (corresponding to a pixel) formed by the banks 3044a and 3044b formed of an insulating film (preferably resin). Although only one pixel is shown here, light emitting layers corresponding to each of R (red), G (green), and B (blue) may be separately formed. A conjugated polymer-based material is used as the organic EL material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene.

  There are various types of PPV-based organic EL materials, and materials such as those described in Non-Patent Document 8 and Patent Document 12 may be used.

H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers for Light Emitting Diodes”, Euro Display, Proceedings, 1999, p.33-37 JP-A-10-92576

  As a specific light emitting layer, cyanopolyphenylenevinylene may be used for a light emitting layer emitting red light, polyphenylenevinylene may be used for a light emitting layer emitting green light, and polyphenylenevinylene or polyalkylphenylene may be used for a light emitting layer emitting blue light. The thickness may be 30 to 150 nm (preferably 40 to 100 nm).

  However, the above example is an example of the organic EL material that can be used for the light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

  For example, in this embodiment, an example in which a polymer material is used for the light emitting layer is shown, but a low molecular organic EL material may be used. Further, an inorganic material such as silicon carbide can be used for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

  In this embodiment, an EL layer having a stacked structure in which a hole injection layer 3046 made of PEDOT (polythiophene) or PAni (polyaniline) is provided over the light-emitting layer 3045 is used. An anode 3047 made of a transparent conductive film is provided over the hole injection layer 3046. In the case of this embodiment, since the light generated in the light emitting layer 3045 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, formation is possible after forming a light-emitting layer or a hole injection layer with low heat resistance. Those that can form a film at as low a temperature as possible are preferable.

  When the anode 3047 is formed, the EL element 3505 is completed. Note that the EL element 3505 here refers to a diode formed by the pixel electrode (cathode) 3043, the light-emitting layer 3045, the hole-injection layer 3046, and the anode 3047. As illustrated in FIG. 38A, the pixel electrode 3043 substantially matches the area of the pixel, and thus the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

  By the way, in this embodiment, a second passivation film 3048 is further provided on the anode 3047. As the second passivation film 3048, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated by oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

  As described above, the EL display panel of the present invention has a pixel portion including pixels having a structure as shown in FIG. 37, and includes a switching TFT having a sufficiently low off-state current value and a current control TFT which is strong against hot carrier injection. Have. Therefore, an EL display panel having high reliability and capable of displaying an excellent image can be obtained.

  The configuration of the present embodiment can be implemented by freely combining with the configurations of Embodiments 1 to 13. In addition, it is effective to use the EL display panel of this embodiment as a display unit of the electronic device of Embodiment 22.

[Example 19]
In this embodiment, a structure in which the EL element 3505 is inverted in the pixel portion shown in Embodiment 18 will be described. FIG. 39 is used for the description. Note that the only difference from the structure in FIG. 37 is the EL element portion and the current controlling TFT, and therefore, the other description will be omitted.

  In FIG. 39, a current control TFT 3503 is formed using the PTFT of the present invention. For the manufacturing process, Embodiments 1 to 13 may be referred to.

  In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 3050. Specifically, a conductive film including a compound of indium oxide and zinc oxide is used. Of course, a conductive film formed of a compound of indium oxide and tin oxide may be used.

  After the banks 3051a and 3051b made of an insulating film are formed, a light emitting layer 3052 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 3053 made of potassium acetylacetonate (denoted as acacK) and a cathode 3054 made of an aluminum alloy are formed thereon. In this case, the cathode 3054 also functions as a passivation film. Thus, an EL element 3701 is formed.

  In the case of this embodiment, light generated in the light emitting layer 3052 is radiated outside from the substrate on which the TFT is formed as indicated by the arrow.

  Note that the configuration of the present embodiment can be implemented by freely combining with the configurations of Embodiments 1 to 13. In addition, it is effective to use the EL display panel of this embodiment as a display unit of the electronic device of Embodiment 22.

[Example 20]
In this embodiment, FIGS. 40A to 40C illustrate an example in which a pixel having a structure different from that of the circuit diagram illustrated in FIG. In this embodiment, reference numeral 3801 denotes a source wiring of the switching TFT 3802, 3803 denotes a gate wiring of the switching TFT 3802, 3804 denotes a current control TFT, 3805 denotes a capacitor, 3806 and 3808 denote a current supply line, and 3807 denotes an EL element. .

  FIG. 40A shows an example in which the current supply line 3806 is shared between two pixels. That is, the feature is that two pixels are formed to be line-symmetric with respect to the current supply line 3806. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

  FIG. 40B illustrates an example in which the current supply line 3808 is provided in parallel with the gate wiring 3803. Note that in FIG. 40B, the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other; however, if the wiring is formed in a different layer, the wiring overlaps with an insulating film. It can also be provided as follows. In this case, since the power supply line 3808 and the gate wiring 3803 can share an occupied area, the pixel portion can have higher definition.

  In FIG. 40C, similarly to the structure of FIG. 40B, a current supply line 3808 is provided in parallel with the gate wiring 3803, and two pixels are symmetric with respect to the current supply line 3808. There is a feature in that it is formed. It is also effective to provide the current supply line 3808 so as to overlap with one of the gate wirings 3803. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

  Note that the configuration of the present embodiment can be implemented by freely combining with the configurations of Embodiments 1 to 13 and 15 to 17. In addition, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electronic device of Embodiment 22.

[Example 21]
In FIGS. 38A and 38B shown in Embodiment 18, the capacitor 3504 is provided to hold the voltage applied to the gate of the current controlling TFT 3503; however, the capacitor 3504 can be omitted. . In the case of the nineteenth embodiment, since the NTFT of the present invention as shown in the first to thirteenth embodiments is used as the current control TFT 3503, it has an LDD region provided so as to overlap the gate electrode via the gate insulating film. ing. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region. The present embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 3504.

  Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

  In the structure shown in FIGS. 40A to 40C shown in the twentieth embodiment, the capacitor 3805 can be omitted in the same manner.

The configuration of the present embodiment can be implemented by freely combining with the configurations of Embodiments 1 to 13 and 16 to 20. In addition, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electronic device of Embodiment 22.
Needless to say, in Examples 17 to 22, NTFT and PTFT are the same as the n-channel TFT and p-channel TFT of the present invention.

[Example 22]
A semiconductor device using a TFT formed by carrying out the present invention can be applied to various semiconductor circuits and display devices typified by electro-optical devices. That is, the present invention can be applied to all electronic devices in which these electro-optical devices and semiconductor circuits are incorporated as components.

  Such electronic devices include a video camera, digital camera, projector (rear or front type), head mounted display (goggle type display), car navigation, personal computer, personal digital assistant (mobile computer, mobile phone or e-book) Etc.). Examples of these are shown in FIGS.

  FIG. 32A illustrates a personal computer, which includes a main body 2001, an image input unit 2002, a display device 2003, and a keyboard 2004. The present invention can be applied to the image input unit 2002, the display device 2003, and other signal control circuits.

  FIG. 32B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the audio input unit 2103, and other signal control circuits.

  FIG. 32C illustrates a mobile computer (mobile computer), which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.

  FIG. 32D illustrates a goggle-type display, which includes a main body 2301, a display device 2302, and an arm portion 2303. The present invention can be applied to the display device 2302 and other signal control circuits.

  FIG. 32E shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), and includes a main body 2401, a display device 2402, a speaker unit 2403, a recording medium 2404, and operation switches 2405. This apparatus uses a DVD (Digital Versatile Disc), a CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display device 2402 and other signal control circuits.

  FIG. 32F illustrates a digital camera, which includes a main body 2501, a display device 2502, an eyepiece 2503, operation switches 2504, and an image receiving unit (not illustrated). The present invention can be applied to the display device 2502 and other signal control circuits.

  FIG. 33A illustrates a front type projector, which includes a display device 2601 and a screen 2602. The present invention can be applied to a display device and other signal control circuits.

  FIG. 33B illustrates a rear projector, which includes a main body 2701, a display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to a display device and other signal control circuits.

  Note that FIG. 33C is a diagram illustrating an example of the structure of the display devices 2601 and 2702 in FIGS. 33A and 33B. Each of the display devices 2601 and 2702 includes a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a retardation plate 2809, and a projection optical system 2810. The projection optical system 2810 is configured by an optical system including a projection lens. In this embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

  FIG. 33D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 33D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

  As described above, the semiconductor device of the present invention has a very wide range of application, and can be applied to electronic devices in all fields. Further, the semiconductor device of the present embodiment can be realized by using a configuration composed of any combination of Embodiments 1 to 21.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention. (Embodiment 1) FIG. 4 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention. (Embodiment 1) FIG. 4 is a partial cross-sectional view of a gate electrode. (Embodiment 1) FIG. 3 is a partial cross-sectional view of a semiconductor layer. (Embodiment 1) FIG. 4 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention. (Embodiment 2) FIG. 4 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention. (Embodiment 2) FIG. 2 is a cross-sectional view of the TFT of the present invention. (Embodiment 3) FIG. 2 is a cross-sectional view of the TFT of the present invention. (Embodiment 4) FIG. 2 is a cross-sectional view of the TFT of the present invention. (Embodiment 4) FIG. 1 is a diagram schematically illustrating a liquid crystal display device of the present invention. (Example 1) FIG. 2 is a top view of a pixel portion and a CMOS circuit of the present invention. (Example 1) FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel portion of the present invention. (Example 1) FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel portion of the present invention. (Example 1) FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel portion of the present invention. (Example 1) FIG. 3 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 1) FIG. 3 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 1) FIG. 3 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 2) FIG. 3 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 3) FIG. 3 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 4) FIG. 3 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 5) FIG. 3 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 6) The figure which showed the plasma generation mechanism of the ICP etching apparatus. (Example 7) FIG. 3 is a conceptual diagram of a multi-spiral coil type ICP etching apparatus. (Example 7) FIG. 4 is a characteristic diagram of a bias power versus a taper angle θ. (Example 7) FIG. _{4 is} a characteristic diagram of a flow ratio of CF ₄ to a taper angle θ. (Example 7) (W / resist) selectivity versus taper angle θ characteristic diagram. (Example 7) 4A to 4C illustrate a manufacturing process of a crystalline silicon film of the present invention. (Example 8) 4A to 4C illustrate a manufacturing process of a crystalline silicon film of the present invention. (Example 9) 4A to 4C illustrate a manufacturing process of a crystalline silicon film of the present invention. (Example 10) 4A to 4C illustrate a manufacturing process of a crystalline silicon film of the present invention. (Example 11) FIG. 3 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 13) FIG. 13 illustrates an example of an electronic device of the invention. (Example 22) FIG. 13 illustrates an example of an electronic device of the invention. (Example 22) FIG. 4 is a graph showing gate voltage-drain current characteristics of a TFT. FIG. 2 illustrates a structure of an active matrix EL display device. (Example 16) FIG. 2 illustrates a structure of an active matrix EL display device. (Example 17) FIG. 4 is a cross-sectional view illustrating a structure of a pixel portion of an active matrix EL display device. (Example 18) 4A and 4B are a top view and a circuit diagram illustrating a structure of a pixel portion of an active matrix EL display device. (Example 18) FIG. 4 is a cross-sectional view illustrating a structure of a pixel portion of an active matrix EL display device. (Example 19) FIG. 3 is a circuit diagram illustrating a configuration of a pixel portion of an active matrix EL display device. (Example 20) The figure which shows an example of the light transmittance characteristic of an antiferroelectric mixed liquid crystal. (Example 14)

Claims (16)

Forming an insulating film in contact with the semiconductor layer,
Forming a first conductive film in contact with the insulating film;
Forming a second conductive film on the first conductive film;
Patterning the second conductive film to form a second gate electrode layer,
Etching the first gate conductive film to form a first gate electrode layer having a longer width in a channel length direction than the second gate electrode layer;
Passing at least a portion of the first gate electrode layer to add an impurity to the semiconductor layer,
A method for manufacturing a semiconductor device, wherein an angle formed by a side surface of the first gate electrode layer and the insulating film is in a range of 3 degrees or more and 60 degrees or less. Forming an insulating film in contact with the semiconductor layer,
Forming a first conductive film in contact with the insulating film;
Forming a second conductive film on the first conductive film;
Patterning the second conductive film to form a second gate electrode layer,
Etching the first gate conductive film to form a first gate electrode layer having a longer width in a channel length direction than the second gate electrode layer;
Passing a part of the first gate electrode layer to add an impurity to the semiconductor layer;
Adding the impurity to the semiconductor layer without passing through the first gate electrode layer and the second gate electrode layer;
A method for manufacturing a semiconductor device, wherein an angle formed by a side surface of the first gate electrode layer with the insulating film is in a range of 3 degrees or more and 60 degrees or less. In claim 2,
By using a mask that covers the first gate electrode layer and has a width in the channel length direction longer than that of the first gate electrode layer, the first gate electrode layer and the second gate electrode layer can pass through the first gate electrode layer and the second gate electrode layer. The method for manufacturing a semiconductor device, wherein the impurity is added to the semiconductor layer without performing the step. In any one of claims 1 to 3,
A method for manufacturing a semiconductor device, wherein an angle formed between a side surface of the first gate electrode layer and the insulating film has a value in a range of 5 to 45 degrees. In any one of claims 1 to 3,
A method for manufacturing a semiconductor device, wherein an angle formed between a side surface of the first gate electrode layer and the insulating film is in a range of 7 degrees or more and 20 degrees or less. Forming a first semiconductor layer and a second semiconductor layer,
Forming an insulating film in contact with the first semiconductor layer and the second semiconductor layer;
Forming a first conductive film on the first semiconductor layer and the second semiconductor layer;
Forming a second conductive film on the first conductive film;
Etching the second conductive film to form a first gate electrode layer and a second gate electrode layer on the first semiconductor layer and the second semiconductor layer, respectively;
Forming a third gate electrode layer and a fourth gate electrode layer between the first gate electrode layer and the second gate electrode layer and the insulating film by etching the first conductive film; And
Passing a part of each of the third gate electrode layer and the fourth gate electrode layer to add an n-type impurity to the first semiconductor layer and the second semiconductor layer;
Adding the n-type impurity to the first semiconductor layer without passing through the first gate electrode layer and the third electrode layer;
Using the second gate electrode layer and the fourth gate electrode layer as masks, adding a p-type impurity to the second semiconductor layer;
A method for manufacturing a semiconductor device, wherein an angle formed between a side surface of the third gate electrode layer and the insulating film is in a range of 3 degrees or more and 60 degrees or less. Forming a first semiconductor layer and a second semiconductor layer,
Forming an insulating film in contact with the first semiconductor layer and the second semiconductor layer;
Forming a first conductive film on the first semiconductor layer and the second semiconductor layer;
Forming a second conductive film on the first conductive film;
Etching the second conductive film to form a first gate electrode layer and a second gate electrode layer on the first semiconductor layer and the second semiconductor layer, respectively;
Forming a third gate electrode layer and a fourth gate electrode layer between the first gate electrode layer and the second gate electrode layer and the insulating film by etching the first conductive film; And
Using the second electrode layer and the fourth gate electrode layer as a mask, adding a p-type impurity to the second semiconductor layer;
Passing a part of the third gate electrode layer to add an n-type impurity to the first semiconductor layer;
Adding the n-type impurity to the first semiconductor layer without passing through the first gate electrode layer and the third electrode layer;
A method for manufacturing a semiconductor device, wherein an angle formed between a side surface of the third gate electrode layer and the insulating film is in a range of 3 degrees or more and 60 degrees or less. Forming a first semiconductor layer and a second semiconductor layer,
Forming an insulating film in contact with the first semiconductor layer and the second semiconductor layer;
Forming a first conductive film on the first semiconductor layer and the second semiconductor layer;
Forming a second conductive film on the first conductive film;
Etching the second conductive film to form a first gate electrode layer and a second gate electrode layer on the first semiconductor layer and the second semiconductor layer, respectively;
Forming a third gate electrode layer and a fourth gate electrode layer between the first gate electrode layer and the second gate electrode layer and the insulating film by etching the first conductive film; And
Using the second electrode layer and the fourth gate electrode layer as a mask, adding a p-type impurity to the second semiconductor layer;
Adding an n-type impurity to the first semiconductor layer without passing through the first gate electrode layer and the third electrode layer;
Passing a part of the third gate electrode layer to add the n-type impurity to the first semiconductor layer;
A method for manufacturing a semiconductor device, wherein an angle between the side surface of the third gate electrode layer and the insulating film is in a range of 3 degrees or more and 60 degrees or less. In any one of claims 6 to 8,
A method for manufacturing a semiconductor device, wherein an angle formed between a side surface of the third gate electrode layer and the insulating film has a value in a range of 5 to 45 degrees. In any one of claims 6 to 8,
A method for manufacturing a semiconductor device, wherein an angle formed between a side surface of the third gate electrode layer and the insulating film is in a range of 7 degrees or more and 20 degrees or less. In any one of claims 6 to 8,
The method for manufacturing a semiconductor device, wherein the third gate electrode layer has a greater width in a channel length direction than the first gate electrode layer. In any one of claims 6 to 11,
A method for manufacturing a semiconductor device, wherein an angle formed between a side surface of the fourth gate electrode layer and the insulating film is in a range of 3 degrees or more and 60 degrees or less. In any one of claims 6 to 11,
A method for manufacturing a semiconductor device, wherein an angle formed between a side surface of the fourth gate electrode layer and the insulating film has a value in a range of 5 to 45 degrees. In any one of claims 6 to 11,
A method for manufacturing a semiconductor device, wherein an angle between a side surface of the fourth gate electrode layer and the insulating film has a value in a range of 7 degrees or more and 20 degrees or less. In any one of claims 6 to 14,
The method for manufacturing a semiconductor device, wherein the fourth gate electrode layer has a longer width in a channel length direction than the second gate electrode layer. In any one of claims 6 to 11,
The method for manufacturing a semiconductor device, wherein the second gate electrode layer and the fourth gate electrode layer have the same width in a channel length direction.

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