JP2004281505A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
JP2004281505A
JP2004281505A JP2003067826A JP2003067826A JP2004281505A JP 2004281505 A JP2004281505 A JP 2004281505A JP 2003067826 A JP2003067826 A JP 2003067826A JP 2003067826 A JP2003067826 A JP 2003067826A JP 2004281505 A JP2004281505 A JP 2004281505A
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connection terminal
package
semiconductor device
lead frame
terminal portion
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JP3896975B2 (en
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Shinji Watanabe
信二 渡辺
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of a semiconductor device which is capable of preventing the generation of burrs at an internal connection terminal and a mounting connection terminal in a package of a hollow structure, and to provide the semiconductor device. <P>SOLUTION: In a lead frame 2, the internal connection terminal 2a exposed to the hollow portion 3a of the package 3 and to both surfaces outside the package 3, and the mounting connection terminal 2b exposed to the outer periphery of the package 3, are formed. The lead frame is sandwiched by an upper mold 7a and a lower mold 7b without a gap, and a molding resin is injection-molded to a cavity 8 to form the package 3. In this way, the molding resin is prevented from flowing into a portion between the terminal 2a and the upper mold 7a, between the terminal 2a and the lower mold 7b, and between the terminal 2b and the lower mold 7b. The semiconductor device can be obtained in which the generation of burrs at the terminal 2a and the terminal 2b is prevented. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子を中空構造のパッケージに内装した半導体装置の製造方法および半導体装置に関する。
【０００２】
【従来の技術】
従来、半導体素子４は、図５に示すようにパッケージ１３と呼ばれる所要形状の収容容器に内装されてなる半導体装置１０の形態で取り扱われている。このような半導体装置１０においては、半導体素子４に設けた外部接続パッド（図示せず。）とパッケージ１３に設けたリードフレーム１２の内部接続端子部１２ａとを金属ワイヤ５により導通させ、パッケージ１３外部に露出させたリードフレーム１２の実装用接続端子部１２ｂを介して実装基板（図示せず。）と導通させるようにしている（例えば、特許文献１を参照。）。
【０００３】
このような半導体装置１０において、内装される半導体素子４が、固体撮像素子、ラインセンサ用素子あるいはフォトディテクタ用素子などのように光電変換を行う受光部を具備する光電変換素子や、ＵＶＰＲＯＭ（Ｕｌｔｒａｖｉｏｌｅｔ Ｐｒｏｇｒａｍｍａｂｌｅ Ｒｅａｄ Ｏｎｌｙ Ｍｅｍｏｒｙ）のように紫外線照射を受けることによりデータの消去を行う記憶素子などの場合には、パッケージ１３内において所要の光を受けることができるようにガラス板６などの透明材料からなる採光窓が設けられている。
【０００４】
ところで、パッケージ１３は、射出成型工程により作成する。図６に示すように、上部金型７ａおよび下部金型７ｂからなる金型には、パッケージ形状に対応するキャビティ８が形成されている。パッケージ１３は、これらの上部金型７ａおよび下部金型７ｂによってリードフレーム１２を挟持し、キャビティ８内にモールド樹脂を射出することによりリードフレーム１２と一体成型される。
【０００５】
【特許文献１】
特開２００１−７７２７７号公報
【０００６】
【発明が解決しようとする課題】
ところが、図５に示すようにリードフレーム１２の内部接続端子部１２ａは、ハーフエッチング加工によって形成されているため、薄肉となっている。そのため、図６に示すように上部金型７ａおよび下部金型７ｂによってリードフレーム１２を挟持したときに、内部接続端子部１２ａは上部金型７ａで押さえることができるが、下部金型７ｂでは受けることができない。
【０００７】
つまり、従来方法では、射出成型時に、キャビティ８内に射出されたモールド樹脂がリードフレーム１２の内部接続端子部１２ａと上部金型７ａとの間に入り込むのを下部金型７ｂで押さえることができない。そのため、リードフレーム１２に撓みが発生し、図６のＡ部を拡大した図７のＢ部に示すように、内部接続端子部１２ａと上部金型７ａとの間に隙間が形成され、この隙間に入り込んだモールド樹脂は、内部接続端子部１２ａの表面にばりとして発生することになる。このように、内部接続端子部１２ａ表面にばりが発生した場合、金属ワイヤ５と内部接続端子部１２ａとの接着強度が弱くなるか、あるいは接着できないという不具合が生じる。
【０００８】
また、上記のようにリードフレーム１２に撓みが発生した場合、図７のＣ部に示すように、実装用接続端子部１２ｂと下部金型７ｂとの間にも隙間が形成されることになる。この隙間に入り込んだモールド樹脂も上記と同様に、実装用接続端子部１２ｂの表面にばりとして発生することになる。従来、この実装用接続端子部１２ｂへのばりの発生を抑制するために、射出成型前にテープ材を予め実装用接続端子部１２ｂに貼り付けた後に射出成型を行い、射出成型後にテープ材を剥がし、実装用接続端子部１２ｂを露出させていた。
【０００９】
そこで、本発明においては、中空構造パッケージの内部接続端子部および実装用接続端子部へのばりの発生を防止することが可能な半導体装置の製造方法および半導体装置を提供することを目的とする。
【００１０】
【課題を解決するための手段】
本発明の半導体装置の製造方法は、リードフレームと一体成型した中空構造のパッケージに半導体素子を内装した半導体装置の製造方法であって、パッケージの中空部およびパッケージの外部にその両面が露出する内部接続端子部と、パッケージの外周部に露出する実装用接続端子部とを形成したリードフレームを、金型により挟持し、モールド樹脂を金型内のキャビティに射出成型することによりパッケージを形成する工程を含む。
【００１１】
本発明の製造方法によれば、リードフレームの内部接続端子部が、パッケージの中空部およびパッケージの外部の両面に露出しているため、リードフレームをこの内部接続端子部において金型により隙間なく挟持することができる。これにより、モールド樹脂を金型内のキャビティに射出した際、モールド樹脂が内部接続端子部と金型との間に入り込むのを防止することができ、内部接続端子部へのばりの発生を防止した半導体装置が得られる。
【００１２】
また、モールド樹脂が内部接続端子部と金型との間に入り込むのが防止されることによって、リードフレームに撓みが発生するのを防止することができる。これにより、リードフレームの実装用接続端子部と金型との間に隙間が発生するのを防止することができ、ひいてはモールド樹脂が実装用接続端子部と金型との間に入り込むのを防止し、実装用接続端子部へのばりの発生をも防止することができる。
【００１３】
このように、リードフレームが、パッケージの中空部およびパッケージの外部の両面に露出した内部接続端子部と、パッケージの外周部に露出した実装用接続端子部とを備えた半導体装置では、内部接続端子部および実装用接続端子部へのばりの発生がないため、内装する半導体素子と内部接続端子部との電気的接続および実装時の基板と実装用接続端子部との電気的接続を確実に行うことができるうえ、パッケージの外周部に露出した実装用接続端子部によって実装も容易に行える。
【００１４】
【発明の実施の形態】
図１は本発明の実施の形態における半導体装置の縦断面図である。
【００１５】
図１において、本発明の実施の形態における半導体装置１は、リードフレーム２と一体成型した中空構造のパッケージ３に半導体素子４を内装したものである。半導体素子４は、例えば、固体撮像素子、ラインセンサ用素子あるいはフォトディテクタ用素子などの光電変換素子や、ＵＶＰＲＯＭのように紫外線照射を受けることによりデータの消去を行う記憶素子などである。半導体装置１は、これらの半導体素子４がパッケージ３内において所要の光を受けることができるようにガラス板５などの透明材料からなる採光窓を備える。
【００１６】
リードフレーム２は、半導体素子４と電気的接続するための内部接続端子部２ａと、内部接続端子部２ａを介して半導体素子４との電気的導通を得るための実装用接続端子部２ｂと、パッケージ３内に埋入させることによりパッケージ３との結合性を高めるための薄肉部２ｃとを備える。内部接続端子部２ａおよび実装用接続端子部２ｂは、単一厚さのリードフレーム材料に対して薄肉部２ｃ以外の部分（内部接続端子部２ａおよび実装用接続端子部２ｂの部分）にレジストを形成し、ハーフエッチングすることにより形成する。
【００１７】
このリードフレーム２とパッケージ３とはモールド樹脂による射出成型工程により一体成型されたものである。但し、内部接続端子部２ａは、金属ワイヤ６により半導体素子４と接続するため、パッケージ３の中空部３ａに露出するように形成する。また、内部接続端子部２ａは、パッケージ３の底面（半導体装置１の実装面）外部にも露出させる。一方、実装用接続端子部２ｂは、半導体装置１の基板上などへの実装を容易にするため、パッケージ３の底面の外周部に露出させる。
【００１８】
図２は図１の半導体装置の製造工程図、図３はリードフレーム２の平面図である。以下、図２の（ａ）〜（ｅ）に基づいて、図１の半導体装置の製造工程について説明する。
【００１９】
（ａ）射出成型工程
ハーフエッチングにより内部接続端子部２ａ、実装用接続端子部２ｂおよび薄肉部２ｃを形成したリードフレーム２を、上部金型７ａおよび下部金型７ｂからなる金型によって挟持する。なお、リードフレーム２は、図３に示すように、隣接する実装用接続端子部２ｂ間のピッチを、内部接続端子部２ａ間のピッチよりも広くとっている。
【００２０】
上部金型７ａおよび下部金型７ｂからなる金型には、パッケージ３の形状に対応するキャビティ８が形成されている。すなわち、キャビティ８は、リードフレーム２の内部接続端子部２ａを、射出成型するパッケージ３の中空部３ａおよび底面外部に露出させるため、内部接続端子部２ａに当接するように形成されている。
【００２１】
このため、リードフレーム２は、この内部接続端子部２ａにおいて上部金型７ａおよび下部金型７ｂにより隙間なく挟持される。これにより、キャビティ８へモールド樹脂を射出した際、このモールド樹脂が内部接続端子部２ａと上部金型７ａおよび下部金型７ｂとの間に入り込まなくなる。また、内部接続端子部２ａを上部金型７ａおよび下部金型７ｂにより挟持することによってリードフレーム２が平らな状態で支持されるため、実装用接続端子部２ｂと下部金型７ｂとの間に隙間が発生せず、モールド樹脂が実装用接続端子部２ｂと下部金型７ｂとの間へ入り込むのが防止される。
【００２２】
また、パッケージ３の射出成型を行った後、リードフレーム２に対してめっき処理を行い、内部接続端子部２ａおよび実装用接続端子部２ｂに所要の金属被膜を形成する。なお、射出成型後にめっき処理を行うのではなく、予め金属被膜を形成したリードフレーム２を用いてパッケージ３の射出成型を行ってもよい。
【００２３】
（ｂ）ダイボンディング工程
リードフレーム２と一体成型されたパッケージ３の中空部３ａへ半導体素子４を適宜の接着剤を用いて接着する。
【００２４】
（ｃ）ワイヤーボンディング工程
半導体素子４の外部接続パッド（図示せず。）と中空部３ａに露出したリードフレーム２の内部接続端子部２ａとを金属ワイヤ５により導通接続する。
【００２５】
（ｄ）ガラス封止工程
パッケージ３の中空部３ａ上へガラス板５をシール材（図示せず。）を用いて接着する。
【００２６】
（ｅ）パッケージ分離工程
所要形状の各パッケージ３へ分離する。図４は完成した半導体装置を示している。同図（ａ）は平面図、（ｂ）は下面図である。
【００２７】
以上のように、本実施形態における半導体装置１では、半導体素子４を内装する中空構造のパッケージ３に一体成型するリードフレーム２に、パッケージ３の中空部３ａおよびパッケージ３の底面外部の両面に露出する内部接続端子部２ａと、パッケージ３の外周部に露出する実装用接続端子部２ｂとを設けている。これにより、内部接続端子部２ａは、上部金型７ａおよび下部金型７ｂで挟持することが可能となるため、射出成型時にモールド樹脂が内部接続端子部２ａと上部金型７ａおよび下部金型７ｂとの間に入り込まなくなり、内部接続端子部２ａへのばりの発生を防止することができる。
【００２８】
また、これによって、リードフレーム２が平らな状態で支持され、実装用接続端子部２ｂと下部金型７ｂとの間に隙間が発生することがないため、実装用接続端子部２ｂと下部金型７ｂとの間にモールド樹脂が入り込まなくなり、実装用接続端子部２ｂへのばりの発生を防止することが可能となる。従来、実装用接続端子部１２ｂへのばりの発生を抑制するために、ばり防止用のテープ材を用いていたが、実装用接続端子部２ｂへのばりの発生が防止されることで、このばり防止用のテープ材を廃止し、製造コストを削減することが可能となる。
【００２９】
また、本実施形態における半導体装置１では、実装用接続端子部２ｂを、パッケージ３の外周部へ露出させているため、基板上への実装も容易となる。さらに、実装用接続端子部２ｂをパッケージ３の外周部へ配置することによって、例えば図３、図４に示すように、実装用接続端子部２ｂのピッチを、内部接続端子部２ａのピッチよりも広くとることが可能になる。これにより、基板実装性および基板実装信頼性を向上することが可能となる。
【００３０】
なお、図４（ｂ）に示すように、内部接続端子部２ａと実装用接続端子部２ｂとの間の薄肉部２ｃは、パッケージ３内に埋入されているため、パッケージ３の下面には露出していない。このように、本実施形態における半導体装置１では、リードフレーム２に薄肉部２ｃを備え、この薄肉部２ｃをパッケージ３内に埋入させることにより、リードフレーム２とパッケージ３との結合性が高められている。
【００３１】
【発明の効果】
本発明により、以下の効果を奏することができる。
【００３２】
（１）リードフレームが、パッケージの中空部およびパッケージの外部にその両面が露出した内部接続端子部と、パッケージの外周部に露出した実装用接続端子部とを備えることにより、射出成型時に金型により隙間なく挟持することが可能となり、モールド樹脂が内部接続端子部と金型との間に入り込むのを防止し、内部接続端子部へのばりの発生を防止することが可能となる。
【００３３】
（２）実装用接続端子部も金型へ押さえ付けることができるようになるため、実装用接続端子部へのばりの発生を防止することが可能となる。これにより、従来ばり防止用に用いていたテープ材を廃止し、製造コストを削減することが可能となる。
【００３４】
（３）実装用接続端子部をパッケージの外周部へ配置することによって、実装用接続端子部のピッチを、内部接続端子部のピッチよりも広くすることができるため、基板実装性および基板実装信頼性を向上することが可能となる。
【図面の簡単な説明】
【図１】本発明の実施の形態における半導体装置の縦断面図である。
【図２】図１の半導体装置の製造工程図である。
【図３】リードフレームの平面図である。
【図４】完成した半導体装置を示し、（ａ）は平面図、（ｂ）は下面図である。
【図５】従来の半導体装置の縦断面図である。
【図６】図５の半導体装置の射出成型工程を示す図である。
【図７】図６のＡ部拡大図である。
【符号の説明】
１ 半導体装置
２ リードフレーム
２ａ 内部接続端子部
２ｂ 実装用接続端子部
２ｃ 薄肉部
３ パッケージ
３ａ 中空部
４ 半導体素子
５ ガラス板
６ 金属ワイヤ
７ａ 上部金型
７ｂ 下部金型
８ キャビティ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor element is housed in a package having a hollow structure, and a semiconductor device.
[0002]
[Prior art]
Conventionally, as shown in FIG. 5, the semiconductor element 4 is handled in the form of a semiconductor device 10 which is housed in a container having a required shape called a package 13. In such a semiconductor device 10, the external connection pads (not shown) provided on the semiconductor element 4 and the internal connection terminals 12 a of the lead frame 12 provided on the package 13 are electrically connected by the metal wires 5, and the package 13 It is configured to be electrically connected to a mounting board (not shown) through the mounting connection terminal portion 12b of the lead frame 12 exposed to the outside (for example, see Patent Document 1).
[0003]
In such a semiconductor device 10, the semiconductor element 4 to be housed is a photoelectric conversion element including a light receiving unit that performs photoelectric conversion, such as a solid-state imaging element, a line sensor element, or a photodetector element, or a UVPROM (Ultraviolet Programmable). In the case of a storage element that erases data by being irradiated with ultraviolet rays, such as a read only memory (Read Only Memory), daylighting made of a transparent material such as a glass plate 6 so that required light can be received in the package 13. Windows are provided.
[0004]
By the way, the package 13 is created by an injection molding process. As shown in FIG. 6, a cavity composed of an upper mold 7a and a lower mold 7b has a cavity 8 corresponding to the package shape. The package 13 is molded integrally with the lead frame 12 by holding the lead frame 12 between the upper mold 7 a and the lower mold 7 b and injecting a mold resin into the cavity 8.
[0005]
[Patent Document 1]
JP 2001-77277 A
[Problems to be solved by the invention]
However, as shown in FIG. 5, the internal connection terminal portions 12a of the lead frame 12 are formed by half-etching, and thus are thin. Therefore, when the lead frame 12 is sandwiched between the upper mold 7a and the lower mold 7b as shown in FIG. 6, the internal connection terminal portion 12a can be pressed by the upper mold 7a, but is received by the lower mold 7b. I can't.
[0007]
That is, in the conventional method, the lower mold 7b cannot prevent the mold resin injected into the cavity 8 from entering between the internal connection terminal portion 12a of the lead frame 12 and the upper mold 7a during the injection molding. . For this reason, the lead frame 12 is bent, and a gap is formed between the internal connection terminal portion 12a and the upper mold 7a, as shown in FIG. The mold resin that has penetrated is generated as burrs on the surface of the internal connection terminal portion 12a. As described above, when burrs are generated on the surface of the internal connection terminal portion 12a, there occurs a problem that the bonding strength between the metal wire 5 and the internal connection terminal portion 12a is weak or that the metal wire 5 cannot be bonded.
[0008]
Further, when the lead frame 12 is bent as described above, a gap is also formed between the mounting connection terminal portion 12b and the lower mold 7b as shown in a portion C in FIG. . The mold resin that has entered this gap is also generated as burrs on the surface of the mounting connection terminal portion 12b in the same manner as described above. Conventionally, in order to suppress the occurrence of burrs on the mounting connection terminal portion 12b, injection molding is performed after a tape material is previously adhered to the mounting connection terminal portion 12b before injection molding, and the tape material is injected after the injection molding. It was peeled off to expose the mounting connection terminal portion 12b.
[0009]
In view of the above, an object of the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device capable of preventing occurrence of burrs on an internal connection terminal portion and a mounting connection terminal portion of a hollow structure package.
[0010]
[Means for Solving the Problems]
A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a semiconductor element is mounted in a package having a hollow structure integrally formed with a lead frame, wherein the inside of the package has a hollow portion and both sides are exposed to the outside of the package. A step of forming a package by sandwiching a lead frame in which a connection terminal portion and a mounting connection terminal portion exposed on an outer peripheral portion of the package are formed by a mold, and injecting molding resin into a cavity in the mold. including.
[0011]
According to the manufacturing method of the present invention, since the internal connection terminal portions of the lead frame are exposed on both surfaces of the hollow portion of the package and the outside of the package, the lead frame is sandwiched between the internal connection terminal portions by the mold without any gap. can do. As a result, when the mold resin is injected into the cavity in the mold, the mold resin can be prevented from entering between the internal connection terminal portion and the mold, thereby preventing the occurrence of burrs on the internal connection terminal portion. The obtained semiconductor device is obtained.
[0012]
In addition, since the mold resin is prevented from entering between the internal connection terminal portion and the mold, it is possible to prevent the lead frame from being bent. As a result, it is possible to prevent a gap from being generated between the mounting connection terminal portion of the lead frame and the mold, thereby preventing mold resin from entering between the mounting connection terminal portion and the mold. However, it is also possible to prevent the occurrence of burrs on the mounting connection terminal portion.
[0013]
As described above, in the semiconductor device in which the lead frame includes the internal connection terminal portion exposed on both surfaces of the hollow portion of the package and the outside of the package and the mounting connection terminal portion exposed on the outer peripheral portion of the package, the internal connection terminal Since no burrs are generated on the mounting part and the mounting connection terminal part, the electrical connection between the internal semiconductor element and the internal connection terminal part and the electrical connection between the board and the mounting connection terminal part during mounting are reliably performed. In addition, mounting can be easily performed by the mounting connection terminal portion exposed on the outer peripheral portion of the package.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a longitudinal sectional view of a semiconductor device according to an embodiment of the present invention.
[0015]
In FIG. 1, a semiconductor device 1 according to an embodiment of the present invention has a semiconductor element 4 housed in a package 3 having a hollow structure integrally formed with a lead frame 2. The semiconductor element 4 is, for example, a photoelectric conversion element such as a solid-state imaging element, a line sensor element, or a photodetector element, or a storage element such as a UVPROM that erases data by receiving ultraviolet irradiation. The semiconductor device 1 includes a lighting window made of a transparent material such as a glass plate 5 so that the semiconductor elements 4 can receive required light in the package 3.
[0016]
The lead frame 2 includes an internal connection terminal 2a for electrically connecting to the semiconductor element 4, a mounting connection terminal 2b for obtaining electrical continuity with the semiconductor element 4 via the internal connection terminal 2a, A thin portion 2c for improving the bonding property with the package 3 by being embedded in the package 3; The internal connection terminal portion 2a and the mounting connection terminal portion 2b are formed by applying a resist to a portion other than the thin portion 2c (the portion of the internal connection terminal portion 2a and the mounting connection terminal portion 2b) for a single-thickness lead frame material. It is formed by forming and half-etching.
[0017]
The lead frame 2 and the package 3 are integrally formed by an injection molding process using a mold resin. However, the internal connection terminal portion 2a is formed so as to be exposed in the hollow portion 3a of the package 3 to be connected to the semiconductor element 4 by the metal wire 6. The internal connection terminal 2a is also exposed outside the bottom surface of the package 3 (the mounting surface of the semiconductor device 1). On the other hand, the mounting connection terminal portion 2b is exposed at the outer peripheral portion of the bottom surface of the package 3 to facilitate mounting the semiconductor device 1 on a substrate or the like.
[0018]
2 is a manufacturing process diagram of the semiconductor device of FIG. 1, and FIG. 3 is a plan view of the lead frame 2. Hereinafter, the manufacturing process of the semiconductor device of FIG. 1 will be described with reference to FIGS.
[0019]
(A) Injection molding step The lead frame 2 on which the internal connection terminals 2a, the mounting connection terminals 2b, and the thin portions 2c are formed by half-etching is clamped by a mold including an upper mold 7a and a lower mold 7b. In the lead frame 2, as shown in FIG. 3, the pitch between adjacent mounting connection terminals 2b is wider than the pitch between the internal connection terminals 2a.
[0020]
In a mold composed of the upper mold 7a and the lower mold 7b, a cavity 8 corresponding to the shape of the package 3 is formed. That is, the cavity 8 is formed so as to abut the internal connection terminal portion 2a in order to expose the internal connection terminal portion 2a of the lead frame 2 to the outside of the hollow portion 3a and the bottom surface of the package 3 to be injection-molded.
[0021]
Therefore, the lead frame 2 is sandwiched between the upper mold 7a and the lower mold 7b without any gap in the internal connection terminal 2a. Thus, when the mold resin is injected into the cavity 8, the mold resin does not enter between the internal connection terminal 2a and the upper mold 7a and the lower mold 7b. In addition, since the lead frame 2 is supported in a flat state by holding the internal connection terminal portion 2a between the upper mold 7a and the lower mold 7b, the lead frame 2 is held between the mounting connection terminal portion 2b and the lower mold 7b. A gap is not generated, and the mold resin is prevented from entering between the mounting connection terminal portion 2b and the lower mold 7b.
[0022]
Further, after performing the injection molding of the package 3, the lead frame 2 is plated to form a required metal film on the internal connection terminal portion 2a and the mounting connection terminal portion 2b. Note that, instead of performing the plating process after the injection molding, the injection molding of the package 3 may be performed using the lead frame 2 on which a metal film is formed in advance.
[0023]
(B) Die bonding step The semiconductor element 4 is bonded to the hollow portion 3a of the package 3 integrally formed with the lead frame 2 using an appropriate adhesive.
[0024]
(C) Wire bonding step The external connection pads (not shown) of the semiconductor element 4 and the internal connection terminal portions 2a of the lead frame 2 exposed in the hollow portions 3a are electrically connected by the metal wires 5.
[0025]
(D) Glass sealing step The glass plate 5 is bonded onto the hollow portion 3a of the package 3 using a sealing material (not shown).
[0026]
(E) Package separation step Separation into packages 3 of required shape. FIG. 4 shows the completed semiconductor device. 2A is a plan view, and FIG. 1B is a bottom view.
[0027]
As described above, in the semiconductor device 1 according to the present embodiment, the lead frame 2 integrally molded with the package 3 having the hollow structure in which the semiconductor element 4 is housed is exposed to both the hollow portion 3 a of the package 3 and the outer surface of the bottom surface of the package 3. And a mounting connection terminal 2b exposed on the outer peripheral portion of the package 3. Thus, the internal connection terminal 2a can be sandwiched between the upper mold 7a and the lower mold 7b, so that the molding resin is injected into the internal connection terminal 2a and the upper mold 7a and the lower mold 7b during injection molding. To prevent the occurrence of burrs on the internal connection terminal portion 2a.
[0028]
Further, the lead frame 2 is thereby supported in a flat state, and no gap is generated between the mounting connection terminal portion 2b and the lower mold 7b. 7b does not enter the mold resin, and it is possible to prevent the occurrence of burrs on the mounting connection terminal portion 2b. Conventionally, in order to suppress the occurrence of burrs on the mounting connection terminal portion 12b, a tape material for preventing burrs was used. However, since the occurrence of burrs on the mounting connection terminal portion 2b is prevented, Eliminating the tape material for preventing burrs makes it possible to reduce manufacturing costs.
[0029]
Further, in the semiconductor device 1 according to the present embodiment, since the mounting connection terminal portion 2b is exposed to the outer peripheral portion of the package 3, mounting on the substrate becomes easy. Further, by arranging the mounting connection terminal portion 2b on the outer peripheral portion of the package 3, the pitch of the mounting connection terminal portion 2b is made larger than the pitch of the internal connection terminal portion 2a as shown in FIGS. It becomes possible to take it widely. As a result, it is possible to improve the board mountability and the board mount reliability.
[0030]
As shown in FIG. 4B, the thin portion 2c between the internal connection terminal portion 2a and the mounting connection terminal portion 2b is embedded in the package 3, so that the lower surface of the package 3 Not exposed. As described above, in the semiconductor device 1 according to the present embodiment, the thin frame portion 2c is provided in the lead frame 2, and the thin wall portion 2c is embedded in the package 3, so that the connectivity between the lead frame 2 and the package 3 is enhanced. Have been.
[0031]
【The invention's effect】
According to the present invention, the following effects can be obtained.
[0032]
(1) Since the lead frame is provided with an internal connection terminal portion whose both surfaces are exposed to the outside of the package and the hollow portion of the package, and a mounting connection terminal portion which is exposed to the outer periphery of the package, a mold is used during injection molding. Accordingly, it is possible to sandwich the resin without any gap, prevent the mold resin from entering between the internal connection terminal and the mold, and prevent the occurrence of burrs on the internal connection terminal.
[0033]
(2) Since the mounting connection terminal portion can also be pressed against the mold, it is possible to prevent the occurrence of burrs on the mounting connection terminal portion. As a result, the tape material conventionally used for preventing burrs is abolished, and the manufacturing cost can be reduced.
[0034]
(3) By arranging the mounting connection terminal portions on the outer periphery of the package, the pitch of the mounting connection terminal portions can be made wider than the pitch of the internal connection terminal portions. It is possible to improve the performance.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a manufacturing process diagram of the semiconductor device of FIG. 1;
FIG. 3 is a plan view of a lead frame.
4A and 4B show a completed semiconductor device, wherein FIG. 4A is a plan view and FIG. 4B is a bottom view.
FIG. 5 is a longitudinal sectional view of a conventional semiconductor device.
FIG. 6 is a view showing an injection molding step of the semiconductor device of FIG. 5;
FIG. 7 is an enlarged view of a portion A in FIG. 6;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Lead frame 2a Internal connection terminal part 2b Mounting connection terminal part 2c Thin part 3 Package 3a Hollow part 4 Semiconductor element 5 Glass plate 6 Metal wire 7a Upper die 7b Lower die 8 Cavity

Claims (4)

リードフレームと一体成型した中空構造のパッケージに半導体素子を内装した半導体装置の製造方法であって、
前記パッケージの中空部および前記パッケージの外部にその両面が露出する内部接続端子部と、前記パッケージの外周部に露出する実装用接続端子部とを形成したリードフレームを、金型により挟持し、モールド樹脂を前記金型内のキャビティに射出成型することにより前記パッケージを形成する工程
を含む半導体装置の製造方法。A method for manufacturing a semiconductor device in which a semiconductor element is housed in a package having a hollow structure integrally molded with a lead frame,
A lead frame formed with a hollow portion of the package and an internal connection terminal portion whose both surfaces are exposed to the outside of the package, and a mounting connection terminal portion exposed at an outer peripheral portion of the package is sandwiched by a mold, and molded. A method of manufacturing a semiconductor device, comprising a step of forming the package by injection molding a resin into a cavity in the mold. 前記内部接続端子部および実装用接続端子部は、ハーフエッチングにより形成することを特徴とする請求項１記載の半導体装置の製造方法。2. The method according to claim 1, wherein the internal connection terminal and the mounting connection terminal are formed by half etching. リードフレームと一体成型した中空構造のパッケージに半導体素子を内装した半導体装置において、
前記リードフレームが、前記パッケージの中空部および前記パッケージの外部の両面に露出した内部接続端子部と、前記パッケージの外周部に露出した実装用接続端子部とを備える
ことを特徴とする半導体装置。In a semiconductor device in which a semiconductor element is mounted in a hollow structure package integrally molded with a lead frame,
A semiconductor device, wherein the lead frame includes an internal connection terminal portion exposed on both surfaces of the hollow portion of the package and the outside of the package, and a mounting connection terminal portion exposed on an outer peripheral portion of the package. 前記実装用接続端子部のピッチが、前記内部接続端子部のピッチよりも広いことを特徴とする請求項３記載の半導体装置。The semiconductor device according to claim 3, wherein a pitch of the mounting connection terminals is wider than a pitch of the internal connection terminals.
JP2003067826A 2003-03-13 2003-03-13 Semiconductor device manufacturing method and semiconductor device Expired - Fee Related JP3896975B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007035844A (en) * 2005-07-26 2007-02-08 Mitsui Chemicals Inc Hollow package made of resin and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007035844A (en) * 2005-07-26 2007-02-08 Mitsui Chemicals Inc Hollow package made of resin and semiconductor device

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