JP2004273700A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device which is excellent in stress migration tolerance and where control of a manufacturing process is easy. <P>SOLUTION: The semiconductor is obtained by providing Cu wires 8a to 8c on a lower layer, providing Cu wires 20a to 20c on a lower layer, and electrically connecting both of them with connection parts 21a to 21c. At the upper part of a large-width Cu wiring 8a meeting a condition that the ratio of a wire depth (d) to the wiring width (w) of a copper wiring is not larger than 0.5, a barrier metal film 12a is provided whose adhesiveness with the large-width Cu wiring 8a is more excellent than that of an insulation film at the large-width Cu wiring 8a. On the other hand, at the upper parts of small-width Cu wires 8b and 8c which does not meet the condition, a conductive thin film layer equivalent to the barrier metal film 12a is not formed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an improvement in stress migration (hereinafter sometimes abbreviated as “SM”) resistance in a wide wiring portion in a damascene wiring structure using copper.
[0002]
[Prior art]
In a semiconductor device, in order to satisfy a required operation speed, a copper damascene wiring structure using copper (Cu) having a lower resistance as a wiring material is used instead of a conventional wiring structure mainly composed of an aluminum (Al) -based alloy. It is being used.
[0003]
Conventionally, in a buried Cu wiring by a damascene method, a technique of Patent Document 1 is known in which a titanium tungsten nitride film is left only on a Cu film whose surface in a groove is depressed by a resist etchback method.
[0004]
[Patent Document 1]
JP-A-10-189592 [0005]
[Problems to be solved by the invention]
However, in the related art, since the surface in the groove of the Cu film is depressed, the cross-sectional area of the Cu film is reduced and the wiring resistance is increased. Sophisticated control of the manufacturing process, such as fine adjustment, was required.
[0006]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device having excellent resistance to stress migration and easily controlling a manufacturing process, and a method of manufacturing the same.
[0007]
[Means for Solving the Problems]
2. The semiconductor device according to claim 1, further comprising first and second lower-layer copper wirings, wherein the first lower-layer copper wiring satisfies a predetermined condition, and wherein the second lower-layer copper wiring satisfies the predetermined lower-level copper wiring. The first and second upper copper wirings formed above the first and second lower copper wirings via an insulating film, and the first and second upper copper wirings formed in the insulating film, And first and second connection portions for electrically connecting the second and lower copper wirings to the first and second upper copper wirings; and forming the first and second connection portions on the surface of the first lower copper wirings, A conductive thin film layer having higher adhesion to the first lower copper wiring than the insulating film above the first lower copper wiring, wherein the conductive thin film layer overlaps all of the electrical connection surfaces of the first connection portion. The predetermined condition is that the ratio of the formation height to the formation width of the copper wiring is 0.5 or less, Lower copper wiring, electrical connection surface all and the second connecting portion is formed of copper.
[0008]
According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: (a) forming a first insulating film on a semiconductor substrate; and (b) forming a first insulating film on an upper layer of the first insulating film. Forming a second groove; and (c) forming first and second lower-layer copper wirings in the first and second grooves, and (d) forming the first lower-layer copper wiring. Forming only a thin film conductive layer on the surface thereof, (f) forming a second insulating film on the entire surface, and (g) forming a first and a second insulating film on the upper portion of the second insulating film. Forming the upper layer copper wiring so as to be electrically connected to the first and second lower copper wirings via first and second connection portions, wherein the step (g) comprises: The first lower copper wiring is performed such that the conductive thin film layer and the entire electrical connection surface of the first connection portion overlap. Satisfies a predetermined condition, the second lower copper interconnect does not satisfy the predetermined condition, the predetermined condition is the ratio of the formed height to form the width of the copper wiring is 0.5 or less.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
<Embodiment 1>
1 to 6 are sectional views showing a method of manufacturing a semiconductor device 22 (see FIG. 2C) according to the first embodiment of the present invention in the order of steps. Hereinafter, the manufacturing steps of the semiconductor device 22 having the Cu damascene wiring structure according to this embodiment will be sequentially described with reference to these drawings.
[0010]
First, as shown in FIG. 1, an interlayer insulating film 2 is formed on a semiconductor substrate 1, and wiring grooves 4a (corresponding to a first groove), 4b and 4c (second grooves) are formed in an upper layer portion of the interlayer insulating film 2. Is selectively formed, a tantalum (Ta) film 6 as a barrier metal is formed by sputtering over the entire surface including the wiring grooves 4a to 4c, and a Cu film (not shown) as a seed film is formed. Is performed by a sputtering method, and then the Cu film 8 is buried in the wiring grooves 4a to 4c and formed over the entire surface by an electrolytic plating method.
[0011]
Next, after performing an annealing process or the like as necessary, as shown in FIG. 2, the excess Cu film 8 is removed by a chemical mechanical polishing (CMP) process to form a Cu wiring. Here, when the surplus Cu film 8 is removed by the CMP process, dishing of Cu is performed on the upper surface of the thick Cu wiring 8a (corresponding to the first lower copper wiring), and the thick Cu wiring 8a is formed on the upper portion of the wiring groove 4a. A recess (space) 10 is formed on the upper surface of the Cu wiring 8a. Specifically, the over-polishing time suitable for forming the recess 10 is measured in advance by experiment, and in the actual CMP process, the dishing amount is controlled by controlling the over-polishing time to be equal to the time obtained in the experiment. Adjust Here, the thick Cu wiring refers to a wiring in which the ratio of the wiring depth w to the wiring width w of the Cu wiring is 0.5 or less, that is, the wiring satisfies the condition (corresponding to the predetermined condition) of the equation (1). .
[0012]
d / w ≦ 0.5 Expression (1)
In other words, the wiring groove 4a is formed in the upper layer portion of the interlayer insulating film 2 to have such a relationship. For example, when the wiring depth d is 0.4 μm, the wiring width w is 0.8 μm or more. In this case, the concave portion having a depth of 1 nm or more at the deepest portion (therefore, a barrier metal film functioning as an adhesion reinforcing film described later) With a maximum thickness of 0.1 nm or more). Further, no concave portion is formed on the upper surface of the narrow wirings 8b and 8c which do not satisfy the wide wiring condition of the above formula (1). Through the above processing, the Cu wirings 8a, 8b, 8c were formed.
[0013]
Next, as shown in FIG. 3, a conductive film 12 made of Ta is formed on the entire upper surface by a sputtering method, and as shown in FIG. 4, an excessive conductive film is removed by a CMP process. At this time, Ta is left only in the concave portion 10 on the upper surface of the Cu wiring 8a generated by dishing, and Ta is not left in other portions such as on the narrow wirings 8b and 8c. As described above, in this embodiment, the barrier metal film 12a (corresponding to a thin film conductive layer) serving as an adhesion strengthening film is formed in a self-aligning manner on the wide Cu wiring 8a.
[0014]
Thereafter, as shown in FIG. 5, an interlayer insulating film 5 (integrated with the interlayer insulating film 2) is formed on the entire upper surface, and the grooves 14a, 14b, 14c for the Cu wiring and the upper and lower The connection holes 16a, 16b, 16c between the layers are formed.
[0015]
Further, as shown in FIG. 6, a Ta film 18 as a barrier metal is formed in the grooves 14a, 14b, 14c and the connection holes 16a, 16b, 16c by a sputtering method, and a Cu film (see FIG. (Not shown) is formed by a sputtering method, and a Cu film is buried in the grooves 14a, 14b, 14c and the connection holes 16a, 16b, 16c by an electroplating method. The wirings 20a (corresponding to the first upper-layer copper wiring), 20b and 20c (corresponding to the second upper-layer copper wiring) and the connecting portions 21a, 21b, and 21c are formed. The Cu wirings 20a to 20c are electrically connected to the Cu wirings 8a to 8c through the connecting portions 21a to 21c, and at this time, all of the bottom surface (electrically connecting surface) of the connecting portion 21a is in contact with the barrier metal film 12a. Overlap. That is, the barrier metal film 12a includes the entire electrical connection surface of the connection portion 21a with the Cu wiring 8a.
[0016]
As described above, the semiconductor device 22 having the Cu damascene wiring structure is generated.
[0017]
As described above, according to this embodiment, by providing the barrier metal film 12a above the wide Cu wiring 8a satisfying the formula (1), the adhesion between the barrier metal film 12a and the wide Cu wiring 8a is increased. In this case, the diffusion of fine voids in the thick Cu wiring 8a and the concentration at the connection portion 21a can be prevented, so that the stress migration resistance can be improved.
[0018]
In the first embodiment, since the narrow Cu wirings 8b and 8c generally have SM resistance, no barrier metal film is provided. For this reason, it is possible to avoid further lowering of the wiring due to the formation of the barrier metal film of the Cu wirings 8b and 8c having lower wiring resistance than the Cu wiring 8a.
[0019]
Further, since the barrier metal film 12a is larger than the bottom surface of the connection hole 16a and overlaps the entire bottom surface of the connection hole 16a, the effect of improving the adhesion of the Cu wiring 8a can be ensured.
[0020]
In addition, since the barrier metal film 12a covers the entire upper surface of the thick Cu wiring 8a, the barrier metal film 12a can be formed with a relatively large formation width. Control of the manufacturing process is easier than in the case of forming a metal film.
[0021]
In particular, the barrier metal film 12a can be formed in a self-aligned manner by forming the conductive film 12 on the entire upper surface and then removing the conductive film 12 except for the inside of the concave portion 10. The alignment of the film 12a becomes unnecessary. In addition, since the recesses are not formed on the upper surfaces of the narrow wires 8b and 8c, which have a relatively large influence of the reduction in the cross-sectional area of the wires due to the formation of the recesses, an increase in the wiring resistance can be suppressed.
[0022]
<Embodiment 2>
7 to 12 are sectional views showing a method of manufacturing a semiconductor device 32 (see FIG. 12) according to the second embodiment of the present invention in the order of steps. Hereinafter, the manufacturing process of the semiconductor device 32 having the Cu damascene wiring structure according to this embodiment will be sequentially described with reference to FIGS. In this embodiment, the same members as those in the first embodiment are denoted by the same reference numerals.
[0023]
First, as shown in FIG. 7, as in the first embodiment, an interlayer insulating film 2 is formed on a semiconductor substrate 1, and wiring grooves 4a, 4b, 4c are selectively formed in an upper layer portion of the interlayer insulating film 2. Then, a Ta film 6 as a barrier metal is formed on the entire surface including the wiring grooves 4a to 4c by a sputtering method, and a Cu film (not shown) as a seed film is formed by a sputtering method. Of the Cu film 8 into the wiring grooves 4a to 4c and the entire surface of the Cu film 8 are formed.
[0024]
Next, after performing an annealing process or the like as necessary, as shown in FIG. 8, the excess Cu film 8 and Ta film 6 are removed by a CMP process. As a result, a thick Cu wiring 8a and narrow Cu wirings 8b and 8c were formed. Here, the thick wiring refers to a wiring having the relationship of the formula (1) with respect to the wiring width w and the wiring depth d. In other words, the lower wiring groove 4a is formed in the interlayer insulating film 2 so as to have such a relationship.
[0025]
Next, as shown in FIG. 9, a conductive film 12 made of Ta is formed on the entire upper surface by a sputtering method, and as shown in FIG. 10, the conductive film 12 functions as an adhesion strengthening film only on the thick Cu wiring 8a. Photolithography and etching so that the remaining barrier metal film 30 (corresponding to the thin film conductive layer) remains, that is, the conductive film 12 does not remain in other portions such as the narrow wires 8b and 8c. I do. Specifically, a photoresist film (not shown) is formed only on the upper part of the Cu wiring 8a using a photoengraving technique using a mask only for the thick Cu wiring 8a. Next, using the above-mentioned photoresist as a mask, the conductive film 12 other than the upper part of the wide Cu wiring 8a is etched and removed using a dry etching technique. After that, the remaining photoresist and the like are removed by ashing, and the barrier metal film 30 is formed only on the upper portion of the thick Cu wiring 8a.
[0026]
Thereafter, as shown in FIG. 11, after an interlayer insulating film 5 is formed on the entire surface, similarly to the first embodiment, grooves 14a, 14b, 14c for the upper Cu wiring are formed on lower Cu wirings 8a, 8b, 8c. Then, the connection holes 16a, 16b, 16c between the upper and lower layers are formed. Further, as shown in FIG. 12, a Ta film 18 as a barrier metal is formed in the grooves 14a, 14b, 14c and the connection holes 16a, 16b, 16c by a sputtering method, and a Cu film (not shown) as a seed film is formed. Is formed by the sputtering method, and the grooves 14a, 14b, 14c and the connection holes 16a, 16b, 16c are continuously filled with a Cu film by the electroplating method, thereby forming the upper Cu wirings 20a, 20b, 20c. I do. The Cu wirings 20a to 20c are electrically connected to the Cu wirings 8a to 8c via the connecting portions 21a to 21c.
[0027]
At this time, the entire bottom surface (electrical connection surface) of the connection portion 21a overlaps with the barrier metal film 30. That is, the barrier metal film 30 includes the entire electrical connection surface of the connection portion 21a with the Cu wiring 8a.
[0028]
As described above, the semiconductor device 32 having the Cu damascene wiring structure is generated.
[0029]
As described above, also in this embodiment, the adhesion between the barrier metal film 30 and the thick Cu wiring 8a is provided by providing the barrier metal film 30 on the thick Cu wiring 8a satisfying the expression (1). In order to prevent the diffusion of minute voids in the thick Cu wiring 8a and the concentration at the connection portion 21a, stress migration resistance (SM resistance) can be improved. Since the narrow wires 8b and 8c have sufficient SM resistance, no barrier metal film is provided on the narrow wires 8b and 8c in this embodiment.
[0030]
Further, since the barrier metal film 30 is larger than the bottom surface of the connection hole 16a and overlaps the entire bottom surface of the connection hole 16a, the adhesion between the barrier metal film 30 and the wide Cu wiring 8a is improved. The effect of suppressing the diffusion of voids in the wiring 8a and the concentration on the connection portion 21a can be ensured.
[0031]
In addition, since the barrier metal film 30 covers the entire upper surface of the thick Cu wiring 8a, the barrier metal film 30 can be formed with a relatively large formation width, so that the barrier metal film 30 functions as an adhesion enhancement film with a minute formation width. Control of the manufacturing process is easier than in the case of forming a metal film.
[0032]
In addition, since the barrier metal film 30 is formed on the surface of the Cu wiring 8a having a large width, the photolithography technology and the etching technology are compared with the barrier metal film 12a of the first embodiment which is embedded in the surface of the Cu wiring 8a. By using this, the barrier metal film 30 can be formed with high precision.
[0033]
Furthermore, since a barrier metal film is not formed on the narrow wirings 8b and 8c, an advanced photolithography technique and an etching technique are not required, and when forming an interlayer film thereafter, the unevenness having a small pitch width is filled. Good embedding characteristics are not required because there is no need.
[0034]
<Embodiment 3>
FIG. 13 is a sectional view showing a structure of a semiconductor device 42 according to the third embodiment of the present invention. In this embodiment, the same members as those in the first embodiment are denoted by the same reference numerals.
[0035]
As shown in FIG. 5, in the third embodiment, the entire upper surface of the thick Cu wiring 8a which is larger than the bottom surface of the connecting hole 16a (larger than the contact area between the connecting hole 16a and the wide Cu wiring 8a) and lower A barrier metal film 40 (corresponding to a thin film conductive layer) is formed so as to be smaller and overlap the entire bottom surface of the connection hole 16a. As described above, the barrier metal film functioning as the adhesion strengthening film does not necessarily need to cover the entire upper surface of the wide Cu wiring 8a, and if the barrier metal film 40 is formed at least around the bottom of the connection hole 16a and larger than the contact area. Good.
[0036]
The photolithography technique and the etching technique are used for forming the barrier metal film 40 as in the second embodiment. However, the difference is that a mask is used only for the bottom of the connection hole 16a, not for the entire top surface of the Cu wiring 8a. The other device configurations and manufacturing steps are the same as those in the second embodiment. The shape of the barrier metal film 40 may be rectangular or circular, and may be formed at least below the connection hole 16a.
[0037]
As described above, also in this embodiment, by providing the barrier metal film 40 above the wide Cu wiring 8a satisfying the formula (1), the adhesion between the barrier metal film 40 and the wide Cu wiring 8a is improved. To prevent the diffusion of voids in the thick Cu wiring 8a and the concentration on the connection portion 21a, the stress migration resistance (SM resistance) can be improved. Since sufficient SM resistance can be ensured in the narrow wires 8b and 8c, a barrier metal film functioning as an adhesion reinforcing film is not provided on the narrow wires 8b and 8c in this embodiment.
[0038]
Further, since the barrier metal film 40 is larger than the bottom surface of the connection hole 16a and overlaps the entire bottom surface of the connection hole 16a, it is possible to ensure the effect of improving the adhesion of the wide Cu wiring 8a to the connection portion 21a. it can.
[0039]
The barrier metal film 40 covers a part of the thick Cu wiring 8a, which is larger than the bottom surface of the connection hole 16a, smaller than the top surface of the Cu wiring 8a, and overlaps the entire bottom surface of the connection hole 16a. As compared with the case, the manufacturing control regarding the formation of the barrier metal film becomes easier.
[0040]
Further, when compared with the barrier metal film 12a of the first embodiment, the barrier metal film 40 can be formed with high accuracy by using a photolithography technique and an etching technique.
[0041]
Further, since no barrier metal film is formed on the narrow wirings 8b and 8c, advanced photoengraving technology and etching technology are not required, and good burying characteristics are not required when forming an interlayer film thereafter. .
[0042]
<Others>
In the first to third embodiments, Ta is used as the barrier metal film and the barrier metal. In addition, high melting point metals such as titanium (Ti) and tungsten (W) or nitrides thereof are used. , Nitride, or a stacked film thereof may be used. Although Cu was used for the seed film, an alloy containing Cu as a main component may be used. The method for forming the barrier film and the seed film is not limited to the sputtering method, but may be another method such as a CVD method. For the embedding of the wiring, the electrolytic plating method of Cu was used, but other methods such as an electroless plating method and a CVD method may be used.
[0043]
Further, in the second and third embodiments, the photoresist film is formed only on the upper part of the wide wiring 8a using the mask of only the part of the wide Cu wiring 8a. By using the same mask as that used to form 8b and 8c, the exposure amount at the time of exposure is adjusted, so that the resist pattern is left only in the wide Cu wiring 8a and the narrow Cu wiring 8b and 8c May not be resolved. This can save the cost of the mask using the same mask.
[0044]
【The invention's effect】
As described above, the semiconductor device according to claim 1 of the present invention is formed on the surface of the first lower-layer copper wiring, and has an adhesive property with the first lower-layer copper wiring that is above the first lower-layer copper wiring. The conductive thin film layer higher than the film electrically connects with the first connection portion, so that diffusion of minute voids in the first lower copper wiring and concentration on the first connection portion can be prevented. In addition, the resistance to stress migration can be improved.
[0045]
In addition, the conductive thin film layer is formed only on the first lower copper wiring having a relatively wide width satisfying a predetermined condition, and is formed on the second lower copper wiring having a relatively narrow width not satisfying the predetermined condition. Since no conductive thin film layer is formed, control of the manufacturing process is facilitated.
[0046]
According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the present invention, a conductive thin film layer formed on the surface of the first lower layer copper wiring and having higher adhesion than copper electrically connects to the first connection portion. Therefore, the adhesion between the first lower-layer copper wiring and the first connection portion can be improved, and diffusion and concentration of minute voids can be prevented, so that stress migration resistance can be improved.
[0047]
In addition, in the step (d), a conductive thin film layer is formed only on the first lower copper wiring having a relatively wide formation width satisfying a predetermined condition, and a second conductive film layer having a relatively narrow formation width not satisfying the predetermined condition is formed. Since no conductive thin film layer is formed on the lower copper wiring, control of the manufacturing process is facilitated.
[Brief description of the drawings]
FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 5 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 7 is a sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention;
FIG. 8 is a sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention;
FIG. 9 is a sectional view illustrating the method of manufacturing the semiconductor device according to the second embodiment of the present invention;
FIG. 10 is a sectional view illustrating the method of manufacturing the semiconductor device according to the second embodiment of the present invention;
FIG. 11 is a sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention;
FIG. 12 is a sectional view illustrating a method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps;
FIG. 13 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention;
[Explanation of symbols]
8a to 8c, 20a to 20c Cu wiring, 10 recess, 12a, 30, 40 barrier metal film, 14a to 14c Cu wiring groove, 16a to 16c connection hole, 21a to 21c connection portion, 22, 32, 42 Semiconductor device.

Claims (10)

A first lower copper interconnect satisfies a predetermined condition, the second lower copper interconnect does not satisfy the predetermined condition,
First and second upper-layer copper wirings formed above the first and second lower-layer copper wirings via an insulating film;
First and second connection portions formed in the insulating film and electrically connecting the first and second lower copper wirings to the first and second upper copper wirings;
A conductive thin-film layer formed on a surface of the first lower-layer copper wiring and having higher adhesion to the first lower-layer copper wiring than an insulating film above the first lower-layer copper wiring; Is formed so as to overlap with the entire electrical connection surface of the first connection portion,
The predetermined condition is that a ratio of a formation height to a formation width of the copper wiring is 0.5 or less,
The second lower layer copper wiring is characterized in that the entire electrical connection surface with the second connection portion is formed of copper.
Semiconductor device. The semiconductor device according to claim 1,
The conductive thin film layer is formed by being embedded in a surface of the first lower copper wiring.
Semiconductor device. The semiconductor device according to claim 1,
The conductive thin film layer is formed on a surface of the first lower copper wiring,
Semiconductor device. The semiconductor device according to any one of claims 1 to 3, wherein
The conductive thin film layer is formed over the entire surface of the first lower copper wiring;
Semiconductor device. The semiconductor device according to any one of claims 1 to 3, wherein
The conductive thin film layer is formed on a part of the surface of the first lower copper wiring;
Semiconductor device. (A) forming a first insulating film on a semiconductor substrate;
(B) forming first and second grooves in an upper layer of the first insulating film;
(C) forming first and second lower-layer copper interconnects in the first and second trenches,
(D) forming a thin-film conductive layer on the surface of only the first lower-layer copper wiring;
(F) forming a second insulating film on the entire surface;
(G) First and second upper copper wirings are electrically connected to the upper layer of the second insulating film via the first and second connection parts, respectively. The step (g) is performed so that the conductive thin film layer and all of the electrical connection surfaces of the first connection portion are overlapped with each other;
The first lower copper wiring does not satisfy a predetermined condition, the second lower copper wiring does not satisfy a predetermined condition,
The semiconductor device manufacturing method, wherein the predetermined condition is that a ratio of a formation height to a formation width of the copper wiring is 0.5 or less. The method for manufacturing a semiconductor device according to claim 6, wherein:
In the step (c), the concave space in which the first lower-layer copper wiring is not formed remains in the upper portion of the first groove, and the second space has no remaining portion in the second groove. Forming to be embedded in the lower copper wiring,
The step (d) includes a step of embedding a thin film conductive layer in the concave space in the first groove.
A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 6, wherein:
The step (c) includes a step of forming the first and second trenches so as to be buried with the first and second lower-layer copper wirings without having a remaining portion in the first and second trenches,
The step (d) includes forming a thin film conductive layer on the first lower copper wiring,
A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 6, wherein:
The step (d) includes forming the conductive thin film layer on the entire surface of the first lower copper wiring,
A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 6, wherein:
The step (d) includes forming the conductive thin film layer on a part of the surface of the first lower copper wiring.
A method for manufacturing a semiconductor device.

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