JP2004260064A5 - - Google Patents

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Publication number
JP2004260064A5
JP2004260064A5 JP2003050968A JP2003050968A JP2004260064A5 JP 2004260064 A5 JP2004260064 A5 JP 2004260064A5 JP 2003050968 A JP2003050968 A JP 2003050968A JP 2003050968 A JP2003050968 A JP 2003050968A JP 2004260064 A5 JP2004260064 A5 JP 2004260064A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2003050968A
Other versions
JP4531340B2 (ja
JP2004260064A (ja
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Publication date
Application filed filed Critical
Priority to JP2003050968A priority Critical patent/JP4531340B2/ja
Priority claimed from JP2003050968A external-priority patent/JP4531340B2/ja
Priority to US10/784,728 priority patent/US6885045B2/en
Priority to KR1020040011788A priority patent/KR20040077477A/ko
Priority to CNB2004100076948A priority patent/CN1293636C/zh
Publication of JP2004260064A publication Critical patent/JP2004260064A/ja
Publication of JP2004260064A5 publication Critical patent/JP2004260064A5/ja
Application granted granted Critical
Publication of JP4531340B2 publication Critical patent/JP4531340B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2003050968A 2003-02-27 2003-02-27 マルチプレクサセルのレイアウト構造 Expired - Fee Related JP4531340B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2003050968A JP4531340B2 (ja) 2003-02-27 2003-02-27 マルチプレクサセルのレイアウト構造
US10/784,728 US6885045B2 (en) 2003-02-27 2004-02-23 Layout structure of multiplexer cells
KR1020040011788A KR20040077477A (ko) 2003-02-27 2004-02-23 멀티플렉서 셀의 레이아웃 구조
CNB2004100076948A CN1293636C (zh) 2003-02-27 2004-02-27 多路复用器单元的布局结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003050968A JP4531340B2 (ja) 2003-02-27 2003-02-27 マルチプレクサセルのレイアウト構造

Publications (3)

Publication Number Publication Date
JP2004260064A JP2004260064A (ja) 2004-09-16
JP2004260064A5 true JP2004260064A5 (ja) 2006-09-21
JP4531340B2 JP4531340B2 (ja) 2010-08-25

Family

ID=32905671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003050968A Expired - Fee Related JP4531340B2 (ja) 2003-02-27 2003-02-27 マルチプレクサセルのレイアウト構造

Country Status (4)

Country Link
US (1) US6885045B2 (ja)
JP (1) JP4531340B2 (ja)
KR (1) KR20040077477A (ja)
CN (1) CN1293636C (ja)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7598165B2 (en) * 2006-08-30 2009-10-06 Micron Technology, Inc. Methods for forming a multiplexer of a memory device
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
JP5070918B2 (ja) * 2007-05-01 2012-11-14 富士通セミコンダクター株式会社 アナログ信号選択回路
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
SG10201608214SA (en) 2008-07-16 2016-11-29 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
FR2987959B1 (fr) * 2012-03-06 2014-03-14 Soitec Silicon On Insulator Multiplexeur, table de correspondance et fgpa
US20150263039A1 (en) * 2014-03-12 2015-09-17 Paramjeet Singh Standard cell layout for logic gate
US20170213847A1 (en) * 2016-01-05 2017-07-27 Bitfury Group Limited Layouts of transmission gates and related systems and techniques
US10769342B2 (en) * 2018-10-31 2020-09-08 Taiwan Semiconductor Manufacturing Company Ltd. Pin access hybrid cell height design

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5265045A (en) * 1986-10-31 1993-11-23 Hitachi, Ltd. Semiconductor integrated circuit device with built-in memory circuit group
US5194749A (en) * 1987-11-30 1993-03-16 Hitachi, Ltd. Semiconductor integrated circuit device
JPH05175467A (ja) * 1991-12-25 1993-07-13 Sharp Corp Ａｓｉｃデバイス
JPH05251671A (ja) 1992-03-06 1993-09-28 Nec Ic Microcomput Syst Ltd ゲートアレイ方式の半導体集積回路装置
US5635737A (en) * 1994-09-23 1997-06-03 Aspec Technology, Inc. Symmetrical multi-layer metal logic array with extension portions for increased gate density and a testability area
JP3523762B2 (ja) * 1996-12-19 2004-04-26 株式会社東芝 半導体記憶装置
JP3185730B2 (ja) * 1997-11-14 2001-07-11 日本電気株式会社 相補型ｍｏｓ半導体装置
JP4503809B2 (ja) 2000-10-31 2010-07-14 株式会社東芝 半導体記憶装置
JP4798881B2 (ja) * 2001-06-18 2011-10-19 富士通セミコンダクター株式会社 半導体集積回路装置
JP2003007827A (ja) * 2001-06-25 2003-01-10 Hitachi Ltd 半導体集積回路装置

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