JP2004259717A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the degree of integration of a semiconductor device and, at the same time, to reduce the size of the device by reducing the parasitic capacitance of the device. <P>SOLUTION: A laminate 17 is formed by providing an n<SP>+</SP>-type buried diffused layer 14 and an n<SP>-</SP>-type epitaxial layer 16 on a p<SP>-</SP>-type silicon substrate 12. Then first and second polycrystalline silicon layers 28a and 28b are formed on the epitaxial layer 16 by separating the layers 28b and 28b from each other by a prescribed distance. In addition, p-type impurities are respectively injected into the polycrystalline silicon layers 28a and 28b several times, and an emitter region 36a and a collector region 36b are formed by diffusing prescribed amounts of the p-type impurities injected into the silicon layers 28a and 28b into the epitaxial layer 16 underlying the silicon layers 28a and 28b. Thereafter, first and second electrode layers are respectively formed on the polycrystalline silicon layers 28a and 28b. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
[Industrial applications]
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a bipolar transistor and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, there has been a demand for improvement in characteristics such as high integration and high speed of a semiconductor device in which a plurality of bipolar transistors having high frequency characteristics are mounted.
[0003]
At present, as one technique for achieving high integration, dielectric isolation technology that reduces parasitic capacitance of a semiconductor device by electrically isolating adjacent bipolar transistors is widely used.
[0004]
Among the dielectric isolation techniques, in particular, a trench isolation method in which bipolar transistors are insulated and isolated by an insulating film (trench groove) is useful because the isolation width can be reduced by forming an isolation region deeply into the substrate (for example, , See Patent Document 1).
[0005]
[Patent Document 1]
JP-A-5-160252
[0006]
[Problems to be solved by the invention]
However, for example, when the adjacent PNP and NPN transistors are formed on the same substrate through the trench groove, the manufacturing process of the PNP transistor avoids the complexity of the processing process associated with the manufacturing process of both transistors. For this reason, there is a case where the NPN transistor manufacturing process is also used.
[0007]
Specifically, for example, when a lateral PNP transistor is manufactured as a level shift circuit of an integrated circuit including a planar NPN transistor manufactured on the same substrate, the manufacturing process of the NPN transistor is PNP. Since it becomes more dominant than the transistor manufacturing process, the degree of freedom in the manufacturing process of the PNP transistor may be reduced.
[0008]
As a result, the performance characteristics of the PNP transistor greatly depend on the manufacturing conditions of the NPN transistor. That is, for example, the impurity concentration contained in each layer of the PNP transistor is influenced by the manufacturing conditions of the NPN transistor, and thus is undesirably restricted.
[0009]
As a result, the parasitic capacitance of the PNP transistor, for example, the junction capacitance between the emitter region and the base region or between the base region and the collector region cannot be controlled as designed, and desired performance characteristics are added to the PNP transistor. There is a fear that you can not.
[0010]
The present invention has been made in view of the above-described problems, and can add predetermined performance characteristics to a semiconductor device, particularly, for example, a PNP transistor provided alongside an NPN transistor, and reduce parasitic capacitance. Accordingly, an object of the present invention is to provide a PNP transistor that can be highly integrated and miniaturized and a method of manufacturing the same.
[0011]
[Means for Solving the Problems]
Therefore, the semiconductor device manufacturing method of the present invention has the following structural features.
[0012]
That is, a laminated body forming step of forming a laminated body by providing a second conductive type impurity diffusion layer on the first conductive type semiconductor substrate, and a first polycrystal separated by a predetermined distance on the second conductive type impurity diffusion layer A polycrystalline silicon layer forming step of forming a silicon layer and a second polycrystalline silicon layer, and implanting a first conductivity type impurity into each of the first and second polycrystalline silicon layers in a plurality of times; A first concentration distribution is formed in each of the first and second polycrystalline silicon layers such that the impurity concentration of the first conductivity type decreases from the surface side of the first and second polycrystalline silicon layers toward the semiconductor substrate. The conductivity type impurity implantation step and the first conductivity type impurity implanted into the first and second polycrystalline silicon layers are disposed in the second conductivity type impurity diffusion layer below the first and second polycrystalline silicon layers. After a predetermined amount of diffusion, a predetermined distance is applied to the second conductivity type impurity diffusion layer. Emitter regions and collector regions that are spaced apart and have a concentration distribution such that the concentration of the first conductivity type impurity decreases from the surface side of the second conductivity type impurity diffusion layer toward the semiconductor substrate. After the forming step and the emitter region / collector region forming step, the first electrode layer is formed on the first polycrystalline silicon layer, and the second electrode layer is formed on the second polycrystalline silicon layer. Forming process.
[0013]
According to this configuration, a concentration distribution is formed in each of the emitter region and the collector region so that the impurity concentration of the first conductivity type decreases toward the semiconductor substrate. However, the first conductivity type impurity concentration in the junction region between each of these regions and the second conductivity type impurity diffusion layer is implanted in a plurality of times in the first conductivity type impurity implantation step (or the dose amount). Control).
[0014]
As a result, the first conductivity in the junction region is controlled, for example, by controlling the initial implantation amount of the first conductivity type impurity so as to be smaller than the conventional implantation amount, which is a one-time implantation. By reducing the type impurity concentration, a semiconductor device with reduced parasitic capacitance can be obtained.
[0015]
On the other hand, the surface side of the first and second polycrystalline silicon layers can maintain a sufficient impurity concentration even after the formation of the emitter region and the collector region by multiple injections of the first conductivity type impurities. .
[0016]
As a result, contact resistance (also referred to as contact resistance), which is a parasitic resistance between the first polycrystalline silicon layer and the first electrode layer and between the second polycrystalline silicon layer and the second electrode layer. Accordingly, it is possible to obtain a semiconductor device in which high integration and miniaturization are realized without increasing the conventional size.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS. Each figure merely shows the shape, size, and arrangement relationship of each component to the extent that the present invention can be understood, and the present invention is limited to the illustrated examples. is not. Further, in order to make the drawing easy to understand, hatching (diagonal lines) showing a cross section is omitted except for a part. In the following description, specific materials and conditions may be used. However, these materials and conditions are only preferred examples, and are not limited to these. Moreover, in each figure, the same component is attached | subjected and shown, and the duplicate description may be abbreviate | omitted.
[0018]
The semiconductor devices of the following embodiments are exemplified by a configuration in which an integrated circuit including a PNP transistor is provided as a level shift circuit of an integrated circuit including an NPN transistor adjacent to the PNP transistor. Although described, the present invention is not limited to this.
[0019]
<First Embodiment>
With reference to FIGS. 1 to 4, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described.
[0020]
As shown in FIG. 1, the semiconductor device 10 of this embodiment includes p as a first conductivity type semiconductor substrate. ⁻ N-type silicon substrate 12 with n ⁺ Mold buried diffusion layer 14 and n ⁻ A second conductivity type impurity diffusion layer 15 including a type epitaxial layer 16 is laminated to constitute a laminated body 17. N here ⁺ The type buried diffusion layer 14 is a layer in which antimony (Sb) as an n-type impurity is diffused. N ⁻ The type epitaxial layer 16 is a layer obtained by epitaxially growing single crystal silicon containing phosphorus (P) as an n-type impurity. Further, a PNP transistor region 50 and an NPN transistor region 60 which will be described later are insulated from each other by the element isolation oxide film 23. The element isolation oxide film 23 includes a silicon oxide film 22 embedded in the trench groove 19 and a p around the bottom of the trench groove 19. ⁻ And a region 20 formed by implanting boron (B) into the mold silicon substrate 12.
[0021]
The PNP transistor region 50 includes n of the second conductivity type impurity diffusion layer 15. ⁻ A p-type emitter region 36a and a p-type collector region 36b, which are the first conductivity type, are formed in the surface region of the type epitaxial layer 16 with a predetermined distance therebetween. N ⁻ N from the surface side of the epitaxial layer 16 ⁺ The depth reaching the mold buried diffusion layer 14 is n ⁺ A mold base drawer region 26a is formed. A first polycrystalline silicon layer 28a and a second polycrystalline silicon layer 28b are formed on the p-type emitter region 36a and the p-type collector region 36b, respectively. First and second polycrystalline silicon layers (28a, 28b) and n ⁺ First to third electrode layers (40a, 40b, 40c) are formed on the mold base lead region 26a.
[0022]
In this embodiment, the p-type impurity concentration contained in the p-type emitter region 36a and the p-type collector region 36b is p from the surface side of these regions. ⁻ The concentration distribution is formed so as to decrease toward the mold silicon substrate 12.
[0023]
Further, in this embodiment, sufficient p-type impurities are held on the surface side of the first and second polycrystalline silicon layers (28a, 28b), and the first and second electrode layers (40a, 40b) and There is no concern of increasing the contact resistance.
[0024]
On the other hand, the NPN transistor region 60 includes n of the second conductivity type impurity diffusion layer 15. ⁻ In the surface region of the type epitaxial layer 16, the p-type intrinsic base region 33 which is the first conductivity type and the p for the extraction electrode ⁺ A mold diffusion region 34 is formed adjacently. Further, a part of the surface region of the p-type intrinsic base region 33 is n ⁺ A mold emitter region 35 is formed. N ⁻ N from the surface side of the epitaxial layer 16 ⁺ The depth reaching the mold buried diffusion layer 14 is n ⁺ A mold collector lead region 26b is formed. p ⁺ A third polycrystalline silicon layer 28 c is formed on the mold diffusion region 34. Third polycrystalline silicon layer 28c, n ⁺ Type emitter regions 35 and n ⁺ Electrode layers (42, 44, 46) are respectively formed on the mold collector lead region 26b.
[0025]
Next, a method for manufacturing the semiconductor device 10 of this embodiment will be described below with reference to FIG.
[0026]
First, as a stacked body forming step, a stacked body is formed by providing a second conductive type impurity diffusion layer on a first conductive type semiconductor substrate.
[0027]
Specifically, p as the first conductivity type semiconductor substrate ⁻ N region on the silicon substrate 12 outside the region where the sub-contact is to be formed (not shown) ⁺ Mold embedded diffusion layer 14 and n ⁻ A second conductivity type impurity diffusion layer 15 including the type epitaxial layer 16 is sequentially formed to form a stacked body 17. N here ⁺ The type buried diffusion layer 14 is formed by diffusing n-type impurity antimony (Sb). N ⁻ The type epitaxial layer 16 is formed by epitaxially growing single crystal silicon containing phosphorus (P) as an n-type impurity (see FIG. 2A).
[0028]
Then n ⁻ A thermal oxide film (SiO2) on the entire surface of the epitaxial layer 16 ₂ ) 18 (not shown), the thermal oxide film 18 is patterned to form a trench groove for separating the PNP transistor region 50 and the NPN transistor region 60 (FIG. 2B). )reference).
[0029]
Thereafter, the stacked body 17 is etched using the thermal oxide film 18 as a mask, and p ⁻ A trench groove 19 having a depth reaching the mold silicon substrate 12 is formed. Then, p from the bottom of each trench 19 ⁻ After boron ion (B) 20 that is a p-type impurity is ion-implanted into the silicon substrate 12, the trench groove 19 is filled with a silicon oxide film 22 to form an element isolation oxide film 23 (see FIG. 2C). ).
[0030]
After that, n is added to the PNP transistor region 50 ⁺ Type (n ⁻ Since the concentration is higher than that of the type epitaxial layer 16, n ⁺ Marked as a mold. ) A step of forming the base lead region 26a is performed. This step is performed in the NPN transistor region 60. ⁺ This is performed simultaneously with the step of forming the mold collector extraction region 26b.
[0031]
More specifically, after a resist film 24 is formed on the entire surface of the thermal oxide film 18 and the element isolation oxide film 23, the resist film 24 is n-type with respect to the PNP transistor region 50. ⁺ The mold base lead region 26a is connected to the NPN transistor region 60 with n ⁺ Patterning for forming the mold collector extraction region 26b is performed. Then, n from above the thermal oxide film 18 exposed by this patterning. ⁻ The n-type impurity phosphorus (P) is ion energy 120 eV and the implantation amount is 1 × 10 4 with respect to the epitaxial layer 16. ¹⁶ Ion / cm ² Inject with n ⁺ Mold base drawer regions 26a and n ⁺ A mold collector lead region 26b is formed (see FIG. 3A).
[0032]
Next, as a polycrystalline silicon layer forming step, a first polycrystalline silicon layer 28 a and a second polycrystalline silicon layer 28 b that are separated by a predetermined distance are formed on the second conductivity type impurity diffusion layer 15.
[0033]
Specifically, after the resist film 24 remaining on the thermal oxide film 18 is removed by etching, n ⁻ In the type epitaxial layer 16, the thermal oxide film 18 on the region where the emitter region and the collector region are formed in the PNP transistor region 50 and the region where the base region is formed in the NPN transistor region 60 are removed by etching, respectively. A structure 27 is obtained.
[0034]
Thereafter, a polycrystalline silicon (polysilicon) layer 28 is formed on the entire surface of the structure 27. Subsequently, after a silicon nitride (SiN) film 30 is formed on the polycrystalline silicon layer 28 (not shown), etching is performed so that the silicon nitride film 30 remains in a region not covered with the thermal oxide film 18. Removal is performed (see FIG. 3B).
[0035]
Thereafter, selective oxidation treatment is performed on the polycrystalline silicon layer 28. By this oxidation treatment, the polycrystalline silicon layer 28 exposed from the silicon nitride film 30 becomes a silicon oxide film 32, and the polycrystalline silicon layer 28 covered with the silicon nitride film 30 remains without being substantially oxidized.
[0036]
Thus, the first polycrystalline silicon layer 28 a and the second polycrystalline silicon layer 28 b that are separated from each other are formed in the PNP transistor region 50. In addition, a third polycrystalline silicon layer 28c is formed in the NPN transistor region 60 (see FIG. 3C).
[0037]
Next, as a first conductivity type impurity implantation step, first conductivity type impurities are implanted into each of the first and second polycrystalline silicon layers (28a, 28b) in a plurality of times. In each of the second polycrystalline silicon layers (28a, 28b), the impurity concentration of the first conductivity type decreases from the surface side of the first and second polycrystalline silicon layers (28a, 28b) toward the semiconductor substrate 12. Form a concentration distribution.
[0038]
Specifically, in this configuration example, the silicon nitride film 30 remaining on the first to third polycrystalline silicon layers (28a, 28b, 28c) is removed by etching, and then p. ⁻ Boron (B), which is a p-type impurity as the first conductivity type, is ion energy 50 eV, implantation amount 1 × 10 5 from above with respect to the entire surface of the silicon substrate 12. ¹³ ~ ¹⁴ Ion / cm ² (Referred to as the first injection step). Accordingly, the first to third polycrystalline silicon layers (28a, 28b, 28c) become p-type semiconductor layers containing p-type impurities (see FIG. 4A).
[0039]
However, since the implantation amount of the p-type impurity (here, boron) in the first implantation step is basically determined in consideration of the speed performance of the NPN transistor, from the viewpoint of manufacturing the PNP transistor. There may be cases where the injection amount is not suitable.
[0040]
Therefore, in the present invention, a plurality of implantation steps are performed on the first and second polycrystalline silicon layers (28a, 28b).
[0041]
Therefore, the second implantation step is performed by, for example, p ⁻ Forming a resistance member required for an integrated circuit in a region outside the PNP / NPN transistor region (50, 60) on the silicon substrate 12 by injecting p-type impurities into polycrystalline silicon (polysilicon resistance forming step); Do it at the same time.
[0042]
Accordingly, boron has an ion energy of 20 to 30 eV and an implantation amount of 1 × 10 6 with respect to the first to third polycrystalline silicon layers (28a, 28b, 28c). ¹³ ~ ¹⁴ Ion / cm ² Inject with. As described above, it is desirable that the implantation step after the first implantation step is also used without any increase in the number of steps if it is also used as one of other manufacturing steps such as other integrated circuits provided on the same substrate.
[0043]
By performing the implantation process a plurality of times in this way, the p-type impurity concentration in each of the first and second polycrystalline silicon layers (28a, 28b) is the surface of the first and second polycrystalline silicon layers (28a, 28b). P from the side ⁻ A concentration distribution that decreases toward the mold silicon substrate 12 is formed. In the first and second polycrystalline silicon layers (28a, 28b), n ⁻ The implantation conditions are preferably set so that the p-type impurity concentration in the vicinity of the epitaxial layer 16 is sufficiently low, while the p-type impurity concentration on the surface side is sufficiently high. Then, the characteristic improvement of this semiconductor device obtained through a post process can be realized more remarkably.
[0044]
Then n ⁻ Of the epitaxial layer 16, p for the lead electrode ⁺ The thermal oxide film 18 and the silicon oxide film 32 above a part of the region adjacent to the mold diffusion region 34 are removed by etching, and the n ⁻ A part of the epitaxial layer 16 is exposed. Then exposed n ⁻ Boron is implanted into the epitaxial layer 16 and p ⁺ A portion to be the p-type intrinsic base region 33 adjacent to the type impurity diffusion region 34 is formed. Thereafter, arsenic (As), which is an n-type impurity, is implanted into a part of the exposed surface region of the p-type intrinsic base region 33 with an ion energy of 50 eV and an implantation amount of 1 × 10. ¹⁶ Ion / cm ² P for the extraction electrode ⁺ N-type impurity diffusion region 34 ⁺ A portion to be a mold emitter region 35 is formed.
[0045]
Next, the first conductivity type impurities implanted into the first, second and third polycrystalline silicon layers (28a, 28b, 28c) are converted into the first, second and third polycrystalline silicon layers (28a, 28b, 28c) A predetermined amount is diffused in the lower second-conductivity-type impurity diffusion layer 15 to be spaced apart from the second-conductivity-type impurity diffusion layer 15 by a predetermined distance, and the impurity concentration of the first conductivity-type is the second conductivity-type. A portion to be a P-type emitter region 36 a and a portion to be a P-type collector region 36 b having a concentration distribution that decreases from the surface side of the impurity diffusion layer 15 toward the semiconductor substrate 12 are formed. Also, the lead electrode p ⁺ A portion to be a mold diffusion region is also formed.
[0046]
Then, p-type impurities (for example, boron) in the first, second and third polycrystalline silicon layers (28a, 28b, 28c) are n. ⁻ Thermal diffusion is performed on the type epitaxial layer 16.
[0047]
By this annealing treatment, the p-type impurity concentration contained in the first, second and third polycrystalline silicon layers (28a, 28b, 28c) is n. ⁻ P from the surface side of the epitaxial layer 16 ⁻ It is diffused by forming a concentration distribution that decreases toward the mold silicon substrate 12. Thus, the p-type emitter region 36a and the p-type collector region 36b are formed in the PNP transistor region 50. The NPN transistor region 60 has a lead electrode p. ⁺ Type diffusion region 34, p-type intrinsic base region 33, and n ⁺ The type emitter region 35 is formed (note that the impurity concentration distribution of the p type emitter region 36a and the P type collector region 36b is p from the surface side of each region. ⁻ Strictly speaking, a high concentration (p ⁺ ) To low concentration (p ⁻ ), But here is generally referred to as p-type. ). In this way, the structure 37 is obtained (see FIG. 4B).
[0048]
The impurity concentration distributions in the p-type emitter region 36a and the P-type collector region 36b depend on the impurity concentration distributions in the first and second polycrystalline silicon layers (28a, 28b) before the annealing process. That is, the diffusion state of the p-type emitter region 36a and the P-type collector region 36b can be controlled by appropriately adjusting the amount of impurities implanted into the first and second polycrystalline silicon layers (28a, 28b) each time. it can.
[0049]
Next, as an electrode layer forming step, a first electrode layer is formed on the first polycrystalline silicon layer 28a, and a second electrode layer is formed on the second polycrystalline silicon layer 28b.
[0050]
Specifically, after covering the entire surface of the structure 37 with a silicon oxide film 38 as an intermediate oxide film (not shown), an electrode layer is formed on the silicon oxide film 38 in the PNP / NPN transistor region (50, 60). Patterning for forming is performed. Thus, in the PNP transistor region 50, the first and second polycrystalline silicon layers (28a, 28b) and n ⁺ The mold base drawer region 26a is exposed. In the NPN transistor region 60, the third polycrystalline silicon layer 28c, n ⁺ Type emitter regions 35 and n ⁺ The mold collector extraction region 26b is exposed.
[0051]
Then p ⁻ After an electrode layer made of aluminum (Al) is formed on the entire surface of the mold silicon substrate 12 (not shown), etching is performed so that the electrode layer remains only on each of the exposed surfaces described above. Thus, in the PNP transistor region 50, the first electrode layer 40a on the first polycrystalline silicon layer 28a, the second electrode layer 40b on the second polycrystalline silicon layer 28b, and n ⁺ Third electrode layers 40c are respectively formed on the mold base lead regions 26a. The NPN transistor region 60 includes a third polycrystalline silicon layer 28c, n ⁺ Type emitter regions 35 and n ⁺ Electrode layers (42, 44, 46) are formed on the mold collector lead region 26b, respectively. Thus, a PNP transistor which is a semiconductor device is completed (see FIG. 1).
[0052]
As is apparent from the above description, according to this embodiment, the p-type impurity is injected into the first and second polycrystalline silicon layers (28a, 28b) in a plurality of times, so that the PNP transistor 50 In the P-type emitter region 36a and the P-type collector region 36b, the p-type impurity concentration is p. ⁻ A concentration distribution that decreases toward the mold silicon substrate 12 is formed.
[0053]
As a result, for example, the initial implantation amount into the first and second polycrystalline silicon layers (28a, 28b) is controlled to be smaller than the conventional implantation amount in which only one implantation is performed. , Each of the P-type emitter region 36a and the P-type collector region 36b and n ⁻ The p-type impurity concentration in the junction region with the type epitaxial layer 16 can be reduced. Therefore, it is possible to obtain a semiconductor device in which the expansion of each of the P-type emitter region 36a and the P-type collector region 36b is substantially suppressed and the parasitic capacitance is reduced.
[0054]
Therefore, a transistor having the same frequency characteristics as before can be obtained by a base region having a region (or width) equivalent to that of the conventional one, and further downsizing and high integration can be realized.
[0055]
Further, a sufficient impurity concentration can be obtained even after the P-type emitter region 36a and the P-type collector region 36b are formed on the surface side of the first and second polycrystalline silicon layers (28a, 28b) by the p-type impurity implantation multiple times. Can be retained.
[0056]
Therefore, in the PNP transistor, the contact resistance, which is a parasitic resistance between the first polycrystalline silicon layer 28a and the first electrode layer 40a and between the second polycrystalline silicon layer 28b and the second electrode layer 40b, is conventionally increased. There is no concern to increase than.
[0057]
Moreover, each manufacturing process of the PNP transistor can be performed without increasing the number compared to the prior art by combining it with any one of the manufacturing processes of other integrated circuits formed on the same substrate.
[0058]
<Second Embodiment>
A method for manufacturing a field effect transistor according to the second embodiment of the present invention will be described with reference to FIGS.
[0059]
In the second embodiment, by performing the first conductivity type region forming step before the polycrystalline silicon layer forming step in the first embodiment, the impurity implantation is performed a plurality of times in the first conductivity type impurity implantation step. The main difference is that there is no need to do it actively. Hereinafter, this difference will be mainly described. The same components as those already described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0060]
As shown in FIG. 5, the semiconductor device 100 of this embodiment is mainly different from the first embodiment in the configuration of the PNP transistor region 50.
[0061]
That is, the PNP transistor region 50 includes n of the second conductivity type impurity diffusion layers 15. ⁻ A P-type emitter region 51 of the PNP transistor is formed in the surface region of the type epitaxial layer 16. Also, n from the surface side of the P-type emitter region 51 ⁺ An n-type intrinsic base region 52 is formed at a depth reaching the mold buried diffusion layer 14. A part of the surface region of the P-type emitter region 51 and the n-type intrinsic base region 52 is provided with a pP for the lead electrode of the PNP transistor ⁺ Mold diffusion regions 53a and p ⁺ In this configuration, the mold collector region 53b is formed at a predetermined distance.
[0062]
Next, a method for manufacturing the semiconductor device 100 of this embodiment will be described below.
[0063]
First, the laminated body forming process is performed in the same manner as the laminated body forming process of the first embodiment (see FIGS. 2A to 2C).
[0064]
In this embodiment, as the first conductivity type region forming step, the first conductivity type region is formed by diffusing the first conductivity type impurity in a predetermined region on the surface side of the second conductivity type impurity diffusion layer 15. .
[0065]
Specifically, a step of forming a p-type impurity region as a first conductivity type region in the PNP transistor region 50 is performed. ⁻ This can be performed at the same time as the step of forming a subcontact which is a region from which the potential of the silicon substrate 12 is drawn (subcontact formation step).
[0066]
Therefore, after forming a resist film 48 on the entire surface of the thermal oxide film 18 (not shown), a p-type impurity diffusion region is formed as a first conductivity type region in the PNP transistor region 50 with respect to the resist film 48. Patterning is performed. Thereafter, n from above the thermal oxide film 18 exposed by this patterning. ⁻ The p-type impurity boron is ion energy of 100 eV and the implantation amount is 1 × 10 4 with respect to the epitaxial layer 16. ¹² ~ ¹³ Ion / cm ² Inject with n ⁻ A p-type impurity diffusion region 51 as an emitter region of the PNP transistor is formed in the type epitaxial layer 16 (see FIG. 6A).
[0067]
Thereafter, in this embodiment, after the resist film 48 is removed and a new resist film 49 is formed, the npn transistor region 60 is formed in the npn transistor region 60 as already described in the first embodiment. ⁺ Simultaneously with the step of forming the mold collector extraction region 26b, the PNP transistor region 50 has n ⁺ A step of forming the mold base drawing region 26a is performed. Furthermore, in this embodiment, after removing the resist film 49, a new resist film (not shown) is formed, penetrates the p-type emitter region 51, and n ⁺ An n-type intrinsic base region 52 of the PNP transistor is formed at a depth reaching the buried type diffusion layer 14 (see FIG. 6B).
[0068]
Thereafter, after the polycrystalline silicon layer forming step is performed in the same manner as the polycrystalline silicon forming step in the first embodiment, the first conductivity type impurity implantation step is performed in the same manner as in the first embodiment. In the embodiment, the steps up to the first implantation step described above are performed, and the implantation conditions at this time are ion energy 50 eV and implantation amount 1 × 10. ¹⁵ Ion / cm ² It is.
[0069]
Thereafter, the emitter region / collector region forming step is performed in the same manner as the emitter region / collector region forming step of the first embodiment, and a part of the surface region of the P-type emitter region 51 in the PNP transistor region 50 is formed. , P for lead electrode of PNP transistor ⁺ A mold diffusion region 53a is formed. In addition, a part of the surface region of the n-type intrinsic base region 52 has a PNP transistor p ⁺ Type collector region 53b (both are higher in concentration than p type impurity region 51; ⁺ Marked as a mold. ). Thereafter, in the same manner as the electrode layer forming step of the first embodiment, the electrode layer forming step is performed to complete a PNP transistor which is a semiconductor device (see FIG. 5).
[0070]
As is clear from the above description, in this embodiment, p for the extraction electrode is used. ⁺ Mold diffusion regions 53a and p ⁺ A p-type emitter region 51 is formed in a region outside the type collector region 53b. As a result, n ⁻ The type epitaxial layer 16 has a p-type impurity concentration of p. ⁻ A concentration distribution that decreases toward the mold silicon substrate 12 is formed.
[0071]
Further, by implanting a sufficient implantation amount into the surface side of the first and second polycrystalline silicon layers (28a, 28b) by one implantation step, p ⁺ Mold diffusion regions 53a and p ⁺ A sufficient impurity concentration can be maintained even after the formation of the mold collector region 53b.
[0072]
Therefore, the semiconductor device 100 of this embodiment can obtain the same effect as the semiconductor device 10 of the first embodiment.
[0073]
Furthermore, in this embodiment, even if the mask alignment accuracy for the resist film 48 is somewhat low, n ⁻ A p-type impurity concentration distribution can be formed in the type epitaxial layer 16. Therefore, since highly accurate mask alignment is not required, manufacturing can be simplified.
[0074]
As mentioned above, this invention is not limited only to the combination of embodiment mentioned above. Therefore, the present invention can be applied by combining suitable conditions at any suitable stage.
[0075]
For example, the n-type impurity and the p-type impurity are not limited to the above, and can be arbitrarily selected according to the purpose and design.
[0076]
【The invention's effect】
As is apparent from the above description, according to the present invention, the first conductivity type impurity concentration is the first conductivity type in the first conductivity type emitter region and the collector region formed in the second conductivity type impurity diffusion layer. A concentration distribution that decreases toward the semiconductor substrate is formed.
[0077]
As a result, the first conductivity type impurity concentration in the junction region between the second conductivity type impurity diffusion layer and the emitter region and the collector region can be reduced as compared with the prior art. Therefore, since the expansion of the emitter region and the collector region is substantially suppressed, a semiconductor device with reduced parasitic capacitance can be obtained.
[0078]
Further, the base region having the region equivalent to the conventional one can obtain a semiconductor device in which the same frequency characteristic as that of the conventional device is ensured, and can realize miniaturization and high integration.
[0079]
In the present invention, a sufficient impurity concentration can be maintained on the surface sides of the first and second polycrystalline silicon layers even after the emitter region and the collector region are formed.
[0080]
Therefore, there is no concern that the contact resistance, which is a parasitic resistance between the first polycrystalline silicon layer and the first electrode layer and between the second polycrystalline silicon layer and the second electrode layer, is increased as compared with the conventional case.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining a semiconductor device according to a first embodiment of the present invention;
FIGS. 2A to 2C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to the first embodiment of the invention; FIGS.
FIGS. 3A to 3C are cross-sectional views for explaining a manufacturing process of the semiconductor device according to the first embodiment of the invention; FIGS.
FIGS. 4A and 4B are cross-sectional views for explaining a manufacturing process of the semiconductor device according to the first embodiment of the invention; FIGS.
FIG. 5 is a cross-sectional view for explaining a semiconductor device according to a second embodiment of the present invention.
6A and 6B are cross-sectional views for explaining a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
[Explanation of symbols]
10, 100: Semiconductor device
12: p ⁻ Type silicon substrate (first conductivity type semiconductor substrate)
14: n ⁺ Mold embedded diffusion layer
15: Second conductivity type impurity diffusion layer
16: n ⁻ Type epitaxial layer
17: Laminate
18: Thermal oxide film
19: Trench groove
20: Boron (first conductivity type impurity) implantation region
22: Silicon oxide film
23: Device isolation oxide film
24, 48, 49: Resist film
26a: n ⁺ Die base drawer area
26b: n ⁺ Die collector drawer area
27, 37: Structure
28: Polycrystalline silicon (polysilicon) layer
28a: first polycrystalline silicon layer
28b: second polycrystalline silicon layer
28c: third polycrystalline silicon layer
30: Silicon nitride film
32, 38: Silicon oxide film
33: p-type intrinsic base region
34: p for extraction electrode ⁺ Mold diffusion region
35: n ⁺ Emitter region
36a: p-type emitter region
36b: p-type collector region
40a: first electrode layer
40b: second electrode layer
40c: third electrode layer
42, 44, 46: electrode layer
50: PNP transistor region
51: p-type emitter region
52: n-type intrinsic base region
53a: p for lead electrode ⁺ Mold diffusion region
53b: p ⁺ Type collector area
60: NPN transistor region

Claims (4)

A laminated body forming step of forming a laminated body by providing a second conductive type impurity diffusion layer on the first conductive type semiconductor substrate;
Forming a first polysilicon layer and a second polysilicon layer separated by a predetermined distance on the second conductivity type impurity diffusion layer; and
Impurities of a first conductivity type are implanted in each of the first and second polycrystalline silicon layers in a plurality of times, and the first conductivity type is introduced into each of the first and second polycrystalline silicon layers. A first conductivity type impurity implantation step for forming a concentration distribution such that the impurity concentration decreases from the surface side of the first and second polycrystalline silicon layers toward the first conductivity type semiconductor substrate;
The first conductivity type impurities implanted into the first and second polycrystalline silicon layers are diffused by a predetermined amount in the second conductivity type impurity diffusion layer below the first and second polycrystalline silicon layers. The second conductivity type impurity diffusion layer is spaced apart by a predetermined distance, and the first conductivity type impurity concentration is from the surface side of the second conductivity type impurity diffusion layer toward the first conductivity type semiconductor substrate. An emitter region / collector region forming step of forming an emitter region and a collector region having a concentration distribution that decreases;
After the emitter region / collector region forming step, forming an electrode layer for forming a first electrode layer on the first polysilicon layer and a second electrode layer on the second polysilicon layer A method for manufacturing a semiconductor device, comprising: a step. A laminated body forming step of forming a laminated body by providing a second conductive type impurity diffusion layer on the first conductive type semiconductor substrate;
A first conductivity type region forming step of forming a first conductivity type region by diffusing a first conductivity type impurity in a predetermined region on the surface side of the second conductivity type impurity diffusion layer;
Forming a first polysilicon layer and a second polysilicon layer separated by a predetermined distance on the first conductivity type region; and
A first conductivity type impurity implantation step of implanting a first conductivity type impurity into each of the first and second polycrystalline silicon layers;
The first conductivity type impurity implanted into the first and second polycrystalline silicon layers is diffused by a predetermined amount into the first conductivity type region below the first and second polycrystalline silicon layers, and predetermined. An emitter region and a collector region that are spaced apart from each other are formed, and the impurity concentration of the first conductivity type is increased in the second conductivity type impurity diffusion layer from the surface side of the second conductivity type impurity diffusion layer. An emitter region / collector region forming step for forming an emitter region and a collector region having a concentration distribution that decreases toward the semiconductor substrate;
After forming the emitter region / collector region, an electrode layer is formed to form a first electrode layer on the first silicon polycrystalline layer and a second electrode layer on the second polycrystalline silicon layer. A method for manufacturing a semiconductor device, comprising: a step. A second conductivity type impurity diffusion layer is formed on the first conductivity type semiconductor substrate, and the second conductivity type impurity diffusion layer has a first conductivity type emitter region and a collector region spaced apart from each other by a predetermined distance. Each of the emitter region and the collector region is formed such that the impurity concentration of the first conductivity type decreases from the surface side of the second conductivity type impurity diffusion layer toward the first conductivity type semiconductor substrate. A semiconductor device characterized by having a high concentration distribution. 4. The semiconductor device according to claim 3, wherein a first polycrystalline silicon layer containing a first conductivity type impurity is contained on the emitter region, and a first conductivity type impurity is contained on the collector region. A second polycrystalline silicon layer is formed at a predetermined distance, a first electrode layer is formed on the first polycrystalline silicon layer, and a second electrode layer is formed on the second polycrystalline silicon layer. Each of the first and second polycrystalline silicon layers is formed at a predetermined distance from the surface side of the first and second polycrystalline silicon layers. A semiconductor device having a concentration distribution that decreases toward the first conductivity type semiconductor substrate.

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