JP2004259400A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the burst operation of a semiconductor memory is restricted by the length of column addresses and data access over a plurality of words is difficult. <P>SOLUTION: A semiconductor memory performs the burst operation by generating internally the request signal of refresh operations and is constituted so as to change column addresses and row addresses for accessing a memory core 24 during the burst operation. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device using a DRAM core requiring high-speed operation.
[0002]
2. Description of the Related Art Conventionally, a burst operation is performed to access a semiconductor memory device having a DRAM (Dynamic Random Access Memory) core at high speed. The burst operation accesses (writes / reads) data for each word by fixing a row address and changing a column address in synchronization with an external clock. Therefore, the burst length is limited to the length of the column address.
[0003]
2. Description of the Related Art In recent years, along with various uses of a semiconductor memory device, some users may require a burst operation having a burst length (Burst Length: BL length) equal to or longer than the length of a column address. is there. Therefore, there is a demand for a semiconductor memory device having a burst operation function capable of performing data access of a plurality of words beyond data access of each word.
[0004]
[Prior art]
Generally, a semiconductor memory device (memory) often performs a burst operation when high-speed access is required. The burst operation in this case means that an address given when a READ / WRITE command (read / write command) is input from the outside is used as an initial value, necessary addresses thereafter are generated internally, and an external signal (external clock) is used. CLK) to input and output data to and from the outside at high speed. An SDRAM (Synchronous DRAM) has such a function. (For example, refer to Patent Documents 1 to 6.)
In recent years, a burst length of a semiconductor memory device may require a burst length longer than the length of a column address. That is, as a burst operation of the semiconductor memory device, data access for a plurality of words may be required beyond data access for each word.
[0005]
[Patent Document 1]
JP-A-4-157693
[Patent Document 2]
JP-A-10-14073
[Patent Document 3]
JP-A-11-283385
[Patent Document 4]
JP-A-11-353874
[Patent Document 5]
JP 2000-11645 A
[Patent Document 6]
JP-A-2000-82287
[0006]
[Problems to be solved by the invention]
By the way, in order to realize a burst length (BL length) longer than the length of the column address, it is necessary to change the row address during the burst operation to switch the word line and continue the operation. In the case where a column signal (CL signal) is output a plurality of times at a shifted timing within one cycle, a CL signal of a plurality of CL signals (a signal for extracting cell data in a memory core after activation of a sense amplifier) as necessary. The word line must be switched between -CL signals or after all CL signals have been output.
[0007]
Further, when an asynchronous SRAM (Static Random Access Memory) interface (pseudo SRAM: Pseudo SRAM) is employed, since a burst operation must be performed while performing an internal refresh operation, generation of an internal refresh request and word line switching are performed. It is also necessary to deal with overlapping requests. Further, in the burst operation, it is necessary to operate the memory core at the end of the operation, so that the recovery time (the interval from the end of the operation to the start of the next operation) becomes longer.
[0008]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device which has a burst operation with virtually no restriction on the burst length and can minimize the recovery time.
[0009]
[Means for Solving the Problems]
According to the present invention, there is provided a semiconductor memory device which internally generates a refresh operation request signal and performs a burst operation, wherein a column address and a row address for accessing a memory core are changed during the burst operation. A semiconductor storage device having the features is provided.
[0010]
According to the semiconductor memory device of the present invention, by changing the column address and the row address for accessing the memory core during the burst operation, the burst operation with virtually no restriction on the burst length becomes possible.
[0011]
By the way, considering the data input / output timing to and from the memory core during the burst operation, the core operation has a certain free time (tCL). The semiconductor memory device according to the present invention performs the switching of the word line and the refresh operation using the idle time tCL. Further, when the column signal (CL signal) is output a plurality of times, the semiconductor memory device according to the present invention interrupts the word line switching between each CL signal according to the column address. Further, the semiconductor memory device according to the present invention gives priority to the word line switching when the occurrence of the internal refresh request and the occurrence of the word line switching request overlap. Furthermore, the semiconductor memory device according to the present invention reduces unnecessary operation at the end of operation to shorten the recovery time.
[0012]
As described above, according to the semiconductor memory device of the present invention, the word line switching and the refresh operation can be performed during the burst operation, and the burst operation with virtually no restriction on the burst length can be realized. Time can be minimized.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.
[0014]
FIG. 1 is a block diagram schematically showing an entire configuration of an embodiment of a semiconductor memory device according to the present invention.
[0015]
In FIG. 1, reference numeral 1 denotes a burst column signal generation circuit (burst CL generation circuit), 2 denotes a column signal output circuit (CL output circuit), and 3 denotes a word line switching request signal generation circuit (WL switching request signal generation circuit). ), 4 is a word line restart signal generation circuit (WL restart signal generation circuit), 5 is a refresh control circuit, 6 is a second column signal counter (CL2 counter), 7 is an unwritten write request signal generation circuit (unwritten write). WR request signal generation circuit), and reference numeral 8 denotes an unwritten write control circuit (unwritten WR control circuit). Reference numeral 9 denotes a precharge control circuit, 10 denotes a final write control circuit (final WR control circuit), 11 denotes a command generation circuit, 12 denotes a clock logic circuit (CLK logic circuit), and 13 denotes a burst length counter (BL counter). , 14 are a normal column signal generator (normal CL generator), 15 is a core control circuit, and 16 is an input / output address counter. Further, reference numeral 17 is a burst column timing signal generation circuit (burst CL timing signal generation circuit), 18 is an input / output data control circuit, 19 is a data latch, 20 is an address latch (ADD latch), and 21 is a column address counter ( CL address counter), 22 is an oscillator (OSC), 23 is an address decoder, and 24 is a memory core. FIG. 1 does not show all the connections between the circuit blocks.
[0016]
Here, the semiconductor memory device shown in FIG. 1 outputs two column signals (two CL signals: the first column signal CL1 and the second column signal CL2) in one cycle, and outputs four signals per one CL signal. This is a case in which data for a total of 8 words is read / written (READ / WRITE) by two CL signals (CL1 and CL2) for words, and as an example, READ (latency = 2) will be described. Latency = 2 means that a read command (READ command) is input and the first data is output to the outside from the second rising edge of the CLK counted from the rising edge of the first clock (CLK).
[0017]
Specifically, four words read by one CL signal are extracted, for example, one word each from four segments selected by addresses A00 and A01. At this time, the first column signal CL1 and the second column signal CL2 have different addresses A02, for example. Here, address A00 = A01 = A02 = data of low level “L” is “1” (data of the first word), and address A00 = A01 = A02 = high level “H” (“1” to “8”) (From the 1st word data to the 8th word data), if the address initial value is A00 = A01 = “H” and A02 = “L” (“4”), CL1 is “ Data "1" to "4" are read, and data "5" to "8" are read at CL2. At this time, the first data “1” to “3” are not output to the outside. The next CL signal is output from the CLK that outputs the data “8”. This operation continues until the BL length ends or until there is an EXIT command by changing / CE1 (chip enable terminal) from "L" to "H".
[0018]
The data of eight words “1” to “8” is read out from the memory core 24 to the data latch 19 and latched, and the input / output data control circuit is controlled in accordance with the output of the CL output circuit 2 (CL signal). The data is output from the data terminal (DQ) via the line 18.
[0019]
FIG. 2 is a block circuit diagram showing an example of a burst column signal generating circuit 1 and a column signal output circuit 2 in the semiconductor memory device of FIG. 1, and FIG. 3 is a waveform for explaining a basic read operation in the circuit of FIG. FIG.
[0020]
As shown in FIG. 2, the burst-related CL generation circuit 1 includes flip-flops 101 to 104, delay lines 105 and 106, and a plurality of logic gates. The CL output circuit 2 includes inverters 201 and 202 and a NAND gate. An output (/ cl) of the CL output circuit 2 is input to the burst-related CL generation circuit 1 via the delay line 200.
[0021]
As shown in FIGS. 2 and 3, when a command is input, the inputs (signals) / bact, wlhpp, and endmask of the burst-type CL signal generation circuit 1 are all "L", and the inputs / endwrp, / pbcl are "H" And the output (signal) / bcl is "H" and the output clmask is "L".
[0022]
When the chip enable signal / CE1 becomes "L", a READ command is issued, and the READ operation is started. The signal pcl is a pulse generated on an ordinary path from an external command (at the start of a burst operation), and is output at the fastest timing after the command is input, with timing from the rise of the word line WL. This signal pcl becomes the first CL signal / cl (first column signal CL1) via the CL output circuit 2. The signal pcl sets the flip-flop 101 in the burst CL generation circuit 1, and sets the nodes n01 and n02 to "H" and "L". The first column signal CL1 (/ cl) output from the CL output circuit 2 is delayed by the delay line 200, returned to the burst-related CL generation circuit 1 as a signal pcl2, and transferred to the node n04 via the NAND gate 107. (At this time, the node n03 is at “H”).
[0023]
The signal at node n04 sets flip-flop 102 and is delayed by delay line 105 to reset flip-flop 101, causing nodes n01 and n02 to go "L" and "H". Since the flip-flop 102 performs a self-reset after the delay by the delay line 106, the output becomes a pulse (/ bcl). Then, the signal / bcl becomes the second CL signal / cl (second column signal CL2) via the CL output circuit 2. Here, the signal pcl2 is generated again from the second column signal CL2, but since the node n01 in the burst-related CL generation circuit 1 is at "L", the node n04 remains at "H" and the signal / bcl is not output. The eight words read from the memory core 24 are latched by the data latch 19, and are output to the outside from the data terminal (DQ) via the input / output data control circuit 18 one word at a time at the rise of CLK. . The internal address holds an initial value, and thereafter is internally generated by a counter. A00 and A01 are degenerated, and when the CL signal is output, the internal address is incremented from A02.
[0024]
When the burst operation is continued, pcl is not output after the first CL1 output unless the rising operation of the word line WL is performed. Therefore, the burst CL timing signal generation circuit 17 outputs the data "8" CLK. / Pbcl is output, and flip-flops 101 and 102 are set. The flip-flop 102 outputs the same / bcl as the first second column signal CL2, and the signal / cl is output from the CL output circuit 2. In this case, the signal / cl is output from the next first column signal CL1. become. Thereafter, the next second ram CL2 is output in the same manner as described above.
[0025]
The above operation is continued until the chip enable signal / CE1 becomes "H" (EXIT).
[0026]
Next, a word line switching operation will be described.
[0027]
FIG. 4 is a block circuit diagram showing an example of a word line switching request signal generation circuit, a word line restart signal generation circuit, and a refresh control circuit in the semiconductor memory device of FIG. 1, and FIG. FIG. 6 is a waveform diagram (after CL2) for explaining the switching operation, and FIG. 6 is a waveform diagram (after CL1) for explaining the word line switching operation in the circuit of FIG.
[0028]
As shown in FIG. 4, the WL switching request signal generation circuit 3 includes a flip-flop 301 and a plurality of logic gates, and the WL restart signal generation circuit 4 includes flip-flops 401 and 402, delay lines 403 and 404, and The refresh control circuit 5 includes a plurality of logic gates, and includes flip-flops 501 to 503, a delay line 504, and a plurality of logic gates.
[0029]
First, in the burst-related CL signal generation circuit 1 shown in FIG. 2, it is assumed that the input (signal) / bact, wlchp, and endmask are all at low level "L", and the output (signal) / pbcl is at high level "H". I do. Addresses A02 to A06 indicate internally generated addresses of the columns (in a phase opposite to the external addresses). In the WL switching request signal generating circuit 3 shown in FIG. 4, it is assumed that the inputs endwr, ce1b, / actset are "H", the write, stop is "L", and the outputs wlchp, wlch are "L". Further, in the WL restart signal generation circuit 4 shown in FIG. 4, the input active is a signal that becomes “L” during activation of the memory core 24, the input stop is “L”, and the output / bact is “H”. In the refresh control circuit 5 shown in FIG. 4, the output refpre is “L”. It is assumed that the refresh control circuit 5 does not operate now.
[0030]
As shown in FIG. 5, when the word line is switched after the second column signal CL2, when the internal column addresses A02 to A06 output the signal CL2 (the signal / cl is output to the WL switching request signal generation circuit 3 shown in FIG. 4). At the time of input (at the time of input), when it becomes the highest level (all "L"), WLchp (pulse) and wlch (state signal) of the switching request signal are output from the WL switching request signal generating circuit 3 of FIG. Here, the signal wlch resets the word lines (WL-0, WL-1) and resets the core control circuit 15. Further, the signal wlchp sets the flip-flops 401 and 402 in the WL restart signal generation circuit 4 in FIG. However, the setting of the flip-flop 402 is later than the timing at which the flip-flop 401 is set by the delay line 403. When the flip-flop 401 is set, the node n05 in the WL restart signal generation circuit 4 shown in FIG. 4 becomes "L", and the flip-flop 402 waits for the output of the set information.
[0031]
During the activation of the memory core 24, the input active is at “L”, but at the timing when the reset of the core control circuit 15 ends, the input active is set at “H”. When active becomes “H”, the flip-flop 401 is reset, the node n05 becomes “H”, and a pulse (/ bact) having a width determined by the delay line 404 is output. The signal / bact activates the normal path of the operation of the memory core 24, becomes the signal / actset whose timing is adjusted by the delay line 400, and raises the word line. The row address is counted up by the signal / bact. At this time, the signal / bact is input to the burst-related CL signal generation circuit 1 shown in FIG.
[0032]
Since the node n02 in the burst-related CL signal generation circuit 1 is "H", the flip-flop 103 is set and the signal clmask becomes "H". Since the signal / actset is a signal on the normal path, pcl is output. Unnecessary / cl is generated when pcl is output. Therefore, when clmask is “H”, pcl is stopped in the CL output circuit 2 of FIG. As described above, after outputting the second column signal CL2, the word line is switched from WL-0 to WL-1, and the memory core 24 is in a standby state until the third column signal (the next first column signal CL1) is generated. It becomes. During that time, eight words of data held in the data latch 19 are sequentially output via the input / output data control circuit 18 in synchronization with the CLK. Note that the signal wlch is reset by the signal / actset, and the signal clmask is held until the output of the next column signal (CL signal).
[0033]
When the column address is counted up to the highest order by the second column signal CL2, it is necessary to switch the word line after outputting the third column signal (the next first column signal) CL1. In that case, it becomes as follows.
[0034]
The initial state of the signals other than the address is the same as the case where the word line is switched after the second column signal CL2. As shown in FIG. 6, when the first column signal CL1 is output, the signals wlchp and wlch are output, and the word lines (WL-0, WL-1) and the memory core 24 are reset as in FIG. The signal wlchp is input to the burst-system CL signal generation circuit 1 of FIG.
[0035]
Since the node n02 in the burst-related CL signal generation circuit 1 is "L", the flip-flop 104 is set and the node n03 is set to "L". Since the node n03 is "L", the signal pcl2 from the first column signal CL1 is stopped, and the second column signal CL2 is not output. As in FIG. 5, the signal / bact is output and the next word line (WL-1) rises. Since the signal clmask is “L”, the signal / cl is output from the normal path of / bact → / actset → pcl. This effectively becomes the second column signal CL2. The signal pcl2 is output from the second column signal CL2. However, since the node n02 in the burst-related CL signal generation circuit 1 of FIG. No signal is output. Thus, after the first column signal CL1 is output, the word line is switched from WL-0 to WL-1, and then the second column signal CL2 is output from the normal path. In the meantime, similarly to FIG. 5 described above, eight words of data held in the data latch 19 are sequentially output to the outside via the input / output data control circuit 18 in synchronization with CLK. Note that the signal wlch is reset by the signal / actset, and the signal clmask is held until the output of the next column signal.
[0036]
Next, the refresh operation will be described.
[0037]
FIG. 7 is a waveform diagram for explaining a refresh operation in the circuit of FIG.
[0038]
The input (signal) active of the refresh control circuit 5 shown in FIG. 4 is the same as the signal active input to the WL restart signal generation circuit 4, and the input (signal) ref is the internal ring oscillator (22). ) Is a refresh request signal periodically generated, and an input (signal) cl2cnt is a refresh operation pulse (details will be described later) generated from the second column signal CL2. It is assumed that the outputs (signals) reflect and refpre are at “L”. The initial state of input / output in the other circuits is the same as that in the description of the word line switching.
[0039]
First, when the refresh request signal ref is generated, the flip-flop 502 in the refresh control circuit 5 shown in FIG. 4 is set, and the node n06 becomes "H". At this time, since the word line is raised (the memory core 24 is activated), the signal active is at “L”, the node n07 of the flip-flop 501 is at “L”, and the node n06 is at “H” signal. Is waiting for output. In this state, when the second column signal CL2 is output, a signal cl2cnt is generated. The signal cl2cnt sets the flip-flop 503, and the signal refpre becomes “H”. The signal refpre resets the word line WL and the memory core 24, like the signal wlch at the time of switching the word line. Further, the flip-flops 401 and 402 in the WL restart signal generation circuit 4 in FIG.
[0040]
When the memory core 24 is reset and the signal active changes to “H”, the flip-flop 501 changes to “H” and the signal reflect is output as a pulse whose width is determined by the delay line 504. At this time, the signal refpre is also reset. The signal “refact” becomes an activation signal for the refresh operation, activates a word line to be refreshed, and the refresh operation is performed. Note that the signal active becomes "H" before the refresh operation. During that time, since the signal refpre maintains "H", the flip-flop in the WL restart signal generation circuit 4 of FIG. The set state of the loop 401 is maintained.
[0041]
When the refresh operation is completed (auto precharge) and the signal active becomes “H”, the signal / bact is output and the word line is restarted as in the case of switching the word line (the row address is the same as before the refresh). I do. At this time, the signal pcl is output from the normal path, but the signal / cl is not "H" since the signal clmask becomes "H" as in FIG. When the word line is switched, the signal wlch is "H", so that neither the signal reflect nor the signal refpre is output.
[0042]
As described above, if there is a refresh request, the refresh operation can be performed during the idle time (tCL) after the CL signal is output, and then the word line can be restarted.
[0043]
Next, the signal cl2cnt input to the refresh control circuit 5 of FIG. 4 will be described.
[0044]
FIG. 8 is a block circuit diagram showing an example of a second column signal counter in the semiconductor memory device of FIG. 1, and FIG. 9 is a waveform diagram for explaining a count operation of the second column signal in the circuit of FIG.
[0045]
As shown in FIG. 8, the CL2 counter 6 includes a counter 601, delay lines 602 and 603, and a plurality of logic gates.
[0046]
By the way, the first operation of the memory core in the burst read operation is started asynchronously with the CLK (clock), so that the interval between the CL signal (Oram signal) at that time and the CL signal from the next CLK is narrowed. There is. Since the refresh operation cannot be performed within the narrowed interval, the refresh operation needs to be performed after the CL signal is output from CLK.
[0047]
That is, as shown in FIGS. 8 and 9, the CL2 counter 6 always counts the second column signal CL2, outputs the signal cl2cnt when the second column signal CL2 is output, and then outputs the second column signal CL2. The signal cl2cnt is output at CL2. When a word line switching request occurs, the counter 601 is reset by the signal wlch, and the word line switching is prioritized without outputting the signal cl2cnt. The counter 601 is reset by a command pulse (CMD) output at the start of the burst operation.
[0048]
Next, the end of the burst read (burst READ) operation will be described.
[0049]
FIG. 10 is a block circuit diagram showing an example of an unwritten write request signal generation circuit, an unwritten write control circuit, and a precharge control circuit in the semiconductor memory device of FIG. Here, it is assumed that the inputs (signals) stop, endwr, wlch, and refpre are at “L”.
[0050]
The signal ce1b is a signal that becomes “L” when the burst length ends or an EXIT command is generated (the chip enable signal / CE1 changes from “L” to “H”). When the second column signal CL2 is generated (however, in the case of ending with the first column signal CL1, from the first column signal CL1), a signal / rst is output after the completion of cell restoration in the memory core 24, and The flip-flop 901 in the precharge control circuit 9 shown in FIG. In this state, when the burst length ends or an EXIT command is generated, the signal ce1b and the node n13 become "L", the precharge signal / pre is output, the word line WL and the memory core 24 are reset, and the burst operation is performed. finish. When a word line switching request or a refresh operation request is made, the signals wlch and refpre become “H”, respectively, and similarly, the signal / pre is generated to perform the reset operation. The flip-flop 901 in the precharge control circuit 9 is reset by the next CL signal (/ pbcl).
[0051]
Next, the end of the burst write (burst WRITE) operation will be described. The basic operation is the same as during reading.
[0052]
In the write operation, contrary to the read operation, eight words of data are taken in synchronously with the CLK, and the CL signal is generated from the rising edge of the CLK when the data is held (when A00 = A01 = A02 = “H”). The first column signal CL1 outputs data “1” to “4” (the first word data to the fourth word data), and the second column signal CL2 outputs “5” to “8” data ( 5th word data to 8th word data) are written into the cells of the memory core 24.
[0053]
This continues until the burst length (BL length) ends or until there is an EXIT command by changing the chip enable signal (chip enable terminal) / CE1 from "L" to "H". Here, the write operation is significantly different from the read operation in the case where the operation is terminated with a CLK other than the data capture CLK of “8”. In the case of reading, the operation circuit including the memory core may be immediately reset at the end of the BL length or when the EXIT command is generated. However, in the case of writing, if the BL length ends or an EXIT command occurs when the data of “7” is received, the CL signal for writing “1” to “7” is unrelated to CLK (asynchronously). Need to be generated.
[0054]
FIG. 11 is a waveform diagram (part 1) for explaining the unwritten write operation in the circuit of FIG. 10 and shows a case where the write operation of data “5” ends. Here, the input (signal) stop of the unwritten WR request signal generation circuit 7 in FIG. 10 is "L", and write is a state signal which becomes "H" at the time of writing.
[0055]
The signal WR-CMD input to the unwritten WR request signal generation circuit 7 and the unwritten WR control circuit 8 in FIG. 10 is a command pulse output at the start of the writing operation. At the time of writing, the flip-flop 701 of the WR request signal generation circuit 7 and the flip-flop 801 of the WR control circuit 8 are set by the signal WR-CMD. It is assumed that the output (signal) endwr of the unwritten WR control circuit 8 in FIG. 10 is “H”, and the output / endwrp and endact of the unwritten WR request signal generation circuit 7 are “H”. The flip-flop 701 of the WR request signal generation circuit 7 is reset by the signal / pbcl immediately before the output of the CL signal, but is reset by the signal / rst. Further, the flip-flop 702 of the WR request signal generation circuit 7 is set by the signal pcl output when the word line WL rises, and the node n11 is at "H".
[0056]
In this state, when the chip enable signal / CE1 becomes “H” (when an EXIT command is input), if wlch = refpre = “L”, endwr = “H”, but the precharge control shown in FIG. Since the node n13 in the circuit 9 is "H", the signal / pre is not output. On the other hand, since the flip-flop 701 of the WR request signal generation circuit 7 is set and the node n10 is at “H”, if ce1b = “L” (and stop = wlch = refpre = “L”), FIG. A pulse whose width is determined by the delay line 704 is output from the unwritten WR request signal generation circuit 7 as a signal / endwrp. The signal / endwrp sets the flip-flop 703 and at the same time sets the signal endact to “L” (the signal endact will be described later).
[0057]
The signal / endwrp resets the flip-flop 901 in the precharge control circuit 9 and further resets the flip-flop 801 of the unwritten WR control circuit 8 after a delay time due to the delay line 802 in the unwritten WR control circuit 8. The signal endwr is set to “L”. Further, the signal / endwrp is input to the burst-related CL signal generation circuit 1 of FIG. 2 to generate a first column signal CL1, perform a write operation of data “1” to “4”, and subsequently, perform a second operation. The column signal CL2 is generated in the same manner as the normal burst operation, and the data "5" write operation is performed. Thereafter, a signal / rst is generated from the second column signal CL2, and since endwr = “L” and ce1b = “H”, a signal / pre is generated, a reset operation is performed, and the burst write operation ends.
[0058]
The last unwritten write operation is performed asynchronously with CLK. In the above, the unwritten WRITE operation has been described. However, there is a problem that the recovery time is long as it is. The reason will be described below.
[0059]
(1) If the process ends with writing of data “1” to “4”, the second column signal CL2 is output even though it is not necessary.
[0060]
(2) In the case of ending with writing of data “8”, the CL signal is output again from the EXIT command as a remaining write even though the CL signal is output from CLK and writing is performed up to data “8”. .
[0061]
(3) There is a case where a word line switching request is generated from the CL signal of the unwritten write, and in that case, the word line switching operation is performed without necessity.
[0062]
Therefore, the semiconductor memory device of the present embodiment is configured as follows in order to solve the above problem.
[0063]
FIG. 12 is a circuit diagram showing an example of a final write control circuit in the semiconductor memory device of FIG. 1. FIGS. 13 and 14 illustrate an unwritten write operation (operation after solving a problem) in the circuits of FIGS. FIG. Here, FIG. 13 shows a waveform when EXIT is performed by writing data “4”, and FIG. 14 shows a waveform when EXIT is performed by writing data “8”.
[0064]
The input (signal) clkp of the final WR control circuit 10 is a pulse generated from the rise of the CLK during the burst operation, and becomes “L” after EXIT. The signal WA02 is an internal address A02 counted up by CLK (the timing of counting up is different from that of the internal A02 for the CL signal). In this circuit, the signal clkp always takes in and latches the signal WA02.
[0065]
As shown in FIG. 14, when EXIT is performed by writing data “4”, since the node n14 is “L” (A02 = “L” is latched), when the signal endact is output at the time of the unwritten write, the signal endmask is output. Becomes "H". The signal endmask is input to the burst-system CL signal generation circuit 1 of FIG. 2, and stops the signal pcl2 generated from the first column signal CL1 and stops the output of the second column signal CL2. At this time, if endmask = “H”, the signal / rst is generated from the first column signal CL1 (a circuit diagram is omitted), and the word line WL and the memory core 24 are reset from the first column signal CL1 to operate. To end. The signal endmask is held until the next command is generated.
[0066]
Next, as shown in FIG. 14, when EXIT is performed by writing data "8", node n14 is at "H" and signal / pbcl is output from CLK of data "8", so flip-flop 1001 is set. As a result, the signal stop becomes “H”.
[0067]
The signal stop is input to the unwritten WR request signal generation circuit 7 in FIG. 10 to stop the generation of the signal / endwrp. The signal stop is input to the precharge control circuit 9 in FIG. 10 and invalidates the signal endwr. Therefore, if ce1b = “L”, a signal / pre is generated, and the word line WL and the memory core 24 are reset. And terminate the operation. Note that the signal stop is held until the next burst operation. As described above, when EXIT is performed by writing the data “8”, the remaining writing is not performed.
[0068]
The signal endwr is input to the WL switching request generation circuit 3 shown in FIG. 4 so that a word switching request (wlchp) is not output during unwritten writing.
[0069]
Further, when the signal stop is input to the WL restart signal generation circuit 4 in FIG. 4 and EXIT is performed by writing data “8”, the word line WL is not restarted. In the case where EXIT is performed by writing data “8” and a word switching request is generated, the flip-flop 301 in the WL switching request generation circuit 3 in FIG. Since stop becomes impossible (wlch = “H”), when stop = “H” and ce1b = “L”, the flip-flop 301 is reset to set the signal wlch to “L”.
[0070]
As described above, according to the embodiment of the semiconductor memory device according to the present invention, the switching of the word line and the refresh operation during the burst operation are performed, thereby enabling the burst operation with virtually no restriction on the burst length and the recovery time. Can be minimized.
[0071]
(Supplementary Note 1) A semiconductor memory device which internally generates a request signal for a refresh operation and performs a burst operation, wherein a column address and a row address for accessing a memory core are changed during the burst operation. Semiconductor storage device.
[0072]
(Supplementary Note 2) The semiconductor memory device according to Supplementary Note 1, wherein the column address selects a sense amplifier connected to a bit line, and the row address selects a word line.
[0073]
(Supplementary Note 3) In the semiconductor memory device according to Supplementary Note 2, in the burst operation, the external address is used as an initial address, the column address and the row address are changed in synchronization with an external clock, and the memory core is accessed. A semiconductor memory device which inputs / outputs a plurality of data at a time and inputs / outputs data from / to the outside in synchronization with the external clock.
[0074]
(Supplementary Note 4) In the semiconductor memory device according to Supplementary Note 1, during the burst operation, an address is internally generated, a lower bit of the address is set in the column address, and an upper bit of the address is set in the row address. When the column address becomes the highest, the row address is incremented by the next external clock.
[0075]
(Supplementary Note 5) In the semiconductor memory device according to Supplementary Note 1, the semiconductor memory device first activates a word line, outputs a column signal in synchronization with an external clock during the burst operation, and inputs the data. A semiconductor memory device that performs output.
[0076]
(Supplementary Note 6) The semiconductor memory device according to any one of Supplementary Notes 1 to 5, wherein the memory core is a DRAM memory core that requires a refresh operation.
[0077]
(Supplementary note 7) The semiconductor memory device according to supplementary note 6, wherein the word line is not reset until the column address becomes the highest order or a refresh operation is performed.
[0078]
(Supplementary Note 8) In the semiconductor memory device according to Supplementary Note 7, when the column address becomes the highest order, a word line switching request signal is generated from the column signal at that time, and after the cell restore time in the memory core is secured, A semiconductor memory device, comprising resetting a word line and switching to a word line of a next row address after a preset time interval.
[0079]
(Supplementary Note 9) In the semiconductor memory device according to supplementary note 8, the word line switching process after the column address becomes the highest order can be performed within a predetermined number of times of the external clock for reading data corresponding to the word line. A semiconductor memory device.
[0080]
(Supplementary Note 10) The semiconductor memory device according to supplementary note 1, wherein the semiconductor memory device outputs a first column signal in a burst read operation at the highest speed asynchronously with an external clock.
[0081]
(Supplementary Note 11) In the semiconductor memory device according to Supplementary Note 1, if the first column address in the burst read operation is other than the highest order, the highest order-1 or the highest order-2 of the column, A semiconductor memory device which continuously outputs data even during line switching and maintains synchronization of an external clock.
[0082]
(Supplementary Note 12) In the semiconductor memory device according to supplementary note 11, in the case of a burst write operation, the semiconductor memory device always takes in external data continuously in synchronization with the external clock even during switching of the word line. A semiconductor memory device characterized by the following.
[0083]
(Supplementary Note 13) In the semiconductor memory device according to supplementary note 1, the semiconductor memory device outputs a column signal twice, that is, a first column signal and a second column signal, twice when extracting data from the memory core. A semiconductor storage device characterized by being taken out separately.
[0084]
(Supplementary Note 14) In the semiconductor memory device according to supplementary note 13, in the case of a burst write operation, the semiconductor memory device always takes in external data continuously in synchronization with the external clock even during the switching of the word lines. A semiconductor memory device characterized by the following.
[0085]
(Supplementary Note 15) In the semiconductor memory device according to Supplementary Note 13, the first column signal is output in synchronization with the external clock, and the second column signal is provided from the first column signal by an internal delay circuit. A semiconductor memory device which is output after a predetermined time interval.
[0086]
(Supplementary Note 16) In the semiconductor memory device according to Supplementary Note 15, when a row address is different between the first column signal output and the second column signal output, the output of the first column signal and the second column signal are different. A semiconductor memory device, wherein the word line is switched between the output of a first column signal and the output of a second column signal.
[0087]
(Supplementary Note 17) The semiconductor memory device according to supplementary note 16, further comprising:
A circuit for stopping the output of the second column signal generated by the internal delay circuit. After switching the word line, a column signal is generated on the same path as the normal path after the next word line rises. A semiconductor memory device used as a second column signal.
[0088]
(Supplementary Note 18) The semiconductor memory device according to supplementary note 17, further comprising:
A semiconductor memory device comprising: a circuit for stopping the output of the third column signal when the third column signal is used by the internal delay circuit.
[0089]
(Supplementary Note 19) In the semiconductor memory device according to Supplementary Note 15, a row address is equal at the time of outputting the first column signal and at the time of outputting the second column signal, and the row address changes at the time of outputting the next column signal. In the case, the word line is switched from a second column signal before the row address changes.
[0090]
(Supplementary Note 20) The semiconductor memory device according to supplementary note 19, further comprising:
A semiconductor memory device, comprising: a circuit for stopping a column signal when a column signal is to be output after the word line is restarted at the next row address.
[0091]
(Supplementary Note 21) In the semiconductor memory device according to Supplementary Note 6, if a request for a refresh operation is issued during the burst operation, the semiconductor storage device waits for a column signal to be output and waits for a column signal to be output. A semiconductor memory device in which a refresh operation is performed by resetting a word line after securing a restore time.
[0092]
(Supplementary Note 22) In the semiconductor memory device according to Supplementary Note 21, the refresh operation performed in response to a refresh operation request during the burst operation is performed within a predetermined number of times of the external clock for reading data corresponding to the word line. A semiconductor memory device characterized by the above-mentioned.
[0093]
(Supplementary Note 23) The semiconductor memory device according to supplementary note 21, wherein the data input / output with the outside is performed in synchronization with a continuous external clock.
[0094]
(Supplementary note 24) The semiconductor memory device according to supplementary note 21, wherein when the refresh operation is completed, the word line that has been activated before the refresh operation is activated again after a preset time interval. Semiconductor storage device.
[0095]
(Supplementary Note 25) In the semiconductor memory device according to Supplementary Note 6, when both the refresh operation and the word line switching operation are requested during the burst operation, the semiconductor memory device gives priority to the word line switching operation. A semiconductor memory device characterized by the above-mentioned.
[0096]
(Supplementary Note 26) The semiconductor memory device according to supplementary note 13, further comprising:
A semiconductor memory device comprising a second column signal counter for counting the second column signal.
[0097]
(Supplementary note 27) In the semiconductor memory device according to supplementary note 26,
If there is a refresh request during the burst operation, the refresh request is held, and the refresh operation is performed when the second column signal counter counts the second column signal twice.
[0098]
(Supplementary Note 28) In the semiconductor memory device according to supplementary note 26,
2. The semiconductor memory device according to claim 1, wherein said second column signal counter is reset when a word line switching request is issued.
[0099]
(Supplementary Note 29) In the semiconductor memory device according to supplementary note 26,
2. The semiconductor memory device according to claim 1, wherein said second column signal counter is reset immediately after a burst operation starts.
[0100]
(Supplementary Note 30) In the semiconductor memory device according to Supplementary Note 1, the semiconductor storage device may include:
A semiconductor memory device wherein, if an operation end signal is present during the burst operation, a word line reset signal is internally generated to reset the word line and end the operation.
[0101]
(Supplementary Note 31) In the semiconductor memory device according to Supplementary Note 30, if there is remaining data that has not been written to the memory core when the operation end signal is generated at the time of the write operation, the operation end signal is used instead of the external clock. A semiconductor memory device for generating a column signal and writing the remaining data.
[0102]
(Supplementary Note 32) The semiconductor memory device according to supplementary note 30, wherein the operation end signal is a signal generated internally or externally applied.
[0103]
(Supplementary Note 33) In the semiconductor memory device according to Supplementary Note 1, even when a plurality of column signals are output by one write operation, unnecessary column signals are not output at the time of unwritten writing.
[0104]
(Supplementary Note 34) In the semiconductor memory device according to Supplementary Note 1, even if a word line switching request is generated from a column signal at the time of the unwritten write, the unwritten write is performed without performing the word line switching operation after the unwritten write. A semiconductor memory device resetting the word line upon completion of the operation and ending the burst operation.
[0105]
(Supplementary Note 35) In the semiconductor memory device according to Supplementary Note 1, when a column signal is generated from the final external clock at the end of the burst write operation, the word line is reset without generating a column signal from the operation end signal. A semiconductor memory device, the operation of which ends.
[0106]
(Supplementary note 36) The semiconductor memory device according to supplementary note 35, wherein even if a word line switching request is generated by a column signal from the last external clock, the word line does not start up. Storage device.
[0107]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide a semiconductor memory device capable of performing a burst operation with virtually no restriction on the burst length and minimizing the recovery time.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing an overall configuration of an embodiment of a semiconductor memory device according to the present invention.
FIG. 2 is a block circuit diagram showing one example of a burst-related column signal generation circuit and a column signal output circuit in the semiconductor memory device of FIG. 1;
FIG. 3 is a waveform chart for explaining a basic read operation in the circuit of FIG. 2;
FIG. 4 is a block circuit diagram showing an example of a word line switching request signal generation circuit, a word line restart signal generation circuit, and a refresh control circuit in the semiconductor memory device of FIG. 1;
FIG. 5 is a waveform diagram (after CL2) for explaining a word line switching operation in the circuit of FIG. 4;
FIG. 6 is a waveform chart (after CL1) for explaining a word line switching operation in the circuit of FIG. 4;
FIG. 7 is a waveform chart for explaining a refresh operation in the circuit of FIG. 4;
8 is a block circuit diagram showing an example of a second column signal counter in the semiconductor memory device of FIG. 1;
FIG. 9 is a waveform diagram for explaining a second column signal counting operation in the circuit of FIG. 8;
10 is a block circuit diagram showing an example of an unwritten write request signal generation circuit, an unwritten write control circuit, and a precharge control circuit in the semiconductor memory device of FIG. 1;
11 is a waveform chart (part 1) for explaining an unwritten write operation in the circuit of FIG. 10;
FIG. 12 is a circuit diagram illustrating an example of a final write control circuit in the semiconductor memory device of FIG. 1;
FIG. 13 is a waveform diagram (part 2) for explaining an unwritten write operation in the circuits of FIGS. 10 and 12;
FIG. 14 is a waveform diagram (part 3) for explaining an unwritten write operation in the circuits of FIGS. 10 and 12;
[Explanation of symbols]
1: Burst column signal generation circuit
2: Column signal output circuit
3: Word line switching request signal generation circuit
4: Word line restart signal generation circuit
5. Refresh control circuit
6: Second column signal counter
7. Unwritten write request signal generation circuit
8. Unwritten write control circuit
9 ... Precharge control circuit
10. Final write control circuit
11 Command generation circuit
12. Clock logic circuit
13: Burst length counter
14: Normal column signal generator
15 Core control circuit
16: I / O address counter
17 ... Burst column timing signal generation circuit
18. Input / output data control circuit
19: Data latch
20 ... Address latch
21 ... Column address counter
22 ... Oscillator
23 ... Address decoder
24 ... Memory core

Claims (10)

A semiconductor memory device for internally generating a refresh operation request signal and performing a burst operation, wherein a column address and a row address for accessing a memory core are changed during the burst operation. . 2. The semiconductor memory device according to claim 1, wherein if a refresh operation is requested during the burst operation, the semiconductor memory device waits for a column signal to be output and sets a cell restore time in the memory core. A semiconductor memory device, in which a refresh operation is performed by resetting a word line after securing. 2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device gives priority to a word line switching operation when both a refresh operation and a word line switching operation are requested during said burst operation. Semiconductor storage device. 2. The semiconductor memory device according to claim 1, further comprising:
A semiconductor memory device comprising a second column signal counter for counting a second column signal. The semiconductor memory device according to claim 4,
2. The semiconductor memory device according to claim 1, wherein said second column signal counter is reset when a word line switching request is issued. 2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device comprises:
A semiconductor memory device wherein, if an operation end signal is present during the burst operation, a word line reset signal is internally generated to reset the word line and end the operation. 7. The semiconductor memory device according to claim 6, wherein at the time of a write operation, when there is remaining data not yet written to said memory core when said operation end signal is generated, a column signal is output from said operation end signal instead of an external clock. A semiconductor memory device for generating and writing the remaining data. 2. The semiconductor memory device according to claim 1, wherein even when a plurality of column signals are output in one write operation, unnecessary column signals are not output at the time of unwritten write. 2. The semiconductor memory device according to claim 1, wherein even if a word line switching request is generated from a column signal at the time of the unwritten write, if the unwritten write is completed without performing the word line switching operation after the unwritten write, A semiconductor memory device wherein the word line is reset to end the burst operation. 2. In the semiconductor memory device according to claim 1, when a column signal is generated from the final external clock at the end of the burst write operation, the word line is reset without generating a column signal from the operation end signal to end the operation. A semiconductor memory device.

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