JP2011159341A - Memory control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently refresh an SDRAM. <P>SOLUTION: In a refresh control circuit 105, an activate command and precharge command are issued to each bank when a specific bank of the SDRAM 107 becomes idle during write or read operation of the SDRAM 107, for refresh. The time during which the SDRAM 107 cannot be accessed by refresh operation is reduced by resuming write or read operation of the SDRAM 107 when the specific bank being refreshed becomes idle. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for efficiently writing and reading image data and the like to and from an SDRAM.

  In recent years, the use of SDRAM as a memory used for image processing has rapidly increased. A feature of the SDRAM is that it has a high-speed input / output interface and a large-capacity memory can be obtained relatively inexpensively. In addition to the conventional SDR (single data rate), SDRAMs that support DDR (double data rate) have recently been used more and more, and the speed of the input / output interface has increased. Progressing.

  On the other hand, the memory cells constituting the SDRAM can hold data only for a certain period of time, and if the writing or reading is not performed for a certain period or more, the data in the memory cells may be corrupted. In order to prevent data corruption, the SDRAM needs to be refreshed at regular time intervals.

  The refresh for SDRAM is roughly divided into auto refresh and self refresh. The self-refresh is a refresh performed to hold data in a memory cell of the SDRAM without performing write and read operations on the SDRAM. On the other hand, auto-refresh is a refresh performed to hold data in SDRAM memory cells while performing write and read operations on the SDRAM. To perform refresh, it is necessary to temporarily stop the write or read operation on the SDRAM. Yes (hereinafter, refresh means auto-refresh).

  During the auto-refresh period, writing to or reading from the SDRAM cannot be performed, which causes the efficiency of access to the SDRAM to deteriorate. Also, as the memory capacity of the SDRAM increases, the time required for one refresh increases. Further, when operating in a high temperature environment, the required average refresh time interval (tREFI) is shortened, and the access efficiency to the SDRAM is further deteriorated.

  In the first method of the prior art disclosed in Patent Document 1, a bank is configured by using a plurality of DRAMs, a refresh operation is performed following write or read access to each bank, and the refresh operation is concealed by performing bank interleaving. The refresh operation is performed without lowering the access efficiency to the DRAM.

  In the second method of the prior art disclosed in Patent Document 2, a plurality of dual port DRAMs are used to form a bank, a refresh operation is performed following a write or read access to each bank, and a bank interleave is performed to perform a refresh operation. And the refresh operation is performed without reducing the access efficiency to the DRAM.

Japanese Patent Laid-Open No. 4-149892 JP-A-8-115594

  However, in the SDRAM, the refresh command cannot be issued until all the banks are in the idle state. Therefore, the write command or the read operation is performed for each bank according to the first method of the conventional technique and the second method of the conventional technique. A subsequent refresh cannot be performed.

  In SDRAM, since it is not possible to perform refresh by designating a bank, refresh cannot be performed until all banks are in an idle state. FIG. 2 shows a timing chart when refresh is performed during a read operation on an FCRAM (Fast Cycle RAM) which is attracting attention as a memory that achieves both low power consumption and high performance as an example of SDRAM access. FCRAM is a double data rate SDRAM with a data bus width of 64 bits. The timing chart shown in FIG. 2 shows that 256 bytes of data can be obtained by accessing all four banks by bank interleaving using a burst length of 8 and all 4 banks. Is a timing chart at the time of reading from the FCRAM.

  The operation parameter of FCRAM is shown.

tCK: Clock cycle 5ns
tRC: Minimum time from activation to next activation issuance for the same bank 59.2ns (12tCK)
CL: Time until data is output from FCRAM in response to a read command 4 tCK
tRP: Time from precharge command to completion of precharge 18ns (4tCK)
tRRD: Minimum time from activation to activation command of another bank 9.2ns (2tCK)
tRCD: Minimum time from activation to issue of write or read command 20ns (4tCK)
tRAS: Minimum time from activation to issuing a precharge command 37ns (8tCK)
tRFC: Minimum time from auto refresh to activation issuance 100ns (20tCK)
The timing chart shown in FIG. 2 will be described below. 256 bytes of data are read from the FCRAM by issuing one read command with auto-precharge to each bank with a burst length of 8 and making a round of 4 banks. The command to the FCRAM for performing four-bank access is composed of an activation command from t0 to a read command with auto precharge from t4, and 256 bytes of data are read from the FCRAM during a period from t2 to t5.
Reading from the FCRAM with a burst length of 8 is performed for each bank using two commands, an activate command and a read command with auto-precharge. Compared with the low cycle time tRC (12tCK), it takes 16 cycles to make a round of 4 banks, and tRC is concealed by making a round of 4 banks, and as a result, random to the FCRAM in units of 256 bytes. Access is possible. When refreshing, the bank 3 becomes idle at t5 eight cycles after the read command with auto precharge of the bank 3 at t4, and the auto-refresh command can be issued at the timing of t5.
At t6 after tRFC (20 tCK) from the refresh command issued at t5, the read operation is resumed by the activate command for bank 0 again, and read data is output from the FCRAM at timing t7. From the above operation, if auto refresh is performed during a read operation that makes a round of 4 banks, the FCRAM cannot be accessed for a period of 27 cycles.

  In the FCRAM, when the junction temperature of the memory chip in the FCRAM is 90 degrees or less, refresh may be issued at an average period of 7.8 μs. However, when the junction temperature of the memory chip in the FCRAM exceeds 90 degrees, refresh is performed. It is necessary to carry out with an average period of 1 μs (200 cycles). Further, the FCRAM cannot be accessed for a period of 27 cycles in one refresh operation. In other words, the data transfer bandwidth of 13.5% is used for the refresh operation, the access efficiency to the FCRAM is reduced to 86.5%, the data transfer bandwidth usable by the master is reduced, and the efficient use of the FCRAM is improved. become unable.

  In view of the above, the present invention provides a control circuit for a synchronous DRAM (hereinafter referred to as SDRAM) that has a plurality of banks and performs data writing or reading a plurality of times by a single writing or reading command. Writing to the SDRAM while shifting the timing of accessing each bank for all banks or some banks constituting the SDRAM in accordance with the access request and the SDRAM access stop signal for stopping access to the SDRAM during the refresh operation of the SDRAM Alternatively, an SDRAM access control circuit that performs a read request, a data control circuit that performs data control between the master and the SDRAM by the SDRAM access control circuit, and a refresh that controls the refresh operation timing for the SDRAM at a constant cycle. The SDRAM refresh control and SDRAM access stop signal are output from the SDRAM schedule signal indicating that the SDRAM output from the SDRAM access control circuit has changed to the idle state and the refresh request signal output from the refresh schedule circuit. A refresh control circuit, and an SDRAM command generation circuit for generating a command to the SDRAM by receiving an SDRAM access control signal output from the SDRAM access control circuit and a refresh control signal output from the refresh control circuit. The memory control circuit is characterized in that the refresh to the SDRAM is performed by activation and precharging based on the generation of the command.

  In order to solve the above problems, the present invention employs the following configuration. That is, according to a first aspect of the present invention, there is provided a control circuit for a synchronous DRAM (hereinafter referred to as SDRAM) having a plurality of banks and performing a plurality of times of data writing or reading with a single writing or reading command. The access to the SDRAM is shifted while shifting the timing of accessing each bank with respect to all banks or a plurality of banks constituting the SDRAM according to the SDRAM access operation and the SDRAM access stop signal for stopping the access to the SDRAM during the refresh operation of the SDRAM. An SDRAM access control circuit for making a write or read request, a data control circuit for controlling data between the master and the SDRAM by the SDRAM access control circuit, and a control for controlling the refresh operation timing with respect to the SDRAM at a constant cycle. The SDRAM refresh control and the SDRAM access stop signal are output from the SDRAM status signal indicating that the SDRAM output from the refresh schedule circuit and the SDRAM access control circuit has changed to the idle state and the refresh request signal output from the refresh schedule circuit. A refresh control circuit, and an SDRAM command generation circuit for generating a command to the SDRAM by receiving an SDRAM access control signal output from the SDRAM access control circuit and a refresh control signal output from the refresh control circuit. The memory control circuit is characterized in that the refresh to the SDRAM is performed by activation and precharging based on the generation of the command.

  In addition to the first aspect of the present invention, the second aspect of the present invention is such that the SDRAM access control circuit continuously performs write or read control across SDRAM banks, and is required for writing or reading of all banks to be accessed. This time is greater than the tRC of the SDRAM and less than twice the tRC.

  In addition to the first aspect of the invention, the third invention performs the refresh operation only after read access to the SDRAM.

  According to a fourth aspect of the present invention, in addition to the first aspect of the present invention, the SDRAM state signal is changed to an idle state of a specific bank of the SDRAM to be accessed.

  According to a fifth aspect of the present invention, the SDRAM status signal indicates that the bank of the SDRAM accessed first in accordance with an access request from the master has changed to the idle state.

  As described above, in the memory control circuit of the present invention, the refresh operation is performed by using the activate command and the precharge command for each bank instead of the auto refresh command, as compared with the case where the auto refresh command is used. The time during which the SDRAM cannot be accessed can be shortened, and the utilization efficiency of the SDRAM can be improved. Moreover, it can be realized by a combination of commands that can be controlled originally with respect to a normal SDRAM, and the utilization efficiency of the SDRAM can be improved without increasing the cost.

The figure which shows the memory control circuit in this Embodiment SDRAM access timing chart in the prior art Timing chart at the time of continuous reading of SDRAM in the present embodiment Timing chart of operation of SDRAM access control circuit 103 in the present embodiment Timing chart of operation of refresh control circuit 105 in this embodiment (1) Timing chart of operation of refresh control circuit 105 in this embodiment (2) Timing chart of read control and refresh control in this embodiment

(Embodiment 1)
Hereinafter, an embodiment of a memory control circuit according to the present invention will be described. FIG. 1 is a block diagram showing a memory control circuit in the present embodiment. The memory control circuit includes a master 101, a data control circuit 102, an SDRAM access control circuit 103, a refresh schedule circuit 104, a refresh control circuit 105, an SDRAM command generation circuit 106, and an SDRAM 107.

The master 101 issues an access request rq to the SDRAM access control circuit 103 in order to write to or read from the SDRAM. The SDRAM access control circuit 103 generates an SDRAM access control signal which is an SDRAM command sequence for writing or reading data to or from the SDRAM 107 in accordance with the access request rq from the master 101 and the SDRAM access stop signal from the refresh control circuit 105.
Further, the SDRAM access control circuit 103 outputs, as an SDRAM state signal, a timing at which the SDRAM changes to an idle state after accessing the SDRAM according to the SDRAM access control signal. The data control circuit 102 inputs data output from the master 101 to the SDRAM 107 and writes data to the SDRAM 107 when writing to the SDRAM 107 in accordance with the control of the SDRAM access control circuit 103. Data read from the SDRAM 107 is input to the master 101. The refresh schedule circuit 104 generates a refresh request signal at an average refresh time interval (tREFI) required for the SDRAM 107.
The refresh control circuit 105 receives the SDRAM state signal and the refresh request signal as input, and generates a refresh control signal for refreshing the SDRAM 107 at a timing when the SDRAM 107 becomes idle at a time interval of tREFI. Furthermore, the refresh control circuit 105 outputs an SDRAM access stop signal to the SDRAM access control circuit 103 during the refresh control of the SDRAM 107, and stops generating a command string for accessing the SDRAM 107 from the SDRAM access control circuit 103 during the refresh operation. Let The SDRAM access control circuit 103 accesses the SDRAM while shifting the timing of accessing each bank when outputting an SRAM access control signal that is a command sequence for writing to or reading from the SDRAM in response to an access request rq from the master 101. To do.

FIG. 3 shows an example of a timing chart of bank interleaving that is performed while shifting the timing of accessing each bank of the FCRAM. An example of operation when the bart length is 8 is shown. A read operation with a burst length of 8 is realized by issuing an activate command and a read command with auto precharge to each bank of the FCRAM. An activate command is issued to bank 0 at t0, and a read command with auto precharge is issued to bank 0 at t1. For bank 1, an activate command and a read command with auto-precharge are issued from the timing of t2, which is four cycles behind bank 0, as in the case of bank 0. By issuing commands in the same manner for the bank 2 and bank 3, data can be read continuously from the FCRAM. The FCRAM address for accessing each bank accesses the same row address Ar and the same column address Ac for all four banks accessed from t0 to t4. In the access that starts with activation of bank 0 starting from t8, the access is to the same column address Bc as the row address Br different from the FCRAM address so far.
As a result, in an access that makes a round of 4 banks, an access with a burst length of 8 requires 16 cycles. In this embodiment, a read command with auto precharge is issued to each bank after three cycles after the activate command. However, a read command with auto precharge for the bank to be continuously accessed is four cycles. If it can be issued at an interval, the interval between the activate command and the read command with auto precharge may be 3 cycles or more.

  As described above, the command sequence is generated so that the time required for writing or reading to the bank to be accessed is longer than the SDRAM low cycle time (tRC = 12 tCK in the case of RCRAM), thereby enabling continuous reading from the SDRAM. It can be carried out. That is, random access can be continuously performed with access of four banks to be accessed as one unit.

Further, the unit of random access can be minimized by making the time required for writing or reading the bank to be accessed smaller than twice the row cycle time (tRC) of the SDRAM. As an example, in a 64-bit data bus FCRAM, if one burst is accessed with a burst length of 8 for each bank, 256 bytes of data can be accessed from the FCRAM in 4 banks, and a small transfer unit suitable for video processing. Can randomly access the FCRAM.
As an example of the present embodiment, the name that has been described for the operation with a burst length of 8 is one activation, one read command, and one operation for each bank even if the burst length is 4. By issuing a read command with auto precharge, the same access to the SDRAM can be realized.
Further, the FCRAM write operation can be accessed in the same manner as the read operation by using the write command with auto precharge instead of the read command with auto precharge. In the present embodiment, an example of an operation in which the address of the FCRAM to be accessed is common in each bank has been described in the access that makes a round of four banks. It is possible to perform random access to the FCRAM in a unit that makes a round of four banks.

  Next, the operation of the SDRAM access control circuit 103 will be described in detail with reference to FIG. The timing chart shown in FIG. 4 shows a timing chart of the operation of the SDRAM access control circuit 103 when a read request is issued from the master 101 to the FCRAM. The SDRAM access control circuit 103 needs to stop access to the SDRAM 107 by an SDRAM access stop signal input from the refresh control circuit 105. This operation will be described later.

  The access request signal rq issued from the master 101 is divided into a read request signal rreq and an address rad. The rreq is input to the SDRAM access control circuit 103 together with the read address rad set simultaneously. In the present embodiment, the row address and the column address are directly specified as the read address, but a logical address created from the row address and the column address may be used, but from a combination of the row address and the column address. The logical address must be uniquely determined.

  The SDRAM access control circuit 103 outputs a response signal ack to the master 101 at a timing t0 when it can respond to an access request rq for reading data from the FCARM output by the master 101. When the master 101 receives the response signal ack, the master 101 outputs an access request read request rq for reading the FCRAM at a timing t2 at which it can be output when there is a next read request.

  The SDRAM access control circuit 103 outputs a response signal ack to the master 101 at the timing t0, and simultaneously fetches the row address Ar and the column address Ac, which are the read addresses of the FCRAM, and starts four cycles for the FCRAM from the next cycle t1. An SDRAM access signal is output as a command string for reading the row address Ar and the column address Ac from the bank. An activate command for bank 0 is generated at timing t1, and a read command with auto precharge for bank 0 is generated at timing t3. The same operation is repeated for bank 1, bank 2, and bank 3 to generate a command for one cycle of four banks.

  The SDRAM access control circuit 103 completes the generation of the read command that makes a round of four banks at the timing t4 when the read command with auto precharge for the bank 3 is generated. The master 101 has already output the second access request rq for reading the FCRAM at the timing t2, and the SDRAM access control circuit 103 again masters the response signal ack at the timing t4 with respect to the access request rq. 101. By repeating this operation, a command sequence for continuous reading of the FCRAM is generated.

  The SDRAM access control circuit 103 outputs an SDRAM access control signal, which is a command sequence to the FCRAM, and at the same time outputs an SDRAM status signal indicating the timing at which the SDRAM changes to the idle state. FIG. 4 shows a timing chart of the SDRAM state signal. The command sequence to the FCRAM that goes around the four banks is the same as that shown in FIG. The SDRAM status signal is 0 to indicate that the SDRAM is busy, and 1 to indicate the idle status.

The SDRAM access control circuit 103 sets the SDRAM state signal to 0 at the timing t1 when the activate command for the bank 0 is generated according to the SDRAM access control signal, indicating that the bank 0 has changed to the busy state. Subsequently, the SDRAM state signal is set to 1 at the timing t7 eight cycles after the timing t3 of the read command generation with auto precharge in the bank 0, indicating that the bank 0 has changed to the idle state. It is a restriction of the FCRAM that the bank becomes idle after eight cycles from the read command with auto precharge, and is a restriction depending on the SDRAM to be used.
In accordance with the access request from the master 101, the SDRAM access control circuit 103 generates an activate command for the bank 0 again at the timing t8, and at the same time, sets the SDRAM state signal to 0 to indicate that the bank 0 has changed to the busy state. Subsequently, the SDRAM state signal is set to 1 at the timing of t10 after 8 cycles from the generation timing t9 of the read command with auto precharge of the bank 0, indicating that the bank 0 has changed to the idle state.

  In this embodiment, since the SDRAM access control circuit 103 performs an access that makes a round of four banks of the FCRAM in accordance with an access request from the master 101, the timing at which the FCRAM becomes idle after the round of access of the four banks. Is the timing after 8 cycles from the read command with auto-precharge of the bank 3, which is the bank to be accessed at the end of the four banks. However, since the SDRAM status signal is used for controlling the timing of starting the refresh operation of the SDRAM, the timing at which the first bank becomes in an idle state is required in an access that makes a round of four banks of the FCRAM. Therefore, bank 0 is a specific bank, and the state of bank 0 is the FCRAM state. The refresh method will be described in detail later.

  In the example of this embodiment, the SDRAM access control circuit 103 accesses four banks from bank 0 to bank 1, bank 2, and bank 3 in accordance with an access request from the master 101. If it is possible to make a round of banks, it is not necessary to access from bank 0. As an example, in the case of realizing access of four banks through the access of bank 1, bank 2, bank 3, and bank 0, the state of bank 1 may be reflected in the SDRAM state signal as the state of FCRAM.

Next, the operation of the refresh control circuit 105 will be described. The refresh schedule circuit 104 outputs a refresh request signal to the refresh control circuit 105 so as to perform refresh at an average refresh time interval (tREFI) required for the SDRAM to be used. As an example, when tREFI is 1 μs and the operation clock of the SDRAM is 200 MHz, a refresh request is output from the refresh schedule circuit 104 in units of 200 cycles.
The refresh control circuit 105 outputs a refresh control signal which is a command sequence for a refresh operation to the SDRAM according to the SDRAM status signal and the refresh request signal. The refresh control signal will be described later in detail. The refresh control circuit 105 outputs a refresh control signal and simultaneously outputs an SDRAM access stop signal so as to stop outputting the SDRAM access control signal to the SDRAM access control circuit 103 during a refresh operation to the SDRAM 107.

FIG. 5 shows a timing chart for explaining the operation of the refresh control circuit 105. In FIG. 5, a refresh request is generated from the refresh schedule circuit 104 with the refresh request signal set to 1. At the timing t0, the refresh request signal becomes 1, and a refresh request for the SDRAM 107 is generated. At the timing t0, the SDRAM status signal is 0 (indicating that the SDRAM is busy), so the SDRAM status signal changes to 1 (indicating that the SDRAM is busy) at the timing t1. The command sequence for the refresh operation of the SDRAM 107 is output to The SDRAM access stop signal is set to 1 at timing t1 at which the SDRAM refresh command sequence is output as the refresh control signal, and the SDRAM access control circuit 103 is stopped from accessing the SDRAM 107.
At the timing t2, the SDRAM state signal is 1 at the timing when the refresh request is generated from the refresh schedule circuit 104. Therefore, the command sequence for the refresh operation of the SDRAM 107 is output to the refresh control signal at the timing t2. Set SDRAM access stop signal to 1. The refresh control signal becomes NOP (no command) after outputting a command sequence for a predetermined refresh operation. The SDRAM access stop signal becomes 1 at the timing when the refresh command sequence is output to the refresh control signal, but becomes 0 until the output of the predetermined refresh command sequence is completed, and the SDRAM 107 of the SDRAM access control circuit 103 becomes. Resume access to.

The operation of the refresh control circuit 105 will be described in detail with reference to the timing chart of FIG. FIG. 6 shows a timing chart when the refresh control circuit 105 generates a command sequence for refresh operation for the FCRAM. The refresh request signal output from the refresh schedule circuit 104 becomes 1 at the timing t0, and a refresh request is generated from the refresh schedule circuit 104. Since the bank 0 of the FCRAM enters an idle state at the timing when the SDRAM status signal output from the SDRAM access control circuit 103 changes to 1, the refresh control circuit 105 starts generating a command string for refreshing the FCRAM. Then, the SDRAM access stop signal is set to 1 to stop the SDRAM access control circuit 103 from accessing the FCRAM.
At the timing of t2, since the bank of the FCRAM is not in an idle state except for the bank 0, the auto refresh command cannot be issued to the FCRAM. Therefore, refresh is performed by specifying a bank and using an activate command and a precharge command. That is, an activate command is generated for the row address Br of the bank 0 at the timing t2, and a precharge command for the bank 0 is generated after tRAS (8 cycles), thereby refreshing the row address Br of the bank 0.
With respect to bank 1, as shown in FIG. 4, when a continuous read operation is performed with a burst length of 8, bank 1, bank 2, and bank 3 are in an idle state every four cycles from the timing when bank 0 becomes idle. To change. Therefore, every four cycles after activation and command generation at the timing t2 for the bank 0, at the timing t3 for the bank 1, at the timing t4 for the bank 2, and at the timing t5 for the bank 3. You can generate an activation command at the timing.
As in the case of bank 0, also in other banks, a precharge command can be generated at tRAS (after 8 cycles) from the activate command, and each bank can be closed to an idle state. The refresh operation of the four banks of the FCRAM is performed by the precharge command of the bank 3 at the timing t7 from the activation command of the bank 0 at the timing t2.
As described above, the refresh operation is realized by refreshing the SDRAM by designating the bank and generating the activate command and the precharge command instead of the normal auto refresh command. At t5, a precharge command for bank 0 is generated, and bank 0 becomes idle at t8 after tRP (4 cycles). Therefore, the refresh control circuit 105 changes the SDRAM access stop signal to 0, and the SDRAM access control circuit 103 makes the SDRAM accessible again.

  As described above, since the refresh operation is performed by designating the bank by the activate command and the precharge command, the refresh control circuit 105 needs to manage the row address for performing the refresh which is not required by the auto refresh command. It is necessary to refresh all the rows in the bank within the SDRAM refresh period.

The SDRAM command generation circuit 106 outputs a control command cm to the SDRAM 107 by mixing and outputting the SDRAM access control signal output from the SDRAM access signal 103 and the refresh control signal output from the refresh control circuit 105.
FIG. 7 shows a timing chart when the FCRAM shifts from the read operation to the refresh operation and shifts to the read operation again. The generation of the FCRAM read command before the refresh operation is in a period from t0 to t2, but the bank 0 is in an idle state at a timing before the timing of t2, and a refresh command can be issued from the timing of t1. Become.
The command for refresh operation is issued during the period from t1 to t4. Like the read operation, the bank 0 is in an idle state before the timing of t4. Therefore, the read operation is performed at the timing of t3 following the refresh operation. You can resume. That is, by overlapping a part of the command issuing period for the read operation and the command issuing period for the refresh operation with respect to the SDRAM, the time required for issuing the command can be shortened. As a result, the time during which the SDRAM cannot be accessed due to the refresh operation can be shortened to 13 cycles.
Note that although the case where the refresh operation is performed during the read operation to the SDRAM has been described in this embodiment mode, the refresh operation to the SDRAM can be performed during the write operation by a similar control method. Even when refreshing is performed between writing operations, it is possible to shorten the time during which the SDRAM cannot be accessed by the refreshing operation, compared to the case where the art refresh command is used.

  In general, SDRAM has a write recovery time, so that the time required for a bank to become idle after a write operation to the bank is longer than the time required for the bank to become idle after a read operation with the same amount of data. Therefore, even when there is a refresh request from the refresh schedule circuit 104, the refresh control circuit 105 performs the refresh only after the read operation to the SDRAM 107, thereby minimizing the time during which the SDRAM cannot be accessed by the refresh operation. Can do.

  In this embodiment, the FCRAM is used as an example of the SDRAM. However, the present invention can also be realized by using a normal SDRAM standardized by JEDEC. In addition, although the unit of writing or reading with respect to the SDRAM is 256 bytes, a unit other than 256 bytes may be used.

  The present invention is useful as a memory control circuit that efficiently performs memory control in a memory control circuit that performs writing and reading of image data and the like to and from a memory having a plurality of banks.

DESCRIPTION OF SYMBOLS 101 Master 102 Data control circuit 103 SDRAM access control circuit 104 Refresh schedule circuit 105 Refresh control circuit 106 SDRAM command generation circuit 107 SDRAM

Claims (5)

In a control circuit for a synchronous DRAM (hereinafter referred to as SDRAM) having a plurality of banks and writing or reading data a plurality of times with a single write or read command,
SDRAM while shifting the timing of accessing each bank with respect to all banks or a plurality of banks constituting the SDRAM according to an access request from the master and an SDRAM access stop signal for stopping access to the SDRAM during the refresh operation of the SDRAM An SDRAM access control circuit for making a write or read request to
A data control circuit for controlling data between the master and the SDRAM by the SDRAM access control circuit;
A refresh schedule circuit for controlling the operation timing of the refresh at a constant cycle with respect to the SDRAM;
A refresh control of the SDRAM and a refresh control of outputting the SDRAM access stop signal from an SDRAM status signal indicating that the SDRAM output from the SDRAM access control circuit has changed to an idle state and a refresh request signal output from the refresh schedule circuit. Circuit,
An SDRAM command generation circuit for generating a command to the SDRAM by inputting an SDRAM access control signal output from the SDRAM access control circuit and a refresh control signal output from the refresh control circuit, and a command from the SDRAM command generation circuit A memory control circuit, wherein refresh to SDRAM is performed by activation and precharge based on occurrence.   The memory control circuit continuously performs write or read control across SDRAM banks in the SDRAM access control circuit, and the time required for writing or reading all banks to be accessed is the SDRAM low cycle time (hereinafter referred to as tRC). 2. The memory control circuit according to claim 1, wherein the memory control circuit is larger than and smaller than twice tRC.   The memory control circuit according to claim 1, wherein the memory control circuit performs a refresh operation only after read access to the SDRAM.   2. The memory control circuit according to claim 1, wherein the memory control circuit indicates that the SDRAM status signal has changed to an idle state of a specific bank of an SDRAM to be accessed.   2. The memory control circuit according to claim 1, wherein the SDRAM status signal indicates that the bank of the SDRAM accessed first in accordance with an access request from the master has changed to an idle state.

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