JP2005332538A - Semiconductor memory and memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable the speed-up of the access operation of a pseudo SRAM. <P>SOLUTION: A refresh request signal requesting refresh operation for a memory cell array 7 is outputted to the outside and operation to be executed on the basis of the decoding result of information on an external access request including the refresh execution request of a response to the refresh request signal is instructed. By executing operation for the memory cell array on the basis of the instruction, operation for the memory cell array including the refresh operation is requested only by external access and the need for providing a refresh entry period is eliminated and a time required for the access operation can be shortened. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device and a memory system, and is particularly suitable for use in a pseudo SRAM (Static Random Access Memory).

  A pseudo SRAM, which is one of semiconductor memory devices, is a memory in which memory cells for storing data are composed of cells similar to DRAM (Dynamic Random Access Memory), and an external interface is compatible with the SRAM. The pseudo SRAM has the features of a DRAM that has a larger capacity and lower bit cost than the SRAM, and has the same ease of use as the SRAM, and realizes a larger capacity and easier system design. For example, a low power (low power consumption) pseudo SRAM is used as a memory (RAM) of a mobile phone.

  FIG. 17 is a block diagram showing a configuration of a conventional pseudo SRAM 101. As shown in FIG. The pseudo SRAM 101 includes a memory cell array 102, an array control circuit 103, a refresh control circuit 104, a chip control circuit 105, an address decoder 106, a data signal control circuit 107, and an interface circuit 108.

  The memory cell array 102 includes a plurality of memory cells arranged in an array with respect to the row direction and the column direction. As described above, each memory cell is a 1T-1C type (one transistor and one capacitor type) memory cell similar to a DRAM. The array control circuit 103 performs a data read (read) operation, a data write (write) operation, and a refresh operation on the memory cells in the memory cell array 102.

  The refresh control circuit 104 outputs a request for a refresh operation necessary for holding the data stored in the memory cell according to a timer value provided therein.

The chip control circuit 105 decodes an external command signal (external command) CMD supplied via the interface circuit 108, and sends a control signal based on the decoding result and a refresh request from the refresh control circuit 104 to the array control circuit 103. Output to. The command signal CMD is composed of a chip enable signal / CE, an address valid (valid) signal / ADV, an output enable signal / OE, and a write enable signal / WE as will be described later (“/” added to the sign of each signal). Indicates that the signal is negative logic).
Further, the chip control circuit 105 performs arbitration between the access request (data read / write) and the refresh request based on the command signal CMD. In this arbitration, a request that has occurred first is processed with priority.

The address decoder 106 decodes an external address signal ADD supplied via the interface circuit 108 and outputs the decoding result to the array control circuit 103.
The data signal control circuit 107 controls exchange of data signals between the inside and outside of the memory in the read operation and the write operation performed according to the external command.

  Note that a clock signal CLK that synchronizes the input / output timings of the command signal CMD and the data signal DQ is input to the interface circuit 108 from the outside, and is supplied to each functional unit in the pseudo SRAM 101.

  FIG. 18 is a timing chart for explaining the operation (data read operation) in the conventional pseudo SRAM. In FIG. 18, the core operation is an operation of selecting the memory cell array 102, in other words, an operation executed by the array control circuit 103 for the memory cell array 102. The Peri operation is an operation of peripheral circuits related to the memory cell array 102 (array control circuit 103) such as the chip control circuit 105 and the data signal control circuit 107.

  First, at time T51, the chip enable signal / CE for setting the device (pseudo SRAM) to the operating state, the address valid signal / ADV indicating that the address signal ADD is valid, and the output enable signal / OE are set to “L”. Change. The chip control circuit 105 decodes these command signals CMD and determines that the external access request is the data read operation RD (A). The address decoder 106 takes in the address signal ADD and decodes it.

  However, if a refresh request from the refresh control circuit 104 is generated before time T51 when an external access request is received, the refresh operation REF is executed in the memory cell array 102 (time T52). Then, the data read operation RD (A) is executed in the memory cell array 102 from the time T53 when the refresh operation REF ends, and the memory cell data 1A, 2A, and 3A corresponding to the decoding result in the address decoder 106 are sequentially read out. Output as data signal DQ.

  When the chip enable signal / CE changes to “H” at time T54, the chip control circuit 105 instructs the array control circuit 103 to end the data read operation RD (A). As a result, the data read operation RD (A) being executed in the memory cell array 102 ends (time T55).

  At time T55, when the chip enable signal / CE and the address valid signal / ADV change to “L”, the chip control circuit 105 decodes the command signal CMD at this time, and an external access request is a data read operation. Judged to be RD (B). The address decoder 106 takes in the address signal ADD and decodes it.

  Then, at time T56 when the refresh entry period TREN elapses from time T55, the data read operation RD (B) is executed in the memory cell array 102, and the data 1B, 2B, 3B, 4B, and 5B are output as the data signal DQ. Note that the refresh entry period TREN is always provided between data read / write operations by an external access request so that the refresh operation can be executed in the memory cell array 102 when a refresh request occurs.

  Thereafter, similarly to the data read operation RD (A), the data read operation RD (B) being executed in the memory cell array 102 is completed by changing the chip enable signal / CE to “H” at time T57. (Time T58).

FIG. 19 is a timing chart for explaining the operation (data write operation) in the conventional pseudo SRAM. In the data write operation shown in FIG. 19, the write enable signal / WE is set to "L" and the output enable signal / OE is maintained at "H", and the data 1A to 3A and 1B to be supplied as the data signal DQ. It is the same as the data read operation shown in FIG. 18 except that 5B is written to the memory cell (time T61 to T68 corresponds to time T51 to T58, respectively), and the description is omitted.
As shown in FIGS. 18 and 19, in the conventional pseudo SRAM, a data read operation and a data write operation are performed.

  In recent years, large-capacity and real-time data communication related to moving image data and the like has been performed, and higher speed operation is also possible for a pseudo SRAM used as a memory of a data communication device including a mobile phone. It is requested.

Japanese Patent Laid-Open No. 11-16346 International Publication No. 98/56004 Pamphlet

  However, in the conventional pseudo SRAM, since the refresh entry period TREN is always provided as shown in FIGS. 18 and 19, the latency is assumed assuming that the worst-case refresh request occurs first. The access time related to the access request from the outside is defined so as to include A series of operations from receiving an external access request (command) to inputting / outputting data starts a series of operations corresponding to the next access request after a series of operations corresponding to a certain access request is completed. In other words, the processing is executed so that only processing related to one access request is always performed.

  As a method of speeding up the operation (access) in the pseudo SRAM, first, a method of shortening the access time from the outside by shortening the latency as shown in FIG. However, if the latency is shortened, the time interval TC between data read / write operations due to an external access request is shortened, and there is a possibility that a period corresponding to the refresh entry period TREN cannot be secured. That is, when the latency is shortened, even if a refresh request occurs, the refresh operation cannot be performed between data read / write operations due to an external access request, and the data stored in the memory cell is lost. There is a risk that.

  Further, as another method for speeding up the operation in the pseudo SRAM, a method of multiplexing access requests from the outside as shown in FIG. However, in the conventional pseudo SRAM, when the data read operation RD (B) is requested when the data read operation RD (A) is executed as shown at time T91 in FIG. At that time, the address signal ADD related to the data read operation RD (B) is captured and decoded. Therefore, the decoding result in the address decoder 106 changes and a different memory cell is selected. Accordingly, when the data read operation RD (B) is requested during the execution of the data read operation RD (A), the access request from the outside cannot be accurately recognized, and correct data is output from that point. That cannot be guaranteed (data 3A in the example shown in FIG. 20B). The same applies to the data write operation.

  The present invention has been made in view of such circumstances, and an object thereof is to increase the speed of access operation of a pseudo SRAM.

  A semiconductor memory device according to the present invention decodes a memory cell array in which a plurality of memory cells are arranged, a refresh request circuit for outputting a refresh request signal for requesting a refresh operation to the outside, and information relating to an external access request for the memory cell array And a processing circuit for instructing an operation to be executed in the memory cell array based on the decoding result, and an array control circuit for executing an operation on the memory cell array based on an instruction from the processing circuit. The external access request includes a refresh execution request in response to the refresh request signal.

According to the above configuration, since the operation on the memory cell array including the refresh operation is required only by an external access request, it is not necessary to provide a refresh entry period, and the time required for the access operation to the memory cell array such as latency and write cycle time is reduced. can do.
In addition, when a register is provided to hold a result of decoding information related to the external access request by the processing circuit, the operation related to the external access request can be executed by a pipeline operation by the processing circuit and the array control circuit. it can.

  According to the present invention, the refresh request signal for requesting the refresh operation is output to the outside, so that the operation on the memory cell array including the refresh operation is controlled only by the external access request. Therefore, the refresh entry period is provided between the operations. This eliminates the need to reduce the time required for the access operation to the memory cell array, increase the number of accessible times per unit time, and realize high-speed access operation of the semiconductor memory device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device 1 according to the first embodiment of the present invention.
The semiconductor memory device 1 is a pseudo SRAM and includes a refresh timer 2, a chip control circuit 3, an address decoder 4, a data signal control circuit 5, an array control circuit 6, a memory cell array 7, and an interface circuit 8.

  The refresh timer 2 measures time using a measuring unit such as a counter and outputs a refresh input request signal REFR to the outside via the interface circuit 8 every time a predetermined period elapses. The refresh timer 2 corresponds to the refresh request circuit in the present invention. The refresh input request signal REFR is a signal for requesting a refresh signal (command) REFE for executing a refresh operation for the memory cell array 7.

The chip control circuit 3 includes a pipeline execution control unit 10 and a command register 12 and comprehensively controls the operation of each circuit in the semiconductor memory device 1.
Specifically, the chip control circuit 3 is supplied with an external command signal (external command) CMD and a refresh signal (command) REFE via the interface circuit 8. The chip control circuit 3 decodes them using a decoder (not shown), and outputs a control signal to the array control circuit 6 based on the decoding result.

The command register 12 is a register that holds a decoding result obtained by decoding in the chip control circuit 3.
The pipeline execution control unit 10 will be described later.

The address decoder 4 decodes an external address signal ADD supplied via the interface circuit 8 and outputs a selection address signal based on the decoding result to the array control circuit 6. The address decoder 4 has an address register 13 that holds a decoding result obtained by decoding the address signal ADD. The decode result held in the address register 13 and the decode result held in the command register 12 relate to the same request, and the decode result held in the command register 12 and the address register 13 is supplied to the trigger signal Trig. Based on the output.
The chip control circuit 3 and the address decoder 4 constitute a processing circuit in the present invention.

The data signal control circuit 5 performs a data signal between the semiconductor memory device 1 and the outside via the interface circuit 8 in a read operation and a write operation with respect to the memory cell array 7 performed according to an external command signal CMD. Controls the exchange of DQ.
Based on the control signal supplied from the chip control circuit 3 and the selection address signal supplied from the address decoder 4, the array control circuit 6 performs a data read (read) operation and data write ( A write operation and a refresh operation are executed.

The memory cell array 7 has a plurality of memory cells arranged in an array in the row (row) direction and the column (column) direction. Specifically, the memory cell array 7 has a plurality of bit lines and a plurality of word lines provided so as to intersect with the bit lines, and memory cells are arranged at intersections between the bit lines and the word lines. . Each memory cell is composed of a 1T-1C type (one-transistor one-capacitor type) memory cell similar to a DRAM, and stores 1-bit data.
The memory cell array 7 has sense amplifiers provided corresponding to the bit lines.

  The interface circuit 8 is for transferring each signal between the inside and outside of the semiconductor memory device 1. The interface circuit 8 receives a command signal CMD, an address signal ADD, and a refresh signal REFE from the outside, and outputs a refresh input request signal REFR to the outside. Further, the data signal DQ is inputted to and outputted from the interface circuit 8. A clock signal CLK for synchronizing input / output timings of the command signal CMD, the data signal DQ, and the like is input from the outside and supplied to each circuit in the semiconductor memory device 1.

  FIG. 2 is a diagram showing a configuration example of a memory system using the semiconductor memory device 1 shown in FIG. In FIG. 2, the semiconductor memory device 1 is illustrated in a simplified manner, and blocks having the same functions as the blocks illustrated in FIG.

  A refresh input request signal REFR output from the refresh timer 2 is input to the memory controller 21. A command signal CMD and a refresh signal REFE output from the memory controller 21 are input to the chip control circuit 3, and an address signal ADD output from the memory controller 21 is input to the address decoder 4. The data signal DQ is input / output between the memory controller 21 and the data signal control circuit 5.

  The memory controller 21 controls the semiconductor memory device 1 based on a request from the processor 22 or the like. For example, when the memory controller 21 receives a refresh request based on the refresh input request signal REFR from the semiconductor memory device 1, the memory controller 21 outputs the refresh signal REFE within a certain period after reception. When the memory controller 21 receives an access request (data read or write) from the processor 22 to the semiconductor memory device 1, the memory controller 21 outputs a command signal CMD and an address signal ADD corresponding to the access request. The memory controller 21 performs an arbitration process between an access request from the processor 22 to the semiconductor memory device 1 and a refresh request by the refresh input request signal REFR, and outputs a command signal CMD or a refresh signal REFE according to the arbitration result.

  As described above, in the memory system using the semiconductor memory device 1, the refresh for causing the semiconductor memory device 1 to perform the refresh operation based on the refresh input request signal REFR output from the refresh timer 2 in the semiconductor memory device 1. The signal REFE is output. Therefore, since the semiconductor memory device 1 itself controls the execution timing of the refresh operation, the controller does not need to have a timer or the like for controlling the execution timing of the refresh operation in the memory controller 21, and the execution timing of the refresh operation. There is no need to consider. Thereby, a memory system as shown in FIG. 2 can be realized by the same conventional system, and can be easily performed even when a new system is constructed.

FIG. 3 is a circuit diagram showing a configuration of the pipeline execution control unit 10 shown in FIG.
The pipeline execution control unit 10 includes NAND (Negative AND operation) circuits 31, 32, 33, and 38, a NOR (Negative OR operation) circuit 39, inverters 30, 36, and 37, and a P channel type transistor 34 and an N channel. A transfer gate 40 including a type transistor 35 is included. In FIG. 3, CMDA is a normal command input alone and a command preceding in a pipeline operation (to be described later) that is a feature of the present embodiment, and CMDB (P) follows the preceding command. This is a command related to pipeline operation. CE and / CE are chip enable signals which are one of the command signals (/ indicates a negative logic signal. The same applies to the following).

  A command CMDB (P) and a chip enable signal CE relating to the pipeline operation are input to the NAND circuit 31, and an output of the NAND circuit 31 is input to the NAND circuit 32. Further, the output of the NAND circuit 33 is input to the NAND circuit 32. The outputs of the NAND circuits 32 and 38 are input to the NAND circuit 33. That is, the NAND circuits 32 and 33 constitute an RS flip-flop.

  The output of the NAND circuit 32 can be input to the inverter 36 via the transfer gate 40 controlled by the chip enable signals CE and / CE. The inverters 36 and 37 have an input terminal connected to an output terminal of an inverter different from that of the inverter 36 and 37, and constitute a latch circuit.

  The output of the inverter 36 is input to the inverter 30, the output of the inverter 30 and the chip enable signal CE are input to the NAND circuit 38, and the output of the NAND circuit 38 is input to the NOR circuit 39. Further, the command CMDA is input to the NOR circuit 39, and the output of the NOR circuit 39 is output as the execution command CMDE.

  In the pipeline execution control unit 10 shown in FIG. 3, while the command CMDA is being executed (at this time, the chip enable signal CE is at the high level “H” (/ CE is at the low level “L”)) When input, the signal is latched by an RS flip-flop including NAND circuits 32 and 33 via the NAND circuit 31.

  Thereafter, when the chip enable signal CE changes to “L” (/ CE is “H”) in order to stop (end) the operation related to the command CMDA, the command CMDB is made up of the inverters 36 and 37 via the transfer gate 40. Transferred to the latch. When the chip enable signal CE becomes “H” again, the command CMDB is output as the execution command CMDE via the NAND circuit 38 and the NOR circuit 39.

FIG. 4 is a circuit diagram showing a configuration of the register circuit 51 that constitutes the command register 12 and the address register 13 shown in FIG. Note that the command register 12 and the address register 13 are configured by using a predetermined number of register circuits 51 shown in FIG. 4 as necessary.
The register circuit 51 includes inverters 52, 55, and 56, and a transfer gate 57 including a P-channel transistor 53 and an N-channel transistor 54.

  In the register circuit 51, the clock signal CLK is supplied to the control terminal (gate) of the transistor 53 via the inverter 52 and is also supplied to the control terminal (gate) of the transistor 54. The input signal IN can be input to the inverter 55 via the transfer gate 57, and the output of the inverter 55 is output as the output signal OUT. The inverters 55 and 56 are connected to each other at the input end and the output end to constitute a latch circuit.

FIG. 5 is a block diagram showing a configuration of the array control circuit 6 shown in FIG. 1. The array control circuit 6 includes circuits 61 to 71 excluding the memory cell array 7 shown in FIG.
In FIG. 5, a block selection instruction circuit 61, a word line (WL) selection instruction circuit 62, a sense amplifier (SA) selection instruction circuit 63, a column line (CL) selection instruction circuit 64, and an amplifier (AMP) activation instruction circuit 65 are The operation timings of the corresponding block selection circuit 66, word line selection circuit 67, sense amplifier activation circuit 68, column line selection circuit 69, and amplifier activation control circuit 70 are controlled.

  The block selection circuit 66 selectively activates the bit line transfer signal line BT and inactivates the precharge signal line BRS according to the block selection address signal BLSA supplied from the address decoder 4. The word line selection circuit 67 selectively activates the word line WL according to the word line selection address signal WLSA supplied from the address decoder 4. The sense amplifier activation circuit 68 activates the sense amplifier drive signal line LE.

  Column line selection circuit 69 selectively activates column line CL according to column line selection address signal CLSA supplied from address decoder 4. The amplifier activation control circuit 70 activates an amplifier drive signal line AEN for driving the amplifier 71. The amplifier 71 amplifies the data read from the memory cell 7 to the data signal control circuit 5 and outputs it.

  Here, the operations (including the selecting operation) of activating the signal lines by the circuits 66 to 70 described above are sequentially performed based on instructions from the corresponding instruction circuits 61 to 65, respectively.

  Specifically, based on the control signal supplied from the chip control circuit 3 and the array selection address signal ARSA supplied from the address decoder 4, an instruction is first issued from the block selection instruction circuit 61 to the block selection circuit 66. . Subsequently, an instruction is issued from the word line selection instruction circuit 62 to the word line selection circuit 67 on condition that an instruction from the block selection instruction circuit 61 is issued.

  Thereafter, similarly, sense amplifier selection instruction circuit 63 to sense amplifier activation circuit 68, column line selection instruction circuit 64 to column line selection circuit 69, and amplifier activation instruction circuit 65 to amplifier activation control circuit 70. The instructions are issued sequentially. However, an instruction from the amplifier activation instruction circuit 65 to the amplifier activation control circuit 70 is issued on condition that an instruction is issued from both the sense amplifier selection instruction circuit 63 and the column line selection instruction circuit 64.

  FIG. 6A is a circuit diagram showing a configuration of the memory cell array 7 shown in FIG. 1, in which one memory cell and its peripheral circuit are illustrated in the memory cell array 7 composed of a plurality of memory cells. Yes. FIG. 6B is a timing chart illustrating a data read operation in the circuit illustrated in FIG.

  In FIG. 6A, C1 is a capacitor, NT1 to NT17 are N-channel transistors, and PT1 to PT3 are P-channel transistors. The capacitor C1 and the transistor NT1 constitute a memory cell (1T1C type memory cell). A set of transistors NT3 to NT5 and a set of transistors NT13 to NT15 constitute precharge circuits 82 and 85, respectively. Transistors NT11, NT12, PT2, and PT3 constitute a sense amplifier 83. 84 is an inverter.

One-bit information is stored in the capacitor C1 of the memory cell 81. An operation at the time of reading data stored in the memory cell 81 (capacitance C1) will be described with reference to FIG.
Note that when none of the data read (read) operation, data write (write) operation, and refresh operation is performed, the bit line transfer signal lines BT0 and BT1 and the precharge signal line BRS are activated. , “H”. Therefore, the transistors NT3 to NT5 and NT13 to NT15 in the precharge circuits 82 and 83 and the transistors NT6, NT7, NT16 and NT17 are turned on, and the potentials of the bit lines BL and / BL are equal.

  When reading data, first, a bit line transfer signal line (bit line transfer signal line BT1 in the circuit shown in FIG. 6A) excluding the bit line transfer signal line BT0 corresponding to the memory cell 81, and a precharge signal The line BRS is inactivated and set to “L”. Therefore, the precharge circuits 82 and 83 are deactivated and the transistors NT16 and NT17 are deactivated (the reset state of the sense amplifier 83 is released). The bit line transfer signal line BT0 maintains “H”.

  Next, when the word line WL is selectively activated and becomes “H”, the transistor NT1 is turned on, and the data stored in the capacitor C1 is read out to the bit line BL. As a result, the potential of the bit line BL changes according to the data stored in the capacitor C1 (SQ1). Here, since the transistors NT6 and NT7 are conductive and the transistors NT16 and NT17 are nonconductive, the data (potential) of the bit lines BL and / BL is supplied to the sense amplifier 83 via the transistors NT6 and NT7. The

  Next, when the sense amplifier drive signal line LE is activated and becomes “H”, the transistors NT8 and PT1 are turned on and the power is supplied to operate the sense amplifier 83, and the data on the bit lines BL and / BL are transferred. Amplified (SQ2). Subsequently, when the column line CL is selectively activated to become “H”, the transistors NT9 and NT10 as the column gates are turned on, and the data of the amplified bit lines BL and / BL are transferred to the data buses DB and / DB. (SQ3).

Thereafter, the column line CL is deactivated to “L”, and the read data is rewritten to the memory cell 81 (capacitance C1) (SQ4), and then the word line WL is deactivated to “L”. To do. Further, by inactivating the sense amplifier drive signal line LE to “L”, the sense amplifier 83 is deactivated, and then all the bit line transfer signal lines BT0 and BT1 and the precharge signal line BRS are activated. To complete the data read operation.
Note that the data write operation to the memory cell 81 is the same as the conventional one, and the description thereof is omitted.

7A to 7C are diagrams for explaining the refresh operation of the semiconductor memory device 1 according to the first embodiment.
FIG. 7A shows drive waveforms of the command signal CMD and the refresh signal REFE supplied to execute the refresh operation in the semiconductor memory device 1 shown in FIG. When the semiconductor memory device 1 has a dedicated terminal (dedicated pin) for inputting the refresh signal REFE, as shown in FIG. 7A, command signals CMD (/ CE, / ADV, / OE, In a state where all of (/ WE) are inactivated ("H"), the refresh signal REFE is changed to "L" in a pulse form, whereby the semiconductor memory device 1 performs a refresh operation.

  When the semiconductor memory device 1 is not provided with a dedicated terminal for inputting the refresh signal REFE and the refresh operation is executed by the command signal CMD, the drive waveform shown in FIG. In addition, in a state where the command signal CMD except the chip enable signal / CE is inactivated, the chip enable signal / CE is changed to “L” in a pulse shape so that the refresh operation is performed in the semiconductor memory device 1. Anyway. Thus, when the refresh operation is to be executed only by the command signal CMD, a dedicated command for executing the refresh operation may be defined in advance.

  FIG. 7C is a diagram showing a flow of refresh operation in the semiconductor memory device 1. When execution of a refresh operation is instructed by an externally supplied refresh signal REFE (or a dedicated command as described above), the refresh signal REFE is first taken into the semiconductor memory device 1 via the interface circuit 8 (S11). Then, the chip control circuit 3 determines a command and determines that it is a refresh operation (S12). Subsequently, the address of the memory that performs the refresh operation is read (S13), and the core (the array control circuit 6 and the memory cell array 7) is activated (S14). Then, the array control circuit 6 performs a refresh operation on the memory cells in the memory cell array 7 corresponding to the address read in step S13 (S15), precharges and ends the processing (S16).

  8A and 8B are diagrams illustrating command examples of the semiconductor memory device 1 according to the first embodiment.

FIG. 8A shows a command example in the case where the semiconductor memory device 1 has a dedicated terminal for inputting the refresh signal REFE.
In the read command RD for performing the data read operation, the signals / CE and / OE are “L”, and the signals / WE and REFE are “H”. In the write command WR for performing the data write operation, the signals / CE and / WE are “L” and the signals / OE and REFE are “H”.
In the refresh command REF for performing the refresh operation, only the signal REFE is “L” and the other signals / CE, / OE and / WE are “H”. When the signals / CE and REFE are “H”, the standby state (non-operating state) is set.

FIG. 8B shows a command example defined only by the command signal CMD when the semiconductor memory device 1 does not have a dedicated terminal for inputting the refresh signal REFE.
The read command RD and the write command WR are the same as the example shown in FIG. 8A except that there is no signal REFE. Further, when the signal / CE is “H”, a standby state (non-operation state) is entered.
The refresh command REF changes the signal / CE to “L” in the form of a pulse while the signals / OE and / WE are “H”.

Next, a pipeline operation in the semiconductor memory device 1 according to the first embodiment will be described.
FIG. 9 is a timing chart showing an operation example of the semiconductor memory device according to the first embodiment. In FIG. 9, a chip enable signal / CE for setting the semiconductor memory device 1 in an operating state, an address valid signal / ADV indicating that the address signal ADD is valid, an output enable signal / OE, and a write enable signal / WE are shown. As an example, the semiconductor memory device 1 that is used as the command signal CMD and further uses the refresh signal REFE executes the refresh operation REF-data read operation RD (A) -data read operation RD (B) by pipeline operation. Yes. In FIG. 9, the core operation is a selection operation of the memory cell array 7 (operation performed by the array control circuit 6 with respect to the memory cell array 7), and the Peri operation is the operation of the array control circuit 6 and the memory cell array 7. This is an operation performed by the circuits 2 to 5 and 8 except for the above.

First, in response to the output of the refresh input request signal REFR from the refresh timer 2 via the interface circuit 8, the refresh signal REFE changes to “L” at time T11. The chip control circuit 3 decodes the command signal CMD and the refresh signal REFE, and determines that a refresh operation is requested from the outside.
At time T12, the refresh signal REFE changes to “H” and a refresh core operation is performed in the memory cell array 7.

  At time T13 when the memory cell array 7 is executing the refresh core operation, the chip enable signal / CE, the address valid signal / ADV, and the output enable signal / OE change to “L”. The chip control circuit 3 decodes these command signals CMD and determines that the external access request is the data read operation RD (A). The address decoder 106 takes in the address signal ADD and decodes it. At this time, since the refresh operation is being executed as the core operation, the chip control circuit 3 and the address decoder 4 hold the respective decode results related to the data read operation RD (A) in the command register 12 and the address register 13.

In this embodiment, the time T13 is used. However, since the control side knows in advance the time required for the refresh operation as the core operation, this read command is executed after a predetermined time has elapsed since the refresh signal REFE was changed. Enter.
Thereafter, the address valid signal / ADV changes to “H”.

  When the refresh operation as the core operation ends at time T14, the pipeline execution control unit 10 in the chip control circuit 3 instructs the execution of the data read operation RD (A) as the core operation, and the command register 12 and the address register On the basis of the decoding result held in 13, the execution of the data read operation RD (A) for the memory cell array 7 is started. Thereby, after time T15, the data 1A, 2A, 3A of the memory cells corresponding to the decoding result held in the address register 13 are sequentially read and output as the data signal DQ.

  When the address valid signal / ADV changes to “L” at time T16 during which the data read operation RD (A) is being performed on the memory cell array 7, the chip control circuit 3 decodes the command signal CMD and externally Is determined to be the data read operation RD (B). The address decoder 4 takes in the address signal ADD and decodes it. At this time, since the operation RD (A) is being executed in the memory cell array 7 as the core operation, the chip control circuit 3 and the address decoder 4 store the respective decode results related to the data read operation RD (B) in the command register 12. And held in the address register 13.

  Next, at time T17, the address valid signal / ADV and the chip enable signal / CE change to "H". When the chip enable signal / CE changes to “H”, the chip control circuit 3 instructs the array control circuit 6 to end the data read operation RD (A), and is executed in the memory cell array 7 at time T18. The data read operation RD (A) is completed. Note that a command that ends the operation by setting the chip enable signal / CE to “H” when the burst operation is performed in such a data read operation or the like is referred to as a termination command.

  At time T18, when the chip enable signal / CE changes to “L” again, the pipeline execution control unit 10 in the chip control circuit 3 instructs the execution of the data read operation RD (B) as the core operation. . At time T19, the execution of the data read operation RD (B) for the memory cell array 7 is started based on the decoding results held in the command register 12 and the address register 13.

  After time T20, the data 1B, 2B, 3B, 4B, and 5B of the memory cells corresponding to the decoding result held in the address register 13 are sequentially read and output as the data signal DQ. At time T21, the chip enable signal / CE changes to “H”, that is, when a termination command is issued, the data read operation RD (B) as the core operation ends at time T22.

  FIG. 10 is a timing chart showing another operation example of the semiconductor memory device according to the first embodiment. In FIG. 10, the semiconductor memory device 1 using the chip enable signal / CE, the address valid signal / ADV, the output enable signal / OE, and the write enable signal / WE as the command signal CMD and further using the refresh signal REFE is connected to the pipe. The case where the refresh operation REF−data write operation WR (A) −data write operation WR (B) is executed by the line operation is shown as an example.

  The operation shown in the timing chart of FIG. 10 differs only in that the write enable signal / WE is set to "L" instead of the output enable signal / OE and the data supplied by the data signal DQ is written to the memory cell. Since the operation example shown in the timing chart of FIG. 9 and the operation in the semiconductor memory device 1 are the same, detailed description is omitted. Note that times T31 to T42 in FIG. 10 correspond to times T11 to T22 shown in FIG. 9, respectively.

  As described above, according to the first embodiment, an operation for a memory cell array including a refresh operation is requested only by an external access request. Can be reduced, the latency in the data read operation and the cycle time in the data write operation can be shortened, the number of accessible times per unit time can be increased, and the bus occupancy rate related to the data signal DQ is increased. And the access operation can be speeded up. In addition, by providing a command register 12 and an address register 13 for holding the decoding result and realizing a pipeline operation in the preceding stage and the subsequent stage, the bus occupancy relating to the data signal DQ can be further increased, and the access operation can be performed. The speed can be increased. For example, when used in a circuit related to image processing and real-time processing, the processing speed can be increased.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 11 is a diagram showing a basic configuration of a semiconductor memory device 201 according to the second embodiment of the present invention. In FIG. 11, blocks having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.
The semiconductor memory device 201 is a pseudo SRAM and includes a chip control circuit 202, an address decoder 203, a refresh address control circuit 204, a data signal control circuit 5, an array control circuit 6, a memory cell array 7, and an interface circuit 205.

  The chip control circuit 202 comprehensively controls the operation of each circuit in the semiconductor memory device 1. The chip control circuit 202 is supplied with an external command signal (external command) CMD and an address signal ADD via the interface circuit 205. Then, the chip control circuit 202 decodes them by a decoder (not shown), and outputs a control signal to the array control circuit 6 based on the decoding result.

  The chip control circuit 202 determines that it is a request for a refresh operation when it is a combination of a predetermined address signal ADD and command signal CMD, and generates and outputs a refresh command REFC. That is, by accessing a specific address, the chip control circuit 202 determines that the request is for a refresh operation. This access is, for example, a regular command (data read, data write) or a combination thereof (for example, data read-data read, data read-data write-data write). Further, in the case of a combination of the predetermined address signal ADD and the command signal CMD, the access operation to the memory cell array 7 is not performed and data is not read from the memory cell.

  The address decoder 203 selectively decodes the external address signal ADD supplied via the interface circuit 8 or the refresh address signal REFA supplied from the refresh address control circuit 204 according to the refresh command REFC, and the decoding result Is output to the array control circuit 6.

  The refresh address control circuit 204 has an internal counter, operates the counter based on the refresh command REFC ′ supplied from the address decoder 203, and sends a signal REFA indicating the refresh address designated by the counter value to the address decoder 203. Output.

  The interface circuit 205 is used to exchange signals between the inside and outside of the semiconductor memory device 201. The interface circuit 205 receives a command signal CMD and an address signal ADD from the outside. Further, the data signal DQ is input to and output from the interface circuit 205. Further, a clock signal CLK for synchronizing input / output timings such as a command signal CMD and a data signal DQ is input from the outside and supplied to each circuit in the semiconductor memory device 201.

FIG. 12 is a diagram showing a functional configuration of the chip control circuit 202 shown in FIG.
The chip control circuit 202 includes a command decoder 211 as shown in FIG. The command decoder 211 receives the command signal CMD and the address signal ADD and decodes them. Further, the command decoder 211 outputs an execution command EXC or a refresh command REFC according to the decoding result. The refresh command REFC is output when the predetermined address signal ADD and the command signal CMD are combined as described above.

  The chip control circuit 202 shown in FIG. 12A is configured to output a refresh command REFC every time a combination of a predetermined address signal ADD and a command signal CMD is input. For example, the chip control circuit 202 may be configured as shown in FIG.

  A chip control circuit 202 illustrated in FIG. 12B includes a command decoder 212 and a counter 213, and the command decoder 212 corresponds to the command decoder 211 illustrated in FIG. In the chip control circuit 202 shown in FIG. 12B, the counter value of the counter 213 is incremented every time a combination of a predetermined address signal ADD and a command signal CMD is input (may be decremented). The counter 213 outputs a refresh command REFC when the counter value reaches a predetermined value. That is, the chip control circuit 202 shown in FIG. 12B outputs a refresh command REFC when a combination of a predetermined address signal ADD and a command signal CMD is input a predetermined number of times.

FIG. 13 is a diagram showing a functional configuration of the address decoder 203 shown in FIG.
The address decoder 203 includes a buffer 221 and a selector 222. The selector 222 receives the address EXA and the refresh address REFA based on the address signal ADD from the outside, and selectively outputs the address EXA or REFA to the buffer 221 in response to the refresh command REFC. For example, the selector 222 outputs the address REFA when the refresh command REFC is “H”, and outputs the address EXA when the refresh command REFC is “L”. Further, the address input to the buffer 221 is output from the address decoder 203.

FIG. 14 is a diagram for explaining the function of refresh address control circuit 204 shown in FIG.
The refresh address control circuit 204 includes a counter 231 and a refresh address determination unit 232 as shown in FIG. The counter 231 increments the counter value CNT every time the refresh command REFC ′ is input (may be decremented), and outputs the counter value CNT to the refresh address determination unit 232. The refresh address determination unit 232 determines and outputs the refresh address REFA based on the supplied counter value CNT.

  FIG. 14B is a diagram for explaining a method for determining the refresh address REFA in the refresh address control circuit 204. The counter 231 increments the counter value by 1 each time the refresh command REFC ′ is input. However, if the refresh command REFC 'is input when the counter value is n, the counter value returns to zero. Note that n corresponds to the total number of word lines that need to be selected in order to perform a refresh operation in the memory cell array 7.

  The counter value and the refresh address have a one-to-one correspondence. For example, when the counter value is 0, A0 is selected and determined as the refresh address REFA, and when the counter value is 1, A1 is selected as the refresh address REFA. It is determined.

FIG. 15 is a diagram for explaining the operation of the semiconductor memory device according to the second embodiment.
In FIG. 15, reference numeral 241 denotes a circuit related to the bank A, and includes a bank A243 in the memory cell array 7 and a control circuit 242 for controlling the bank A243. Reference numeral 244 denotes a circuit related to the bank B, which includes a bank B246 in the memory cell array 7, a control circuit 245 for controlling the bank B246, and a data signal control circuit 247. Reference numeral 248 denotes an interface circuit. Although the control circuits 242 and 245 are shown as one block, they have the functions of the chip control circuit 202, the address decoder 203, the refresh address control circuit 204, etc. shown in FIG.

  Thus, by providing the control circuits 242 and 245 for each bank 241 and 246 in the memory cell array 7, it is possible to control each bank 241 and 246 independently. Thus, for example, the bank B 246 can be accessed while performing a refresh operation in the bank A 241, and another bank that is not performing the refresh operation is accessed and data is read or written while performing a refresh operation in a certain bank. be able to.

FIG. 16 is a diagram showing an example of a refresh command in the semiconductor memory device according to the second embodiment.
Regardless of which bank is subjected to the refresh operation, in the case of a refresh command, the signals / CE and / OE are “L” and the signal / WE is “H”. The bank for performing the refresh operation is specified by using a part of the address signal ADD (in FIG. 16, the address signal ADD corresponding to the bits A0 to A2).

In addition, each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.

(Supplementary note 1) a memory cell array in which a plurality of memory cells for storing data are arranged;
A refresh request circuit for outputting a refresh request signal for requesting a refresh operation for holding data stored in the memory cell to the outside;
A processing circuit that decodes information related to an external access request to the memory cell array supplied from the outside, and instructs an operation to be executed in the memory cell array based on a decoding result;
An array control circuit for performing an operation on the memory cell array based on an instruction from the processing circuit;
The semiconductor memory device, wherein the external access request includes a refresh execution request in response to the refresh request signal.
(Supplementary note 2) The semiconductor memory device according to supplementary note 1, wherein the refresh request circuit has a timer function and outputs the refresh request signal to the outside whenever a certain period of time elapses.
(Supplementary note 3) The semiconductor memory device according to supplementary note 1, wherein the refresh execution request uses a signal from an individual signal line.
(Supplementary note 4) The semiconductor memory device according to supplementary note 1, wherein the refresh execution request uses a specific command.
(Supplementary note 5) The semiconductor memory device according to supplementary note 1, further comprising a register that holds a decoding result of information related to an external access request by the processing circuit.
(Supplementary Note 6) When the processing circuit receives a second external access request during execution of an operation corresponding to the first external access request in the memory cell array, the processing circuit relates to the second external access request. The information decoding result is held in the register, and after the operation corresponding to the first external access request is finished, an operation to be executed in the memory cell array is instructed based on the decoding result held in the register. The semiconductor memory device according to appendix 5, wherein:
(Supplementary note 7) A pipeline execution control circuit for instructing execution of the operation corresponding to the second external access request after the operation corresponding to the first external access request is completed in the memory cell array. The semiconductor memory device according to appendix 6, wherein:
(Supplementary note 8) The semiconductor memory according to Supplementary note 5, wherein the register includes a command register that holds a decoding result of command information related to the external access request, and an address register that holds a decoding result of address information. apparatus.
(Supplementary note 9) The semiconductor memory device according to supplementary note 1, wherein the operation related to the external access request is executed by a pipeline operation by the processing circuit and the array control circuit.
(Additional remark 10) The semiconductor memory device according to additional remark 1,
A control device for outputting information related to the external access request,
The memory system according to claim 1, wherein the control device receives the refresh request signal and outputs the refresh execution request as a response.
(Additional remark 11) The said control apparatus outputs the said refresh execution request within a fixed period after receiving the said refresh request signal, The memory system of Additional remark 10 characterized by the above-mentioned.
(Supplementary note 12) The control device performs an arbitration process between an access request related to reading or writing of data to the memory cell and the refresh execution request, and outputs an external access request based on the arbitration result The memory system according to appendix 10.
(Supplementary note 13) a memory cell array in which a plurality of memory cells for storing data are arranged;
A processing circuit for decoding command information and address information related to an external access request to the memory cell array supplied from the outside, and instructing an operation to be executed in the memory cell array based on a decoding result;
An array control circuit for performing an operation on the memory cell array based on an instruction from the processing circuit;
The processing circuit executes a refresh operation for holding data stored in the memory cell in the memory cell array when command information and address information relating to the external access request are in a predetermined combination. A semiconductor memory device, characterized by:
(Additional remark 14) It further has an address control circuit which controls the address which performs the above-mentioned refresh operation,
The address control circuit has a counter whose value changes for each predetermined value when command information and address information relating to the external access request are in a predetermined combination, and executes the refresh operation based on the counter value 14. The semiconductor memory device according to appendix 13, wherein an address is determined.
(Supplementary Note 15) The memory cell array includes a plurality of banks.
14. The semiconductor memory device according to appendix 13, wherein the processing circuit and the array control circuit are provided for each bank, and can be controlled independently.

1 is a block diagram illustrating a configuration example of a semiconductor memory device according to a first embodiment. 1 is a block diagram illustrating a configuration example of a memory system to which a semiconductor memory device according to a first embodiment is applied. It is a figure which shows the circuit structural example of the pipeline execution control part in 1st Embodiment. It is a figure which shows the circuit structural example of the register | resistor in 1st Embodiment. It is a figure which shows the structural example of the array control circuit in 1st Embodiment. FIG. 3 is a diagram illustrating a circuit configuration example of a memory cell of the memory cell array and its peripheral circuit in the first embodiment, and a data read sequence related to the memory cell. It is a figure for demonstrating the refresh operation | movement in 1st Embodiment. It is a figure which shows the example of a command of the semiconductor memory device by 1st Embodiment. 3 is a timing chart illustrating an operation example of the semiconductor memory device according to the first embodiment. 6 is a timing chart showing another operation example of the semiconductor memory device according to the first embodiment. It is a block diagram which shows an example of the fundamental structure of the semiconductor memory device by 2nd Embodiment. It is a figure for demonstrating the chip | tip control circuit in 2nd Embodiment. It is a figure for demonstrating the address decoder in 2nd Embodiment. It is a figure for demonstrating the refresh address control circuit in 2nd Embodiment. FIG. 10 is a diagram for explaining an operation of the semiconductor memory device according to the second embodiment. It is a figure which shows the example of a command of the semiconductor memory device by 2nd Embodiment. It is a block diagram which shows the structure of the conventional pseudo SRAM. It is a timing chart which shows the data read-out operation | movement of the conventional pseudo SRAM. It is a timing chart which shows the data write-in operation | movement of the conventional pseudo SRAM. It is a figure for demonstrating the problem in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 2 Refresh timer 3 Chip control circuit 4 Address decoder 5 Data signal control circuit 6 Array control circuit 7 Memory cell array 8 Interface circuit 10 Pipeline execution control part 12 Command register 13 Address register CLK Clock signal CMD Command signal REFR Refresh input Request signal REFE Refresh signal ADD Address signal DQ Data signal

Claims (10)

A memory cell array in which a plurality of memory cells for storing data are arranged;
A refresh request circuit for outputting a refresh request signal for requesting a refresh operation for holding data stored in the memory cell to the outside;
A processing circuit that decodes information related to an external access request to the memory cell array supplied from the outside, and instructs an operation to be executed in the memory cell array based on a decoding result;
An array control circuit for performing an operation on the memory cell array based on an instruction from the processing circuit;
The semiconductor memory device, wherein the external access request includes a refresh execution request in response to the refresh request signal.   2. The semiconductor memory device according to claim 1, wherein the refresh request circuit has a timer function and outputs the refresh request signal to the outside whenever a predetermined period elapses.   3. The semiconductor memory device according to claim 1, wherein the refresh execution request uses a signal from an individual signal line.   3. The semiconductor memory device according to claim 1, wherein the refresh execution request uses a specific command.   The semiconductor memory device according to claim 1, further comprising a register that holds a decoding result of information related to an external access request by the processing circuit.   When the processing circuit receives a second external access request during execution of an operation corresponding to the first external access request in the memory cell array, the decoding result of information related to the second external access request Is stored in the register, and after the operation corresponding to the first external access request is completed, an operation to be executed in the memory cell array is instructed based on a decoding result held in the register. The semiconductor memory device according to claim 5.   2. The semiconductor memory device according to claim 1, wherein the operation related to the external access request is executed by a pipeline operation by the processing circuit and the array control circuit. A semiconductor memory device according to claim 1;
A control device for outputting information related to the external access request,
The memory system according to claim 1, wherein the control device receives the refresh request signal and outputs the refresh execution request as a response. A memory cell array in which a plurality of memory cells for storing data are arranged;
A processing circuit for decoding command information and address information related to an external access request to the memory cell array supplied from the outside, and instructing an operation to be executed in the memory cell array based on a decoding result;
An array control circuit for performing an operation on the memory cell array based on an instruction from the processing circuit;
The processing circuit executes a refresh operation for holding data stored in the memory cell in the memory cell array when command information and address information relating to the external access request are in a predetermined combination. A semiconductor memory device, characterized by: An address control circuit for controlling an address for executing the refresh operation;
The address control circuit has a counter whose value changes for each predetermined value when command information and address information relating to the external access request are in a predetermined combination, and executes the refresh operation based on the counter value 10. The semiconductor memory device according to claim 9, wherein an address is determined.

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