JP2004252589A - Debugging support device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a debugging support device which performs detection of a memory space switching factor in debugging and switching control of a memory space instead of a central processing unit. <P>SOLUTION: This debugging support device 16 comprises a memory space switching factor detection part 12 for detecting an undefined instruction fetch or break point, and a memory space switching control part 13 for controlling the switching of the memory space from a user memory space 14 to a debugging memory space 17 in the detection of the undefined instruction fetch or break point. The memory space switching control part 13 switches the memory space from the user memory space 14 to the debugging memory space 17 for every instruction execution when a step execution break is permitted. When the memory space is switched to the debugging memory space 17, the memory space switching factor detection part 12 generates a forced interruption to a CPU 11. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a debug support device mounted on a microcomputer.
[0002]
A microcomputer may be equipped with a debugging support device for debugging a program such as firmware executed by the microcomputer. Such a microcomputer includes a user memory space that stores a program to be debugged and also serves as a work area when the program is executed, and a debug memory space that stores an interrupt processing program for performing debug processing. During debugging, the CPU (central processing unit) accesses both the user memory space and the debug memory space.
[0003]
[Prior art]
FIG. 6 is a block diagram functionally showing a schematic configuration of a conventional microcomputer equipped with a debug support device. As shown in FIG. 6, conventionally, a memory space switching factor detector 2 that realizes a function of detecting a switching factor between the user memory space 4 and the debug memory space 7 and a function of controlling switching of the memory space are realized. The memory space switching control unit 3 is provided in the CPU 1.
[0004]
Therefore, when the CPU 1 performs break point detection, undefined instruction fetch detection, or step execution break when the current memory space is in the user memory space 4, the CPU 1 starts forced interrupt processing. As a result, the memory space is switched to the debug memory space 7 via the memory space switching circuit 6 of the debug support device 5.
[0005]
On the other hand, when the current memory space is in the debug memory space 7, the CPU 1 switches the memory space to the user memory space 4 when detecting a RETI instruction (return interrupt instruction) fetch. At the same time, the CPU 1 executes a RETI instruction and performs a return for a forced interrupt when shifting from the user memory space 4 to the debug memory space 7.
[0006]
Further, in a conventional microcomputer equipped with a debug support device, a one-shot memory space switching signal is generated when accessing the user memory space from the debug memory space. Therefore, it is possible to access the user memory space from the debug memory space only for the next access when the memory space switching signal is generated.
[0007]
Further, a technology for switching a memory space between a debugged system and a debug support system is known for a debug support device (see Patent Document 1). A technique for debugging software arranged on a bank memory using an in-circuit emulator is known (see Patent Document 2).
[0008]
[Patent Document 1]
JP-A-2-28732
[Patent Document 2]
JP-A-5-113906
[0009]
[Problems to be solved by the invention]
However, the CPU of the conventional debug support device-equipped microcomputer (hereinafter referred to as an evaluation microcomputer) has become a microcomputer (hereinafter referred to as a mass production microcomputer) not equipped with a debug support device due to the multi-functionality for switching the memory space. ), The number of gates increases and the area increases. Therefore, there is a problem in that the CPU for the evaluation microcomputer and the CPU for the mass production microcomputer are not compatible, so that they must be prepared separately.
[0010]
Further, in the conventional evaluation microcomputer, data access exceeding the data width of the bus from the debug memory space to the user memory space cannot be performed with one instruction. For example, when the CPU reads or writes 16-bit data for an 8-bit bus width, it switches to the first user memory space in one shot, and the first 8-bit data is transferred to the user memory space. Then, the second switch to the user memory space and the remaining 8-bit data are accessed in one shot. Therefore, there is a problem that access efficiency from the debug memory space to the user memory space is poor.
[0011]
The present invention has been made in view of the above problems, and provides a debugging support device capable of detecting a memory space switching factor during debugging and controlling switching of a memory space, instead of a CPU. For the purpose. Another object of the present invention is to provide a debugging support device that enables continuous data access to a user memory space during debugging.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a debugging support apparatus according to the present invention includes a memory space switching factor detecting means for detecting an undefined instruction fetch or a breakpoint, and a memory space as a user memory space when an undefined instruction fetch or a breakpoint is detected. And a memory space switching control means for controlling switching when switching from the debug memory space to the debug memory space. The memory space switching control means switches the memory space from the user memory space to the debug memory space every time one instruction is executed when the step execution break is permitted. When switching the memory space to the debug memory space, the debug support device generates a forced interrupt to the CPU.
[0013]
According to the present invention, the debug support device can detect a memory space switching factor and switch the memory space from the user memory space to the debug memory space instead of the CPU.
[0014]
In the present invention, the memory space switching factor detecting means may detect the RETI instruction fetch, and the memory space switching control means may switch the memory space from the debug memory space to the user memory space at the time of detection. In this case, the debug support device can detect the RETI instruction fetch instead of the CPU and switch the memory space from the debug memory space to the user memory space.
[0015]
In order to achieve the above object, the debug support apparatus according to the present invention has a register that is set when access from the debug memory space to the user memory space is permitted, and this register is set. If the CPU access is a data access, a signal indicating that the memory space is a user memory space is output. If the CPU access is an opcode fetch or operand fetch, the memory space is a debug memory space. It has a memory space control means for outputting a signal. The register is cleared when the signal indicating the memory space is switched from the state indicating the user memory space to the state indicating the debug memory space.
[0016]
According to the present invention, as long as the CPU access is data access during debugging, the memory space becomes the user memory space, so that continuous data access to the user memory space is possible.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0018]
(Embodiment 1)
FIG. 1 is a block diagram functionally showing a schematic configuration of a debug environment by the debug support apparatus according to the first embodiment of the present invention. In FIG. 1, a CPU 11, a memory space switching factor detection unit 12, a memory space switching control unit 13, a user memory space 14, a debug support device 15, a memory space switching circuit 16, and a debug memory space 17 are constituent elements of an evaluation microcomputer. is there.
[0019]
The memory space switching factor detection unit 12 and the memory space switching control unit 13 are mounted on the debug support device 15. Therefore, in the first embodiment, the CPU 11 does not have a function of detecting a memory space switching factor and a function of controlling switching of the memory space. These functions are realized by the debug support device 15.
[0020]
FIG. 2 is a block diagram functionally showing the detailed configuration of the debug support apparatus 15. As shown in FIG. 2, the memory space switching factor detector 12 includes a break controller 21 and a plurality of comparators 22a, 22b, 22c, and 22d. Although four comparators are shown in FIG. 2, the number of comparators is increased or decreased according to the number of break factors such as an address break, an instruction break, an operand break, or a data break. Five or more may be sufficient. In the following description, for the sake of convenience, the first comparator 22a, the second comparator 22b, the third comparator 22c, and the fourth comparator 22d are used.
[0021]
The memory space switching factor detection unit 12 constantly monitors accesses performed by the CPU 11 to the user memory space 14 or the debug memory space 17 via the memory space switching circuit 16. Then, the first comparator 22a, the second comparator 22b, the third comparator 22c, and the fourth comparator 22d are assigned to various breakpoint codes and RETI instruction codes, respectively. The code is compared with the code fetched by the CPU 11.
[0022]
Here, in FIG. 2, in each of the comparators 22a, 22b, 22c, and 22d, the comparison target for the fetch code of the CPU 11 is clearly shown, and the codes of various break points are assigned to the corresponding first to third comparators 22a. , 22b, 22c, and shown as break factor 0, break factor 1 and break factor n. Further, the code of the RETI instruction is also extracted from the corresponding fourth comparator 22d and clearly shown.
[0023]
The break control unit 21 forces the CPU 11 when any of the first to third comparators 22a, 22b, and 22c matches the CPU 11 fetch code and the break point code, that is, when a break point is detected. Interrupt. In addition, when the step execution break is permitted, the break control unit 21 issues a forced interrupt to the CPU 11 every time one instruction is executed in the user memory space 14.
[0024]
The break control unit 21 also issues a forced interrupt to the CPU 11 when the CPU 11 fetches an undefined instruction. Although the undefined instruction fetch is detected by the memory space switching factor detector 12, the configuration for realizing this detection function is not shown.
[0025]
The memory space switching control unit 13 includes a forced interrupt / interrupt return detection unit 25 and an interrupt processing / return processing sequence control unit 26. The forced interrupt / interrupt return detection unit 25 detects that the CPU 11 has been forcedly interrupted by the break control unit 21. The forced interrupt / interrupt return detection unit 25 detects in the fourth comparator 22d that the fetch code of the CPU 11 matches the code of the RETI instruction.
[0026]
The interrupt processing / return processing sequence control unit 26 switches sequence control for switching the memory space from the user memory space 14 to the debug memory space 17 when the forced interrupt / interrupt return detection unit 25 detects the occurrence of a forced interrupt to the CPU 11. To do. The interrupt processing / return processing sequence control unit 26 performs sequence control for switching the memory space from the debug memory space 17 to the user memory space 14 when the RETI instruction is detected by the forced interrupt / interrupt return detection unit 25. .
[0027]
The memory space switching circuit 16 switches the memory space based on the sequence control of the interrupt processing / return processing sequence control unit 26. When a forced interrupt occurs, the CPU 11 performs an interrupt process. In addition, the CPU 11 executes a RETI instruction and performs a return process for a forced interrupt.
[0028]
Next, the operation of the apparatus shown in FIG. 2 will be described. When the current memory space is in the user memory space 14, when the CPU 11 detects that the CPU 11 has performed an undefined instruction fetch or breakpoint access, the memory space switching factor detector 12 generates a forced interrupt to the CPU 11. To do. Thereby, the CPU 11 starts an interrupt process. Further, when the occurrence of a forced interrupt to the CPU 11 is notified, the memory space switching control unit 13 outputs a signal for switching the memory space to the debug memory space 17 to the memory space switching circuit 16. Thereby, the memory space is switched to the debug memory space 17.
[0029]
When the step execution break is permitted, the memory space switching factor detection unit 12 generates a forced interrupt to the CPU 11 every time one instruction is executed in the user memory space 14. Thereby, the CPU 11 performs an interrupt process for every execution of an instruction. Further, the memory space switching control unit 13 outputs a signal for switching the memory space to the debug memory space 17 to the memory space switching circuit 16 every time one instruction is executed. As a result, the memory space is switched to the debug memory space 17 for each instruction.
[0030]
On the other hand, when the current memory space is in the debug memory space 17, when detecting that the CPU 11 has performed the RETI instruction fetch, the memory space switching factor detection unit 12 notifies the memory space switching control unit 13 of the fact. Based on the notification, the memory space switching control unit 13 outputs a signal for switching the memory space to the user memory space 14 to the memory space switching circuit 16. As a result, the memory space is switched to the user memory space 14. At the same time, the CPU 11 executes a RETI instruction and performs a return process for a forced interrupt when shifting from the user memory space 14 to the debug memory space 17.
[0031]
According to the first embodiment described above, the debug support device 15 is provided with the function of detecting the cause of switching the memory space and the function of controlling the switching of the memory space. 15 can switch the memory space. Therefore, since the evaluation microcomputer can be configured without increasing the number of functions, gates and size of the CPU 11, the CPU 11 for the evaluation microcomputer and the CPU for the mass production microcomputer can be compatible. it can. For example, in the case of an 8-bit CPU, although depending on the number of break factors to be defined, the gate area of the CPU can be improved by about 10 to 20% compared to the conventional case.
[0032]
(Embodiment 2)
FIG. 3 is a block diagram functionally showing a schematic configuration of a debug environment by the debug support apparatus according to the second embodiment of the present invention. In FIG. 3, a CPU 31, a user memory space 34, a debug support device 35, a memory space switching circuit 36, a debug memory space 37, a memory space control unit 38, a user memory space access control unit 41, and a memory space control unit main body 42 are evaluated. It is a component of the microcomputer.
[0033]
The memory space control unit 38 is mounted on the debug support device 35. The user memory space access control unit 41 and the memory space control unit main body 42 are mounted on the memory space control unit 38. The user memory space access control unit 41 realizes a function of performing continuous data access to the user memory space 34 during debugging.
[0034]
When the memory space is in the user memory space 34, the memory space control unit main body 42 switches the memory space to the debug memory space 37 after detecting the debug memory space switching factor. When the memory space is in the debug memory space 37, the memory space control unit main body 42 switches the memory space to the user memory space 34 after detecting the user memory space switching factor.
[0035]
FIG. 4 is a block diagram functionally showing the detailed configuration of the memory space control unit 38 of the debug support apparatus. As shown in FIG. 4, the user memory space access control unit 41 includes a selector 51, a user memory space access permission bit 52, and a rising detector 53.
[0036]
When the value of the user memory space access permission bit 52 is zero, the selector 51 supplies the output signal of the memory space control unit main body 42 as a signal indicating the memory space (memory space signal) to the memory space switching circuit 36. Further, when the value of the user memory space access permission bit 52 is 1, the selector 51 supplies an operation code signal or an operand signal as a memory space signal to the memory space switching circuit 36.
[0037]
Here, the output signal of the memory space control unit main body 42 indicates the user memory space 34 when it is zero, and indicates the debug memory space 37 when it is 1. The opcode signal or operand signal becomes 1 when the access of the CPU 31 is an opcode fetch or operand fetch, and becomes zero when the access of the CPU 31 is a data access. The memory space when the access of the CPU 31 is an opcode fetch or an operand fetch is a debug memory space 37. A memory space when the CPU 31 accesses data is a user memory space 34.
[0038]
The user memory space access permission bit 52 is a bit for permitting access from the debug memory space 37 to the user memory space 34, and is set by the CPU 31. When the user memory space access permission bit 52 is set, that is, when the value of the user memory space access permission bit 52 is 1, the next data access to the user memory space 34 is permitted. The user memory space access permission bit 52 is provided in a register in the debug support device 35 and constitutes a part of the debug memory space 37, but this is omitted in FIG.
[0039]
The user memory space access permission bit 52 is cleared and returned to zero when the memory space signal output from the selector 51 changes from zero to one. The rising detector 53 detects that the memory space signal output from the selector 51 has changed from zero to one.
[0040]
Next, the operation of the apparatus shown in FIG. 4 will be described. When the current memory space is in the debug memory space 37, if the user memory space access permission bit 52 is set, the memory space signal output from the selector 51 is obtained from the output signal of the memory space control unit main body 42 from the opcode signal or Switch to operand signal.
[0041]
Thereafter, when the access performed by the CPU 31 is data, the memory space becomes the user memory space 34, and the memory space signal output from the selector 51 is zero. Therefore, since the rise detector 53 does not detect the rise of the memory space signal, the user memory space access permission bit 52 is not cleared and remains set.
[0042]
In this state, when the CPU 31 subsequently performs data access, the memory space becomes the user memory space 34. Thus, until the CPU 31 next accesses the opcode or operand, the memory space becomes the user memory space 34, and the CPU 31 continuously accesses the user memory space 34.
[0043]
When the access of the CPU 31 becomes an opcode or an operand, the memory space signal output from the selector 51 is switched to 1. As a result, the rise detector 53 detects the rise of this memory space signal, and the user memory space access permission bit 52 is cleared and returns to zero. The memory space is switched to the debug memory space 37.
[0044]
A timing chart from when the user memory space access permission bit 52 is set to when it is cleared is shown in FIG. In FIG. 5, “bus” indicates not the specific data but the type of access, that is, the operation code, operand or data. In the timing chart shown in FIG. 5, data access to the user memory space 34 is continuously performed for data 0 and data 1 on the bus. Then, the memory space signal is switched from zero to 1 by the next opcode fetch of data access to data 1, and the user memory space access permission bit 52 is returned from 1 to zero.
[0045]
According to the second embodiment described above, while the user memory space access permission bit 52 is set, the memory space becomes the user memory space 34 as long as the access of the CPU 31 is data access. The space 34 can be accessed. Therefore, the access efficiency for continuous data to the user memory space 34 at the time of debugging is improved.
[0046]
In the above, this invention is not restricted to each embodiment mentioned above, A various change is possible. For example, the debug memory space and the user memory space may be provided in physically separate memories, or may be provided in the physically same memory.
[0047]
(Supplementary note 1) A debugging support device mounted on a microcomputer together with a central processing unit capable of accessing both a user memory space and a debugging memory space during debugging,
A debugging support device comprising: a memory space switching factor detecting means for detecting a factor for switching between a user memory space and a debugging memory space by monitoring access of the central processing unit during debugging.
[0048]
(Supplementary note 2) The debug support device according to supplementary note 1, further comprising memory space switching control means for controlling switching when switching between the user memory space and the debug memory space during debugging.
[0049]
(Supplementary Note 3) When the memory space switching factor detecting unit detects an undefined instruction fetch as a factor for switching the memory space, the memory space switching control unit controls the memory space to switch from the user memory space to the debug memory space. The debug support device according to appendix 2, characterized in that:
[0050]
(Supplementary Note 4) When the memory space switching factor detecting means detects a breakpoint set in advance as a factor for switching the memory space, the memory space switching control means changes the memory space from the user memory space to the debug memory space. The debug support device according to appendix 2, wherein control to switch to is performed.
[0051]
(Supplementary note 5) The debug support according to supplementary note 2, wherein the memory space switching control means performs control to switch the memory space from the user memory space to the debug memory space for each instruction execution when step execution break is permitted. apparatus.
[0052]
(Supplementary Note 6) When the memory space switching factor detecting unit detects a return interrupt instruction fetch as a factor for switching the memory space, the memory space switching control unit controls the switching of the memory space from the debug memory space to the user memory space. The debug support device according to any one of appendices 2 to 5, wherein:
[0053]
(Supplementary note 7) The memory space switching factor detecting means generates a forced interrupt to the central processing unit when the memory space is switched from the user memory space to the debug memory space by the memory space switching control means. The debug support device according to any one of appendices 2 to 5.
[0054]
(Supplementary note 8) A debugging support device mounted on a microcomputer together with a central processing unit capable of accessing both a user memory space and a debugging memory space during debugging,
While access from the debug memory space to the user memory space is permitted, a signal indicating that the memory space is the debug memory space is output if the central processing unit access is an opcode fetch or operand fetch, A debugging support device comprising memory space control means for outputting a signal indicating that the memory space is a user memory space if the access of the processing device is data access.
[0055]
(Supplementary note 9) A debugging support device mounted on a microcomputer together with a central processing unit capable of accessing both a user memory space and a debugging memory space during debugging,
An access permission bit that is set when access from the debug memory space to the user memory space is permitted;
Memory space control means for outputting zero when the memory space is a user memory space and outputting 1 when the memory space is a debug memory space;
While the access permission bit is set, select and output a signal that becomes 1 if the access of the central processing unit is an opcode fetch or operand fetch, and becomes zero if the access of the central processing unit is a data access, On the other hand, when the access permission bit is cleared, a selector that selects and outputs a signal output from the memory space control means;
A debugging support device comprising:
[0056]
(Supplementary note 10) The debug support device according to supplementary note 9, further comprising a detector that clears the access permission bit when it is detected that the output signal of the selector is switched from zero to one.
[0057]
(Supplementary Note 11) A memory space switching circuit is further provided that sets the memory space as a user memory space when the output signal of the selector is zero, and sets the memory space as a debug memory space when the output signal of the selector is 1. The debug support apparatus according to Supplementary Note 10, wherein
[0058]
(Supplementary Note 12) The memory space switching factor detection means is configured to compare a break factor set in advance with the access of the central processing unit, and to the central processing unit when the comparison result in the comparator matches. The debug support device according to appendix 1, further comprising break control means for generating a forced interrupt.
[0059]
(Supplementary note 13) The debug support device according to supplementary note 12, wherein a plurality of the comparators are provided according to the type of break factor.
[0060]
(Supplementary Note 14) The memory space switching control means includes: a forced interrupt detection means for detecting that the break control means has generated a forced interrupt to the central processing unit; and a memory based on a detection result of the forced interrupt detection means. 13. The debug support apparatus according to appendix 12, further comprising an interrupt processing control unit that performs control for switching the space from the user memory space to the debug memory space.
[0061]
(Supplementary note 15) The debug support device according to supplementary note 1, wherein the memory space switching factor detection means includes a comparator for comparing the return interrupt instruction code with the fetch code of the central processing unit.
[0062]
(Supplementary Note 16) The memory space switching control means detects an interrupt return detection means for detecting a return interrupt instruction fetch based on the comparison result of the comparator, and sets the memory space as a debug memory based on the detection result of the interrupt return detection means. 16. The debug support device according to appendix 15, further comprising return processing control means for performing control for switching from space to user memory space.
[0063]
【The invention's effect】
According to the present invention, it is possible to obtain a debug support device in which a function for detecting a factor for switching a memory space and a function for controlling switching of a memory space are provided. In addition, according to the present invention, as long as the CPU access is data access during debugging, it is possible to obtain a debug support device that enables continuous data access to the user memory space.
[Brief description of the drawings]
FIG. 1 is a block diagram functionally showing a schematic configuration of a debug environment by a debug support apparatus according to a first embodiment of the present invention;
FIG. 2 is a block diagram functionally showing a detailed configuration of the debug support apparatus according to the first exemplary embodiment of the present invention;
FIG. 3 is a block diagram functionally showing a schematic configuration of a debug environment by the debug support apparatus according to the second embodiment of the present invention;
FIG. 4 is a block diagram functionally illustrating a detailed configuration of a memory space control unit of the debug support device according to the second exemplary embodiment of the present invention;
FIG. 5 is a timing chart showing a memory space switching operation timing by the debug support device according to the second exemplary embodiment of the present invention;
FIG. 6 is a block diagram functionally showing a schematic configuration of a conventional microcomputer equipped with a debug support device.
[Explanation of symbols]
11,31 CPU
12 Memory space switching factor detector
13 Memory space switching control unit
14,34 User memory space
15, 35 Debug support device
16, 36 Memory space switching circuit
17, 37 Debug memory space
38 Memory space controller
41 User memory space access controller
42 Memory space control unit body
51 selector
52 User memory space access permission bit
53 Rising detector

Claims (10)

A debugging support device mounted on a microcomputer together with a central processing unit capable of accessing both a user memory space and a debugging memory space during debugging,
A debugging support device comprising: a memory space switching factor detecting means for detecting a factor for switching between a user memory space and a debugging memory space by monitoring access of the central processing unit during debugging. 2. The debugging support apparatus according to claim 1, further comprising a memory space switching control unit that controls switching when switching between the user memory space and the debugging memory space during debugging. When the memory space switching factor detection means detects an undefined instruction fetch as a factor for switching the memory space, the memory space switching control means performs control to switch the memory space from the user memory space to the debug memory space. The debugging support device according to claim 2, wherein When the memory space switching factor detecting unit detects a breakpoint set in advance as a factor for switching the memory space, the memory space switching control unit performs control to switch the memory space from the user memory space to the debug memory space. The debugging support apparatus according to claim 2, wherein the debugging support apparatus performs the debugging. 3. The debug support apparatus according to claim 2, wherein the memory space switching control unit performs control to switch the memory space from the user memory space to the debug memory space for each instruction execution when step execution break is permitted. When the memory space switching factor detection means detects a return interrupt instruction fetch as a factor for switching the memory space, the memory space switching control means performs control to switch the memory space from the debug memory space to the user memory space. The debug support device according to any one of claims 2 to 5, wherein 3. The memory space switching factor detection means generates a forced interrupt to the central processing unit when the memory space is switched from a user memory space to a debug memory space by the memory space switching control means. The debug support device according to any one of 5 above. A debugging support device mounted on a microcomputer together with a central processing unit capable of accessing both a user memory space and a debugging memory space during debugging,
While access from the debug memory space to the user memory space is permitted, a signal indicating that the memory space is the debug memory space is output if the central processing unit access is an opcode fetch or operand fetch, A debugging support device comprising memory space control means for outputting a signal indicating that the memory space is a user memory space if the access of the processing device is data access. A debugging support device mounted on a microcomputer together with a central processing unit capable of accessing both a user memory space and a debugging memory space during debugging,
An access permission bit that is set when access from the debug memory space to the user memory space is permitted;
Memory space control means for outputting zero when the memory space is a user memory space and outputting 1 when the memory space is a debug memory space;
While the access permission bit is set, select and output a signal that becomes 1 if the access of the central processing unit is an opcode fetch or operand fetch, and becomes zero if the access of the central processing unit is a data access, On the other hand, when the access permission bit is cleared, a selector that selects and outputs a signal output from the memory space control means;
A debugging support device comprising: The debug support device according to claim 9, further comprising a detector that clears the access permission bit when it is detected that the output signal of the selector is switched from zero to one.

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