JPH04264923A - Information processor - Google Patents

Abstract

PURPOSE:To prevent prefetching failure by providing a loop counter circuit which counts the number of times of loop when the loop instruction of the number of times of loop preset in a branch predicting function as a branching instruction is generated. CONSTITUTION:In the case that the branching instruction prefetched first is executed by an instruction executing means 6, and branching is executed, a branch prediction circuit 7 is informed of branching condition affirmation BCA. At that time, if a number of times of loop setting instruction LCS is added previously, the loop counter circuit 101 of a loop count table 10 is informed of this. Next, the branch prediction circuit 7 executes the prefetching of the instruction succeeding the branching instruction prefetched first, and stores a branching destination address in a prefetch pointer 8. This stored branching destination address is prefetched by an instruction prefetching means 1 as a prefetching address PFA.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a branch prediction function.

0002

2. Description of the Related Art A branch prediction function of an information processing device predicts a branch destination instruction, which is an instruction to be executed next to a branch instruction, when a branch instruction occurs.

FIG. 2 is a flowchart showing an example of a conventional information processing apparatus of this type.

As shown in FIG. 2, the conventional branch prediction function of this type of information processing apparatus uses a cache memory as a branch prediction table 20.

When a branch occurs, the branch address 22 of the branch instruction S4, which is the instruction where the branch occurred, and the branch destination address 21 of the branch destination instruction S2, which is the instruction to which the branch occurs, are stored in the cache memory. . Furthermore, a valid bit 23 is set. Next, when a branch instruction is fetched, a search is made to see if the branch address 22 of the branch instruction S4 is stored in the branch prediction table 20. At this time, only branch destination addresses 21 for which valid bits are set in the branch prediction table 20 are searched.

If the branch instruction address 22 is stored, the instruction S2 at the branch destination address 21 stored as the branch destination of the branch instruction S4 is fetched. If the branch instruction address 22 is not stored, the branch instruction S4
The branch address 22 and the branch destination address 21 of the branch destination S2 are stored in the branch prediction table 20, and a valid bit 23 is set.

[0007]

[Problems to be Solved by the Invention] In the above-mentioned conventional information processing device, the branch prediction function stores the branch address of a branch instruction and the address of the branch destination when a branch occurs, and When prefetching, the instruction at the predicted branch destination is prefetched, not the instruction that follows, so even if the last branch instruction when exiting from the loop instruction is prefetched, the subsequent instruction will not be prefetched. The disadvantage was that it was not carried out and failed. As a result, there is a drawback that time loss occurs in pipeline processing, etc., and the performance of the processing device is degraded.

[0008]

Means for Solving the Problems The information processing apparatus of the present invention has a branch prediction function that predicts a branch destination instruction that is the next execution instruction of the branch instruction when a branch instruction occurs. The branch prediction function includes a loop counter circuit that counts the number of loops when a loop instruction of a predetermined number of loops is generated as the branch instruction.

[0009]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention.

As shown in FIG. 1, the information processing apparatus of this embodiment includes an instruction prefetch means 1, an instruction predecode means 2, an instruction decode effective address generation means 3, an address conversion means 4, and an operand access means. 5, an instruction execution means 6, a branch prediction circuit 7, a prefetch pointer 8, a branch prediction table 9, and a loop count table 10.

[0012] Here, the components 1 to 6 include those based on software.

[0013] The branch prediction table 9 contains the branch destination address 9
1, a branch address 92, and a comparator 93.

The loop count table 10 has a loop counter circuit 101, a loop counter 102, and a valid bit 103.

Next, the operation of this embodiment will be explained.

First, when a branch instruction is fetched during program execution, this branch instruction is detected by the address conversion means 4 and is notified to the branch prediction circuit 7 as a branch instruction detection IBD.

Next, the branch prediction circuit 7 stores the address from the address conversion means 4 in the prefetch pointer 8 as a predicted branch address BPA.

Next, the comparator 93 of the branch prediction table 9 compares the stored branch prediction address BPA with the branch address 92 of the branch prediction table 9 to search for a match. At this time, only the loop count table 10 whose valid bit 103 is set in advance is searched. As a result of the search, if there is no matching address, the branch predicted address BPA stored in the prefetch pointer 8 is prefetched as is by the instruction prefetch means 1 as the prefetch address PFA. Furthermore, the instruction following this branch instruction is prefetched.

When the previously prefetched branch instruction is executed by the instruction execution means 6 and a branch is taken, the branch prediction circuit 7 is notified of the branch condition determination BCA. At that time, if the loop count setting command LCS is added, this is notified to the loop counter circuit 101 of the loop count table 10.

Next, the branch prediction circuit 7, which has been informed of the branch condition determination BCA, prefetches the instruction following the previously prefetched branch instruction, and stores the branch destination address in the prefetch pointer 8. This stored branch destination address is prefetched by the instruction prefetch means 1 using it as a prefetch address PFA. At the same time, branch destination address 91 and branch address 9 are added to branch prediction table 9.
Register 2. At that time, if the loop count setting command LCS has been added, the loop count is set in the loop counter 102 of the loop count table 10, and the valid bit 103 is set.

Next, the comparator 93 of the branch prediction table 9 compares the stored branch prediction address BPA with the branch address 92 of the branch prediction table 9 to search for a match. If a matching address is found as a result of the search, a hit detection signal HD is output to inform the branch prediction circuit 7 of the branch destination address 91 registered in the branch prediction table 9. The branch prediction circuit 7 stores this branch destination address 91 in the prefetch pointer 8, and prefetches this address 91 using the instruction prefetch means 1 as the prefetch address PFA.

The hit detection signal HD is also output to the loop counter circuit 101 of the loop count table 10. The loop counter circuit 101 decrements the loop counter 102 corresponding to the branch address 92 by one. If the loop counter 102 is 0, no settings are made. Furthermore, if the loop counter 102 becomes 0 as a result of decrementing, the setting of the valid bit 103 is canceled and the branch prediction table 9
, and in the next branch instruction, the subsequent instruction is prefetched.

[0023]

As described above, the information processing device of the present invention includes a loop counter circuit that counts the number of loops when a loop instruction with a preset number of loops is generated as a branch instruction in the branch prediction function. By preparing,
When prefetching the last branch instruction when exiting from a loop instruction during the execution of a loop instruction, prefetching is performed not for the instruction at the predicted branch destination but for the subsequent instruction, which has the effect of preventing prefetch failures. As a result, no time loss occurs in pipeline processing, etc., and the performance of the processing device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an information processing device of the present invention.

FIG. 2 is a flowchart showing an example of a conventional information processing device.

[Explanation of symbols]

1 Instruction prefetch means 2 Instruction predecode means 3 Instruction decode effective address generation means 4
Address conversion means 5 Operand access means 6 Instruction execution means 7 Branch prediction circuit 8 Prefetch pointers 9, 20 Branch prediction table 10 Loop count table 21, 91 Branch destination address 22, 92 Branch address 23, 103 Valid bit 93 Comparator 101 Loop Counter circuit 102 loop counter

Claims (2)

[Claims] 1. An information processing device having a branch prediction function that predicts a branch destination instruction that is an instruction to be executed next to the branch instruction when a branch instruction occurs, wherein the branch prediction function predicts a branch destination instruction that is an instruction to be executed next to the branch instruction. An information processing device comprising: a loop counter circuit that counts the number of loops when a loop instruction for the number of loops is generated. 2. The branch prediction function includes a prefetch pointer for prefetching an instruction, a branch prediction table having a branch destination address and a comparator, a loop count table having the loop counter circuit and a valid bit, and the branch instruction. and a branch prediction circuit that performs a process of extracting the branch destination instruction when the branch instruction is detected, and when the branch instruction is detected, the branch prediction circuit sets the address stored in the prefetch pointer and the valid bit. The comparator compares the branch destination address with the branch destination address and extracts it as the next execution instruction, the loop counter circuit detects the set value of the number of loops, and subtracts by 1 for each execution of the loop instruction, 2. The information processing apparatus according to claim 1, wherein the setting of the valid bit is canceled when the set value reaches 1.