JPH10124313A - Parallel processing computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the necessity of complicated hardware and to prevent the reduction of performance due to inter-instruction dependent relation or the like by including mutual dependent relation such as register interference in an instruction string of a certain program and executing an instruction of another program during the reset of the dependent relation. SOLUTION: A program identifier(ID) 1 corresponding to a certain program is added to instructions fetched by instruction fetching parts 1a to 1c and the ID 1 added instructions are sent to an instruction merging part 2 at intervals. When two or more instructions are simultaneously sent from the fetching parts 1a to 1c, the merging part 2 orders these sent instructions and sends the instructions to an instruction decoding part 4 in order. The decoding part 4 interprets the instructions and reads out data from an internal storage device (register) 3 corresponding to the program ID 1. An operation part 5 accesses data stored in the internal storage device 3 corresponding to the program ID 1 or a main storage device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing computer for executing a plurality of programs in parallel at an instruction level.

[0002] With the recent increase in complexity and scale of programs, there is a demand for faster processing in computer systems. For this reason, the operation cycle of the processor of the computer has been accelerated, but due to technical and physical limitations, a parallel processing computer that executes a plurality of instructions at the same time is required.

[0003]

2. Description of the Related Art FIG. 3 schematically shows a conventional instruction-level parallel processing computer. 2. Description of the Related Art A conventional parallel processing computer at an instruction level uses a pipeline method in which the execution of one instruction is divided into a plurality of stages and each stage is executed in parallel.

FIG. 3 shows the concept of pipeline processing by a pipeline system in which the execution of the above-mentioned one instruction is divided into a plurality of stages and each stage is executed in parallel. IF denotes an instruction fetch stage, D is a decode stage for interpreting the fetched instruction, E is an operation stage for executing the interpreted instruction, and W is a stage for storing the operation result of the operation stage in a register or the like.

In this case, for example, when the operation result of the instruction 1 is used by the instruction 2, the E stage of the instruction 2 cannot be executed until after the W stage of the instruction 1 is completed. As described above, in the instruction 2, the D stage is extended to two stages, and the characteristic of the pipeline type parallel processing cannot be utilized.

That is, in one program, there are many cases where, for example, instructions having, for example, register dependencies exist in the instruction sequence in close proximity, so that the number of pipelines and stages in the processor of the parallel processing computer is reduced. By increasing or preparing a large number of arithmetic units, many instructions can be executed in parallel. However, a subsequent instruction (for example, the example of the instruction 2) until the dependency between the instructions is eliminated. Execution of a program, or incorrect execution by parallel execution, for example,
In the case of a branch instruction, the instruction sequence at the branch destination or the following instruction sequence is pre-executed, and the time when the branch destination is determined (E stage)
Thus, a so-called recovery process for discarding the useless process executed in advance and returning to the original state, a unit for storing the instruction of the branch destination at the time of the branch prediction, a method required for the branch prediction, It is necessary to have control means in the processor.

[0007]

Therefore, in a conventional instruction level parallel processing computer, even if a processor can execute many instructions in parallel, for example, the parallel processing is performed by an instruction having a register dependency. There was a problem that the capability could not be fully utilized, the performance was degraded due to the halt of the execution of the subsequent instruction, and the hardware was complicated by hardware means for eliminating register dependencies and the like.

In view of the above-mentioned drawbacks, the present invention focuses on the fact that, while executing a program having a large number of instructions having dependencies, the instructions between the programs do not have the above-described register dependency, and are independent of a plurality of programs. To provide a parallel processing computer that can achieve the same or near performance as when there are no dependencies between instructions without requiring complicated hardware by taking out instructions and executing them in parallel It is intended for.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. The above problem is solved by a parallel processing computer configured as follows.

A plurality of instruction fetch units 1a, 1b,..., 1c, which fetch instructions independently from a plurality of programs stored in one or a plurality of main storage devices and add a program identifier to each fetched program instruction. And an instruction merging unit 2 that receives the extracted instructions, assigns them to the instruction decoding unit 4 and sends the instructions to the instruction decoding unit 4, interprets the instruction having the program identifier, and if necessary, stores an internal storage device in the instruction ( Register), an internal storage device address is newly calculated from the address of the register 3 and the program identifier, and an instruction decoding unit 4 for reading data from the address is received.The program identifier and the internal storage device address are received, and the internal storage device address in the instruction is received. And a new internal storage address from the program identifier and write data to that address, or replace the main storage address in the instruction with Newly calculated main storage addresses and a program identifier, configured to include a calculating unit 5 to access that address.

There are a number of instruction fetch units 1a, 1b, to 1c according to the degree of parallelism to be realized. For example, by having four instruction fetch units, a parallel processing computer that executes four instructions in parallel can be realized.

In the processor of the parallel processing computer according to the present invention, as shown in FIG. 1, the instruction fetch units 1a, 1b,
1c independently retrieve instructions of a plurality of programs stored in one or more main storage devices.

In this case, when a plurality of programs are stored in one main storage device, for example, a main storage device capable of multi-port access is required, or each program is stored in a different bank. In addition, different banks are accessed and machine instructions of different programs are fetched every machine cycle by a known interleave method. When each of the plurality of programs is stored in another main storage device, an instruction is extracted from the corresponding program by independently accessing each main storage device.

In this manner, the instruction fetch units 1a, 1b,
A program identifier corresponding to the program is added to the instruction fetched in 1c and sent to the instruction merging unit 2. The instruction merging unit 2 sequentially sends the transmitted instructions to the instruction decoding unit 4. At this time, when instructions are sent from two or more instruction fetch units 1a, 1b, to 1c at the same time, the sent instructions are put in order and the instruction decode units are sequentially put in order.
Send it to 4.

The instruction decoding unit 4 interprets the instruction, and in the case of an instruction requiring data of a general-purpose register,
Reads data from internal storage device (register) 3,
At this time, data is read from the internal storage device (register) 3 corresponding to the program identifier added to the instruction. That is, the parallel processing computer of the present invention includes, for example, R1, R2,..., R16 corresponding to the program identifier as general-purpose registers R1, R2,.

An operation unit 5 for performing various operations accesses an internal storage device (general-purpose register) 3 corresponding to the program identifier and data in a main storage device. or,
At the time of branch instruction processing, the arithmetic unit 5 sends the designated address of the next instruction obtained by the arithmetic unit 5 to the instruction fetch units 1a, 1b, to 1c corresponding to the program identifier.

In each of the instruction fetch units 1a, 1b, to 1c,
Since the instructions of the own program are configured to be sent to the instruction merge unit 2 at intervals so as not to cause a dependency between the instructions of the own program, the instruction No register interference).
Therefore, even in a program having an instruction having the register interference relationship, as described above, the next instruction is not sent until the dependency is resolved.
Since the instruction of another program can be executed, the instruction decoding unit 4 and the arithmetic unit 5 do not stop the execution of the instruction unlike the related art, and also have a hardware for eliminating a complicated dependency. Hardware, for example, the above-described register interference detection means, recovery means, storage device for branch prediction, and control means are not required, and the pipeline processing can be executed smoothly.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing the principle of the present invention, and FIG.
FIG. 2A is a view showing one embodiment of the present invention, and FIG.
Shows an example of the configuration of the parallel processing computer of the present invention, and FIG.
Shows an example in which a program identifier is added to an instruction.

In an embodiment of the present invention, a plurality of instructions are fetched independently from a plurality of programs stored in one or a plurality of main storage devices, and a program identifier is added to each fetched program instruction. Instruction fetching units 1a, 1b, to 1c, an instruction merging unit 2 which receives the fetched instructions, assigns them to an order, and sends them to an instruction decoding unit 4, interprets instructions having the above program identifier, and If this is the case, a new internal storage device address is calculated from the address of the internal storage device (register) 3 in the instruction and the program identifier, and an instruction decoding unit 4 for reading data from that address. Receiving and calculating a new internal storage address from the internal storage address and the program identifier in the instruction, and writing data to the address, or Newly from the main memory address and a program identifier in the instruction to calculate a main storage address, and a calculation unit 5 to access that address is the means necessary to the embodiment of the present invention. Note that the same reference numerals indicate the same object throughout the drawings.

Hereinafter, the configuration and operation of the parallel processing computer according to the present invention will be described with reference to FIG. 2 while referring to FIG.
In FIG. 2A, a, b, and c are a plurality of program areas, which may be arranged on one main storage device. May be arranged in the main storage device, but when a plurality of program areas are arranged in one main storage device, as described above, the main storage device having a multi-port, At the same time, if it is necessary to be able to fetch a plurality of instructions, or if the programs a, b,..., C are stored in mutually different banks, a known interleave method Is accessed to retrieve a plurality of instructions. When each of the programs a, b, to c is arranged in a separate main storage device, a plurality of instructions can be read out independently by accessing each main storage device independently. .

In the instruction fetch units 1a, 1b, to 1c, program counters PCa, PCb, P indicating the address of the instruction to be read are provided.
Cc and corresponding program identifiers PIDa, PIDb, P
Each has an IDc.

The instruction fetch units 1a, 1b, to 1c fetch the instructions ca, cb, cc from the corresponding program areas a, b, c in accordance with the program counters PCa, PCb, PCc, and program identifiers PIDa, PIDb, PIDc. Is added to the extracted instructions ca, cb, cc and sent to the instruction merging section 2.

The instruction fetch units 1a, 1b,..., 1c increment the values of the program counters PCa, PCb, PCc by one. After detecting the completion signal sent based on the program identifier from, the process of retrieving the next instruction is repeated again. At this time, if the type of the completion signal of the preceding instruction is, for example, an inter-register operation instruction or the like, there is a risk of register interference between the instruction and a subsequent instruction. Will never occur and start fetching the next instruction. When the preceding instruction is a branch instruction, since the branch destination is determined, the branch destination having the determined branch destination address set in the program counters PCa, PCb, and PCc is read. , So that a branch prediction and a recovery process accompanying the branch prediction are not required.

As shown in FIG. 2B, the program identifier is added to the instruction by adding a field of the number of bits capable of identifying a plurality of programs to the bit field of the instruction code. can do.

The instruction merging section 2 includes the above-described instruction fetching sections.
Instructions ca, cb, cc sent from 1a, 1b, to 1c are sequentially sent to the instruction decoding unit 4, but a plurality of instruction fetching units 1a, 1
When instructions are sent simultaneously from b, to 1c, the instructions are ordered and the instruction decoding unit 4
Send to

The configuration after the instruction decoding unit 4 is basically the same as the configuration of the conventional pipeline system. However, in the parallel processing computer of the present invention, there are conventional means for detecting register interference, There is no need to have a branch prediction means or a recovery means when the branch prediction is not successful.

The instruction decoding unit 4 interprets the instruction, and various arithmetic units 50 provided in the arithmetic unit 5, for example, adders, multipliers, dividers, shifters, branch instruction arithmetic units (for example, branch instruction arithmetic units) Data to be sent by selecting an adder for calculating a destination address, a determiner for determining a branch condition) and the like, but corresponding to the type of data indicated by the instruction, an internal storage device, for example, According to the address of the internal storage device in the instruction, for example, the register number, the data in the internal storage device (register) 3 is read, and the extracted data is sent to the corresponding computing unit 50.

Such means combines, for example, the contents of the bit field of the program identifier added by the instruction fetch units 1a, 1b,... 1c with the internal storage device address field in the instruction, for example, the register number designation field. This can be realized by performing an operation such as performing an operation and setting the address of the internal storage device (register) 3.

The operation unit 5 comprises a plurality of operation units 50 operating in parallel for each instruction. The arithmetic unit 50 that writes to the internal storage device (register) 3 is an instruction decoding unit.
In the same manner as performed in step 4, the address of the internal storage device (register) 3 of the instruction is designated from the program identifier and the address of the internal storage device (register) 3.

If the instruction specifies access to the main storage device, the corresponding arithmetic unit 50 combines the address in the main storage device specified by the instruction with the program identifier. The result obtained by performing an operation such as performing an operation is accessed as an address corresponding to the program in the main storage device.

When the arithmetic unit 50 is a branch instruction arithmetic unit, for example, the address indicating the next branch destination instruction is stored in the program counter PCa, 1a, 1b,. Set to PCb, PCc.

In the above embodiment, the instruction fetch unit 1
The reading of the next instruction in a, 1b, to 1c has been described as an example in which the previously read instruction is read after execution has been completed in the device after the instruction decoding unit 4, but regardless of completion of execution of the instruction, Instructions are always read and the instruction decode unit 4
Then, as in the conventional case, the dependency is checked, and if there is a dependency, transmission to the instruction decoding unit 4 is waited until the dependency is resolved, and an instruction that does not need to be executed, for example, Needless to say, if the instruction is read in advance by branch prediction or the like, the instruction may be invalidated. Even in this case, as described above, since the instruction is not executed merely by reading the next instruction in the instruction fetch units 1a, 1b, to 1c, the instruction affects the state of the parallel processing computer. Therefore, the present invention can be realized with a simpler configuration than conventional hardware such as recovery.

As described above, in the parallel processing computer of the present invention, a plurality of instruction fetching sections for independently fetching instructions from a plurality of programs and adding a program identifier to the instructions of each fetched program, And an instruction merging unit that sends them to the instruction decoding unit in an order, interprets the instruction having the program identifier, and newly stores the internal storage from the internal storage device address and the program identifier in the instruction if necessary. An instruction decoding unit that calculates a device address and reads data from the address, receives the program identifier and the internal storage device address, and newly calculates an internal storage device address from the internal storage device address and the program identifier in the instruction;
It is characterized in that it is configured to write data to the address or to newly calculate a main storage device address from the main storage device address and the program identifier in the above-mentioned instruction, and to have an operation unit for accessing the address. There is.

[0034]

As described above in detail, according to the parallel processing computer of the present invention, there is an instruction that cannot be executed because of an interdependency such as register interference in an instruction sequence of a certain program. Even so, instructions of another program can be executed until the dependency is resolved, so that there is a remarkable effect that the program processing does not stop in the parallel processing computer, which has been conventionally required. Complex hardware such as branch prediction and recovery processing can be dispensed with, and there is an effect that it greatly contributes to preventing performance degradation due to such inter-instruction dependency.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 shows an embodiment of the present invention.

FIG. 3 is a diagram schematically showing a conventional instruction-level parallel processing computer;

[Explanation of symbols]

1a, 1b, 1c Instruction fetch unit 2 Instruction merge unit 3 Internal storage device (register) 4 Instruction decode unit 5 Operation unit 50 Operation unit Program identifier (PIDa, PIDb, PIDc) Internal storage address, main storage address a, b , c Program area PCa, PCb, PCc Program counter

Claims (1)

[Claims] 1. A plurality of instruction fetch units for independently fetching instructions from a plurality of programs stored in one or a plurality of main storage devices, and adding a program identifier to the instructions of each fetched program; An instruction merging unit that receives a plurality of instructions, and sends them to the instruction decoding unit in an order; interprets the instruction having the program identifier, and if necessary, newly generates an instruction from the internal storage device address and the program identifier in the instruction. An instruction decoding unit that calculates an internal storage device address and reads data from the address, receives the program identifier and the internal storage device address,
A new internal storage device address is calculated from the internal storage device address and the program identifier in the instruction, and data is written to that address, or a new main storage device is calculated from the main storage device address and the program identifier in the instruction. A parallel processing computer comprising: an arithmetic unit for calculating an address and accessing the address.