CN116737241B - Instruction fusion method, processor core, processor and computer system - Google Patents
Instruction fusion method, processor core, processor and computer system Download PDFInfo
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- 230000004927 fusion Effects 0.000 claims abstract description 68
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- 230000005540 biological transmission Effects 0.000 claims abstract description 9
- 238000001514 detection method Methods 0.000 claims description 18
- 238000012545 processing Methods 0.000 claims description 5
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- 238000012546 transfer Methods 0.000 description 5
- 230000006399 behavior Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses an instruction fusion method and a processor supporting the same, comprising the following steps: s1, acquiring two adjacent instructions in an execution sequence, namely a first instruction and a second instruction; s2, when the first instruction is detected to be a conditional transmission instruction, the second instruction is an operation instruction, and the first instruction and the second instruction are related to a register, the first instruction and the second instruction are fused, and the conditional operation instruction comprising fusion information is obtained. The invention can reduce the number of instructions to be executed through the instruction fusion of the conditional transmission instruction and the operation instruction, can execute more complex operations, can complete more operations in less time, and can reduce the waiting time generated by the correlation between the instructions, thereby accelerating the execution speed of the processor. And no extra instruction is added, so that the method has better compatibility with the existing processor.
Description
Technical Field
The present invention relates to the field of processor technologies, and in particular, to an instruction fusion method, a processor core, a processor, and a computer system.
Background
The existing general processor architecture is mainly divided into a reduced instruction set computer (Reduced Instruction Set Computing, RISC) and a complex instruction set computer (Complex Instruction Set Computing, CISC), wherein one instruction in the CISC instruction set can complete a plurality of operations, but the design of the processor is complex, redundant or low-efficiency instructions are easy to generate, each instruction in the RISC instruction set only executes a single simple operation, such as addition operation, subtraction operation and the like, but the instruction length is shorter, the format is regular, the decoding difficulty is greatly reduced, meanwhile, the design of a pipeline structure is easy, and the instructions can be quickly executed. The mainstream RISC-V instruction set is now the reduced instruction set, which, although simple, may require more instructions to execute a program, and if the number of instructions can be reduced, the RISC processor may have higher performance.
The instruction fusion method merges two or more adjacent instructions into one instruction, thereby reducing the number of instructions, and one fused instruction is fused in a later pipeline structure. Therefore, the fused instruction can complete more work in less time, the hardware resources are released more quickly, and the performance of the processor is improved.
In the existing instruction fusion method of RISC-V instruction set, mainly the fusion method of conditional branch instruction and the fusion method of operation instruction are fusion of basic instruction, for the newly added Zicond expansion instruction, i.e. conditional transfer instruction, there is no corresponding optimization, and compared with conditional transfer instruction, both are selected by condition judgment, but the conditional transfer instruction does not need to undergo branch prediction, so that the possibility of prediction failure can be reduced. In addition, the conditional instruction has a very large number of applications in programs, which is an alternative logic: AB: C, corresponds to if else condition selection. Therefore, to further improve the execution efficiency of the processor, instruction fusion of conditional instruction is required.
Patent publication number CN115576608 discloses a processor core, processor, chip, control device and instruction fusion method. Wherein the processor core comprises: the instruction fetching unit is used for acquiring two machine instructions adjacent in time sequence; the fusion detection unit is used for judging whether the two machine instructions meet the fusion condition or not; if yes, fusing the first operation instruction and the second operation instruction to obtain a fused instruction; the decoding unit is used for decoding the fusion instruction to obtain a decoding result and an operand corresponding to the fusion instruction; and the execution unit is used for carrying out masking operation on the operands according to the operation instruction of the fusion instruction to obtain an execution result of the fusion instruction.
Patent publication number CN115562725 discloses an instruction fusion method, a processor, a computer system and a storage medium, wherein the instruction fusion method comprises: acquiring a first instruction and a second instruction which are adjacent in execution sequence; when detecting that the data of the first instruction and the data of the second instruction have correlation, fusing the first instruction and the second instruction to obtain a fused comparison jump instruction comprising fusion information, wherein the fused comparison jump instruction is suitable for carrying out instruction jump based on a comparison result, and the fusion information comprises first instruction information of the first instruction and second instruction information of the second instruction.
Both the above two comparison documents disclose an instruction fusion method, but the fusion method has a large number of instruction strips, is easy to occupy hardware resources, reduces the execution speed of a processor, and has no better compatibility with the processor because the write-before-read correlation among instructions is easy to produce a pause, and more complex operation is executed by adding additional instructions.
The above-described technical terms are defined as follows:
1. A processor: the computing and control cores of a computer system.
2. Pipeline structure: refers to decomposing an instruction processing process into a plurality of stages and independently executing each stage to form an instruction pipeline. Each stage performs a different operation such as fetching, decoding, executing, accessing, writing back, etc. Therefore, the processor can process a plurality of instructions simultaneously, and the execution efficiency of the processor is improved.
3. Conditional branch instruction: and judging whether the source operands are equal to perform address jump, namely address selection.
4. Conditional pass instruction: and judging whether the source operand is equal to 0 or not to select data.
5. Operation instruction: instructions for performing arithmetic operations, such as addition, subtraction, etc.
Disclosure of Invention
The invention aims to provide a technical scheme of an instruction fusion method, a processor core, a processor and a computer system aiming at the defects existing in the prior art.
In order to solve the technical problems, the invention adopts the following technical scheme:
The instruction fusion method is characterized by comprising the following steps of:
S1, acquiring two adjacent instructions in an execution sequence, namely a first instruction and a second instruction;
S2, when the first instruction is detected to be a conditional transmission instruction, the second instruction is an operation instruction, and the first instruction and the second instruction are related to a register, the first instruction and the second instruction are fused, and the conditional operation instruction comprising fusion information is obtained.
Further, the first instruction and the second instruction are register related, specifically including:
And fusing the first instruction and the second instruction to obtain the fused conditional operation instruction if the destination register of the first instruction is the same as the destination register of the second instruction and the destination register of the first instruction is the same as the source register of the second instruction.
Further, the fusion information includes instruction valid encoding information of the first instruction and the second instruction.
A processor core, characterized by: the processor core is configured to perform the instruction fusion method as described above, comprising:
1) Instruction fetching unit: the method comprises the steps of fetching a first instruction and a second instruction which are adjacent in execution sequence, and decoding the subsequent instructions and executing the instructions;
2) An instruction decoding unit: the method comprises the steps of decoding a fusion instruction to obtain decoding information of the fusion instruction;
3) An instruction transmitting unit: the system comprises a plurality of execution units, a plurality of execution units and a plurality of control units, wherein the execution units are used for distributing instructions to the corresponding execution units according to the types and the operands of the instructions and transmitting the operands required by the execution units;
4) An instruction execution unit: and the operation for performing operation first and then selection on the conditional operation instruction.
Further, the instruction fetch unit includes:
A pre-decoding unit: for providing information for instruction fusion;
and a fusion detection unit: and the method is used for judging whether the first instruction and the second instruction can be fused into a conditional operation instruction according to the information of the first instruction and the second instruction.
Further, the pre-decode unit provides information for instruction fusion including instruction type and register information that decodes the first instruction and the second instruction.
Further, the processor core further includes an instruction retirement unit: and the method is used for writing the execution result back to the destination register, and carrying out simultaneous retirement processing on the fused conditional instruction and the fused operation instruction.
A processor, characterized by: including at least one processor core as described above.
A computer system, characterized in that: including a processor adapted to perform the method as described above.
Due to the adoption of the technical scheme, the invention has the following beneficial effects:
1. The fusion method of the invention can reduce the number of instruction, thereby reducing the occupation of hardware resources and accelerating the execution speed of the processor.
2. The fusion method of the invention can reduce the pause generated by the write-before-read correlation between instructions.
3. The fusion method of the invention can execute more complex operation without adding extra instructions, and has better compatibility with the processor.
Description of the drawings:
the invention is further described below with reference to the accompanying drawings:
FIG. 1 is a flow chart of a method of instruction fusion, a processor core, a processor and a computer system according to the present invention;
FIG. 2 is a block diagram of a processor core in accordance with the present invention;
FIG. 3 is a flow chart illustrating the execution of a conditional operation fusion instruction according to the present invention;
FIG. 4 is a flow chart of the fusion of instruction sequences in the present invention.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, shall fall within the scope of the invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
The technical terms described in the invention are defined as follows:
1. lifecycle of instructions: refers to the time from the fetching of a instruction to the retirement of the instruction execution.
2. The operands: the operands of an instruction refer to data used for executing operations in the instruction, and are divided into source operands and destination operands, wherein the source operands refer to data to be operated on, and the destination operands refer to result data of the operations. The operands may be in the form of immediate, registers, memory addresses, and the like. The type and number of operands depends on the type and function of the instruction.
3. Source and destination registers: if the operands are all in register form, then the instruction obtains the source operand from the source register and writes the destination operand to the destination register after execution.
4. Register correlation: for sequentially executing instructions a and B, if the source register of instruction B is the destination register of instruction a, then there is a register-dependent case for instructions a and B.
5. Conditional operation instruction: and a fused instruction obtained by fusing the conditional transfer instruction and the operation instruction judges whether the source operand is equal to 0 or not to select the result after operation or not.
As shown in fig. 1, a method for fusing instructions includes the following steps:
S1, acquiring two adjacent instructions in an execution sequence, namely a first instruction and a second instruction;
S2, when the first instruction is detected to be a conditional transmission instruction, the second instruction is an operation instruction, and the first instruction and the second instruction are related to a register, the first instruction and the second instruction are fused to obtain a conditional operation instruction comprising fusion information, and the fusion information comprises instruction effective coding information of the first instruction and the second instruction.
The first instruction and the second instruction are register related, and specifically include: and fusing the first instruction and the second instruction to obtain the fused conditional operation instruction if the destination register of the first instruction is the same as the destination register of the second instruction and the destination register of the first instruction is the same as the source register of the second instruction.
The fusion method of the invention is based on RISC-V instruction set, and the related instructions are as follows:
1. conditional pass instruction: czero.nez, czero.eqz.
2. Operation instruction: add, sub, and, or, xor.
The conditional instruction has a very large number of applications in programs, and is in fact an alternative logic: AB: C, corresponds to if else condition selection. The instruction behavior of a conditional instruction is: whether one source operand is 0 is judged, and the value of the other source operand is written back to the destination register according to the judgment result, or 0 is written back to the destination register.
The instruction behavior of the operation instruction mainly comprises: addition operation, subtraction operation, logical AND operation, logical OR operation, logical XOR operation.
After two instructions are fused, the instruction behaviors of the fused instructions are as follows:
1. judging whether one source operand is 0, writing the result of the addition operation of the other two source operands back to the destination register, or writing one source operand back to the destination register.
2. Judging whether one source operand is 0, writing the result of subtracting operation of the other two source operands back to the destination register, or writing one source operand back to the destination register.
3. And judging whether one source operand is 0, and writing the results of the logical AND operation of the other two source operands back to the destination register, or writing 0 back to the destination register.
4. Judging whether one source operand is 0, writing the result of the logical OR operation of the other two source operands back to the destination register, or writing one source operand back to the destination register.
5. Judging whether one source operand is 0, writing the result of the logical exclusive OR operation of the other two source operands back to the destination register, or writing one source operand back to the destination register.
For example:
czero.nez rd,rs2,rc//rd＝(rc＝＝0)？rs2：0
add rd,rs1,rd//rd＝rs1+rd
Post-fusion rd= (rc= 0)? (r1+r2) rs1
Instruction czero.nez, determine if rc is 0, if 0, write rs2 into rd, if not 0, write 0 into rd. And (3) an add instruction is used for calculating rs1, adding rd and writing the result into the rd. After fusion, judging whether rc is 0, if so, writing rs1+rs2 into rd, and if not, writing rs1 into rd.
Other instruction fusions are shown in table 1:
table 1 instruction fusion sequence a processor core, as shown in fig. 2, comprises:
1) Instruction fetching unit: the method comprises the steps of fetching a first instruction and a second instruction which are adjacent in execution sequence from a memory, and decoding the subsequent instructions and executing the instructions;
The instruction fetch unit includes:
A pre-decoding unit: for providing information for instruction fusion; the pre-decode unit provides information for instruction fusion including instruction type and register information that decodes the first instruction and the second instruction.
Decoding by a pre-decoding unit:
In order to perform fusion detection, some information of the instruction including the instruction type, the register number and the executed operation needs to be known in advance, and the pre-decoding unit can obtain the information through simple decoding according to the operation code of the instruction.
And a fusion detection unit: the method comprises the steps of judging whether the first instruction and the second instruction can be fused into a conditional operation instruction according to information of the first instruction and the second instruction;
the detection content of the fusion detection unit is as follows:
If the instruction types of two adjacent instructions meet the fusion condition, namely, the first instruction is a conditional transmission instruction, and the second instruction is an addition, subtraction, logical AND, logical OR and logical XOR instruction, the comparison of the register numbers is performed. If the destination register of the first instruction and the destination register of the second instruction are the same register, and the destination register of the first instruction and one source register of the second instruction are the same register, and the other source register is not the same register, the two instructions conform to a fusion condition, and the first instruction is identified as a fusion instruction.
In addition, the second instruction cannot be completely lost, and an additional code is generated according to the instruction information obtained by pre-decoding and is added in the instruction information of the fusion instruction, so that preparation is made for decoding by a subsequent decoding unit.
Instruction sequence fusion is shown in fig. 4:
The method is characterized in that the instruction fetching unit is used for fetching four instructions, the four instructions are sent to the fusion detection unit after being pre-decoded, and two adjacent instructions are subjected to fusion detection, namely a first instruction and a second instruction, a second instruction and a third instruction, a third instruction and a fourth instruction, and the four instructions are subjected to fusion detection. Assuming that the fusion detection unit detects that the first instruction is a conditional transmission instruction and the second instruction is an addition instruction, and registers of the two instructions also conform to a fusion condition, the first instruction and the second instruction can be fused into one conditional operation instruction. Assuming that the third instruction and the fourth instruction do not meet the fusion condition, the value takes four instructions taken out by the unit to pass through the fusion detection unit to obtain three instructions, namely a fusion instruction and two common instructions, namely a fused instruction sequence shown in the figure.
The three instructions enter a decoding unit in sequence to be decoded, a common instruction is decoded to obtain a control signal, preparation is made for subsequent pipeline use, a fused instruction is provided with a fused instruction identifier, and the final control signal is obtained by combining all information when the operation code of the instruction is needed to be seen and the additional code in the instruction information is needed to be seen during decoding.
Through pre-decoding and fusion detection of the instruction fetching unit, the number of instructions entering the decoding unit is reduced, and the reduction of the number of instructions can improve the performance of the processor, because the number of times of execution of the processor is reduced, the occupation of resources such as the decoding unit, the execution unit, the register group and the like is reduced, and the execution speed of the processor is accelerated.
2) An instruction decoding unit: the method comprises the steps of decoding a fusion instruction, identifying information such as an instruction type, an operand, a function code and the like, obtaining decoding information of the fusion instruction, and transmitting the decoding information to an instruction transmitting unit;
Decoding by an instruction decoding unit:
In the fusion method, the pre-decoding unit mainly aims at providing necessary instruction information for the fusion detection unit, so that the fusion detection unit can conveniently identify the instruction, and the instruction is locally decoded, and the instruction decoding unit mainly aims at executing the operation of the execution unit and is completely decoded. After the conditional operation fusion instruction carries the additional code and is decoded, the number of source operands of the instruction is increased by one, and the execution function code is changed.
Such as the conditional pass instruction and add instruction exemplified previously:
czero.nez rd, rs2, rc two source operands rc, rs2, one destination operand rdadd rd, rs1, rd two source operands rs1, rd, one destination operand rd
Fused czero.nez-add rd, rs1, rs2, rc three source operands rc, rs1, rs2, a destination operand rd
The function code is changed from the original function code which only performs the selection operation to the function code which performs the addition.
3) An instruction transmitting unit: the system comprises a plurality of execution units, a plurality of execution units and a plurality of control units, wherein the execution units are used for distributing instructions to the corresponding execution units according to the types and the operands of the instructions and transmitting the operands required by the execution units;
correlation of instruction issue units:
In an instruction issue unit, an instruction waits for an operand to be ready, i.e. a register to be read for the latest data, and if the operand of the instruction comes from the result of a previous instruction, the instruction can be executed after the result of the previous instruction is obtained, and a read-before-write dependency (READ AFTER WRITE, RAW) exists between the two instructions, which type of dependency affects the efficiency of parallel execution of the processors.
The two instructions in the fusion method have the RAW correlation, because the source operand of the second instruction is the destination operand of the first instruction, the second instruction can enter the execution unit for execution after the execution of the first instruction is completed, but the waiting time is saved after the fusion, and the writing of a register is saved because the destination registers of the two instructions are the same, the occupation of a writing port of a register group is reduced, the subsequent instruction with the correlation can be enabled to take the operand earlier, and the execution efficiency is improved.
The fused conditional instruction has one more source operands than the unconnected conditional instruction, but reduces the stall caused by the correlation, and improves the performance as a whole.
4) An instruction execution unit: operations for performing operations first and then selecting conditional operation instructions, such as addition, subtraction, logical OR, logical XOR, and the like;
the conditional transfer instruction only executes the operation of one of two alternatives in the execution unit, the operation instruction only executes the single operation in the execution unit, and the fused conditional operation instruction is to execute one of two alternatives on the result after operation, which is equivalent to executing the more complex operation selection operation, so that the execution speed can be increased.
5) An instruction retirement unit: the method is used for writing the execution result back to the target register, and carrying out simultaneous retirement processing on the fused conditional transmission instruction and the operation instruction, mainly removing the executed instruction from the pipeline structure and updating the related register so as to ensure the correctness of the instruction and the correctness of the execution sequence.
The conditional operation instruction is written back to the destination register after being executed, and the fused conditional transmission instruction and the operation instruction are retired at the same time, namely, when the fused instruction becomes the oldest instruction in the pipeline, the register is updated and disappears from the pipeline.
The execution of the fused instruction during its lifecycle is shown in fig. 3:
The value unit is used for fetching a plurality of sequential instructions, pre-decoding is performed according to the operation code of the instructions, the instruction type and the register number can be known through pre-decoding, and the instructions are sent to the fusion detection unit. The fusion detection unit checks the instruction type and the register number of two adjacent instructions, if the fusion condition is met, the first instruction is identified as a fusion instruction, the instruction information of the second instruction is generated into an additional code, and the code enters the instruction decoding unit along with the instructions. The instructions from the instruction value unit to the instruction decoding unit are fused instructions, the number of instruction strips is reduced at the moment, and final control signals and register information are obtained according to additional codes generated by the fusion detection unit during the decoding of the fused instructions, wherein the control signals are mainly signals for distinguishing the instructions from the operation types by the transmitting unit and the executing unit. After decoding, the instruction enters an instruction transmitting unit, and when the operand is ready, the instruction can enter an executing unit to execute. And the fusion instruction in the execution unit needs to be subjected to additional processing to meet the function of the fusion instruction, and finally an operation result is obtained. And the fused instruction after completion of execution can write the operation result back to the register, and the fused two instructions are retired simultaneously.
Instruction fusion of conditional pass instructions and arithmetic instructions can reduce the number of instructions to be executed, can perform more complex operations, can complete more operations in less time, and can reduce latency due to dependencies between instructions, thereby increasing the processor execution speed. And no extra instruction is added, so that the method has better compatibility with the existing processor.
A processor comprising at least one processor core as described above.
A computer system comprising a processor adapted to perform the above.
The above is only a specific embodiment of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent substitutions or modifications made on the basis of the present invention to achieve substantially the same technical effects are included in the scope of the present invention.
Claims (7)
1. The instruction fusion method is characterized by comprising the following steps of:
S1, acquiring two adjacent instructions in an execution sequence, namely a first instruction and a second instruction;
S2, when the first instruction is detected to be a conditional transmission instruction, the second instruction is an operation instruction, and the first instruction and the second instruction are related to a register, fusing the first instruction and the second instruction to obtain a conditional operation instruction comprising fusion information; the first instruction and the second instruction are register related, and specifically include: and fusing the first instruction and the second instruction to obtain a fused conditional operation instruction if the destination register of the first instruction is the same as the destination register of the second instruction and the destination register of the first instruction is the same as the source register of the second instruction.
2. A method of instruction fusion according to claim 1, wherein: the fusion information comprises instruction effective coding information of the first instruction and the second instruction.
3. A processor core, characterized by: the processor core is configured to perform the instruction fusion method of claim 1 or 2, comprising:
1) Instruction fetching unit: the method comprises the steps of fetching a first instruction and a second instruction which are adjacent in execution sequence, and decoding the subsequent instructions and executing the instructions; the instruction fetch unit includes: a pre-decoding unit: for providing information for instruction fusion; and a fusion detection unit: the method comprises the steps of judging whether the first instruction and the second instruction can be fused into a conditional operation instruction according to information of the first instruction and the second instruction;
2) An instruction decoding unit: the method comprises the steps of decoding a fusion instruction to obtain decoding information of the fusion instruction;
3) An instruction transmitting unit: the system comprises a plurality of execution units, a plurality of execution units and a plurality of control units, wherein the execution units are used for distributing instructions to the corresponding execution units according to the types and the operands of the instructions and transmitting the operands required by the execution units;
4) An instruction execution unit: and the operation for performing operation first and then selection on the conditional operation instruction.
4. A processor core according to claim 3, characterized in that: the pre-decode unit provides information for instruction fusion including instruction type and register information that decodes the first instruction and the second instruction.
5. A processor core according to claim 3, characterized in that: the processor core further includes an instruction retirement unit: and the method is used for writing the execution result back to the destination register, and carrying out simultaneous retirement processing on the fused conditional instruction and the fused operation instruction.
6. A processor, characterized by: comprising at least one processor core as claimed in claim 3.
7. A computer system, characterized in that: comprising a processor adapted to perform the method of claim 6.
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