JP2004214880A - Memory mapping method and buffer memory circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory mapping method and a buffer memory circuit for facilitating management of ATM cells in units of cells and enhancing the utilizing efficiency of a memory without forming areas of the memory not in use when the memory temporarily stores the ATM cells or the like. <P>SOLUTION: In order to store data in bytes not being the n-th power of 2 such as an ATM cell in 53 bytes, a plurality of memory sections 11 to 14 separated in units of the byte length of the n-th power of 2 are prepared to map the ATM cell, and ATM cell data are written in / read from a plurality of the memory sections 11 to 14. The first memory section 111 and the second memory section 112 store the header of the ATM cell data and the third memory section 113 and the fourth memory section 114 store the information (payload). <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory mapping method and a buffer memory circuit, and more particularly to a memory mapping method and a buffer memory circuit suitable for storing data of a byte length other than 2 n, such as an ATM (Asynchronous Transfer Mode) cell.
[0002]
[Prior art]
When transferring information from a device having a high processing speed to a device having a low processing speed, a buffer memory is disposed between devices so as to reduce a transfer waiting time and prevent data overflow. This is a memory for temporarily storing data. In many cases, the buffer memory is constituted by a semiconductor integrated circuit (IC or LSI) such as a DRAM (Dynamic Random Access Memory). Such DRAMs are standardized and are available at relatively low cost from multiple manufacturers.
[0003]
In an ATM-related apparatus, a certain amount of ATM cells is generally stored in a buffer memory such as a FIFO (first-in first-out) memory for the purpose of converting the cell speed or absorbing CDV (Cell Delay Variation). The ATM cell has a 53-byte format which usually includes a 5-byte header and a 48-byte payload (information section). Some conventional memory configuration methods for mapping such ATM data to a buffer memory have been proposed (for example, see Patent Document 1).
[0004]
FIG. 7 shows a conventional first memory mapping method. In the first memory mapping method, a memory is divided into 64 (that is, the minimum value of 2 to the n-th power larger than 53) bytes, and 53-byte cells are stored. Therefore, processing in units of cells is easy. That is, by using only the upper digits of the memory address, the amount of accumulated data can be easily confirmed, and processing and management in units of cells can be easily performed. FIG. 8 shows a second conventional memory mapping method. In the second memory mapping method, mapping is performed in units of 53 bytes (that is, without creating a space). In this memory mapping method, since the head position of the ATM cell is not fixed with respect to the address of the memory, a large-scale arithmetic circuit is required to monitor the amount of data accumulated in the memory.
[0005]
[Patent Document 1]
JP-A-2000-278278 (pages 3-4, FIGS. 1, 3)
[0006]
[Problems to be solved by the invention]
The conventional technique described above has several problems. That is, in the memory mapping method of FIG. 7, there is an unused area (hatched portion in FIG. 7) of 11 bytes (64-53 =) per storage area of one cell, and the memory use efficiency is poor. On the other hand, if priority is given to memory use efficiency, mapping is performed in units of 53 bytes as shown in FIG. In this case, the head address value of each cell unit is 53 × n−1 (that is, 0, 52, 105, 158, 211, 264,... In decimal), and it is difficult to manage the cell unit.
[0007]
In order to manage the cell unit by the mapping method shown in FIG. 8, a decoder for calculating the number of cells from the address counter value supplied to the memory is added, or a counter for counting the number of cells is added separately from the address counter. Action is required. When a decoder is added, there is a concern that the circuit scale of the decoder becomes large and the operation speed of the circuit is limited, especially when there are many cells to be stored. On the other hand, when a cell counter is added separately from the address counter, if the consistency between the values of the memory address counter and the cell counter is lost for some reason, it is necessary to create a mechanism for determining and restoring this. However, the circuit becomes complicated. Summarizing the above, in the conventional example of FIG. 7, although the management in units of cells is easy, the use efficiency of the memory is low. In the conventional example shown in FIG. 8, although the use efficiency of the memory is good, when the management is performed in units of cells, the circuit scale is increased by adding a decoder and the operation speed is limited, or the circuit is complicated by adding a cell counter.
[0008]
[Object of the invention]
The present invention has been made in view of the above-mentioned problems of the prior art, and has a memory mapping method that satisfies both advantages of the example of FIG. 7 or 8, that is, both ease of management in cell units and memory use efficiency. A buffer memory circuit is provided.
[0009]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the memory mapping method and the buffer memory circuit of the present invention employ the following characteristic configurations.
[0010]
(1) In a memory mapping method of a buffer memory for temporarily writing data sequentially input with a byte length other than 2 to the power of n and then reading the data,
A memory mapping method for dividing the byte length other than 2 to the power of n into a plurality of units of 2 to the power of n, and mapping the data to a plurality of memory units independently prepared for each of the divided units.
[0011]
(2) The memory mapping method according to (1), wherein the input data is ATM cell data having a length of 53 bytes.
[0012]
(3) The memory mapping according to (2), wherein the plurality of memory units are a 4-byte first memory unit, a 1-byte second memory unit, a 16-byte third memory unit, and a 32-byte fourth memory unit. Method.
[0013]
(4) The memory mapping method according to (2), wherein the plurality of memory units are a 4-byte first memory unit, a 1-byte second memory unit, and an 8-byte third to eighth memory unit.
[0014]
(5) The memory mapping method according to (2), wherein the plurality of memory units are a 4-byte first memory unit, a 1-byte second memory unit, and a 16-byte third to fifth memory unit.
[0015]
(6) The header of the ATM cell data is stored in the first memory unit and the second memory unit, and the information (payload) of the ATM cell data is stored in a memory unit subsequent to the third memory unit. , (4) or (5).
[0016]
(7) In a buffer memory circuit for sequentially writing sequentially input data having a byte length other than 2 to the power of n and then reading out the data,
The buffer memory is divided into a plurality of memory units each having a length of 2 n bytes, and as an address counter for controlling writing and reading of the plurality of memory units, a byte counter, a section counter, and a cascade-connected byte counter, respectively. A buffer memory circuit including a cell counter.
[0017]
(8) The buffer memory circuit according to (7), wherein the input data is 53-byte ATM cell data having a 5-byte header and 48-byte information (payload).
[0018]
(9) The plurality of memory units include a 4-byte first memory unit and a 1-byte second memory unit for storing a header of the ATM cell data, and an 8-byte for storing information (payload) of the ATM cell data. , The buffer memory circuit according to the above (8), comprising a third or a plurality of memory units of 16 bytes or 32 bytes.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the configuration and operation of a preferred embodiment of a memory mapping method and a buffer memory circuit according to the present invention will be described in detail with reference to the accompanying drawings.
[0020]
FIG. 1 is a format diagram of an ATM cell in a preferred embodiment of the present invention.
The ATM cell 10 is composed of, for example, 53 bytes. As shown in FIG. 1A, the ATM cell 10 has a 4-byte first memory unit (mem0) 11 and a 1-byte second memory unit (mem1) 12. , A 16-byte third memory unit (mem2) 13 and a 32-byte fourth memory unit (mem3) 14. The 5-byte header of the ATM cell is stored in the first memory unit 111 and the second memory unit 112, and the 48-byte information (payload) is stored in the third memory unit 113 and the fourth memory unit 114. ing.
[0021]
FIG. 1B shows a detailed configuration of the first memory unit 11. FIG. 1C shows a detailed configuration of the second memory unit 12. FIG. 1D shows a detailed configuration of the third memory unit 13. FIG. 1E shows a detailed configuration of the fourth memory unit 14. As shown in FIGS. 1B to 1E, the first to fourth memory units 111 to 114 include a plurality of memories of 4 bytes, 1 byte, 16 bytes and 32 bytes, respectively. Then, the sequentially input ATM cells are stored at sequential addresses of these memories.
[0022]
For example, in the first ATM cell, the first 4 bytes are addresses 0x0000 to 0x0003 of the first memory unit 111, the next 1 byte is an address 0x0000 of the second memory unit 112, and the next 16 bytes are an address of the third memory unit 113. 0x0000 to 0x000F and the last 32 bytes are stored at addresses 0x0000 to 0x001F of the fourth memory unit 114. The first 4 bytes of the second ATM cell are the addresses 0x0004 to 0x0007 of the first memory unit 111, the next 1 byte is the address 0x0001 of the second memory unit 112, and the next 16 bytes are the addresses 0x0010 to 0x0010 of the third memory unit 113. 0x001F and the last 32 bytes are stored in the fourth memory unit 114 at addresses 0x0020 to 0x003F. The third and lower ATM cells are sequentially stored at the next addresses of the first to fourth memory units 111 to 114 in the same manner as described above.
[0023]
As described above, in the present invention, data of a specific number of bytes other than 2 n is divided and stored in a plurality of 2 n memory units such as 1, 2, 4, 8, 16,. .
[0024]
Next, FIG. 2 is a configuration diagram of an address generation unit 20 that stores (or writes) the ATM cells input to the first to fourth memory units 11 to 14 of the ATM cell 10 according to the present invention shown in FIG. is there. The address generator 20 includes a byte (Byte) counter 21, a section (Section) counter 22, a cell (Cell) counter 23, and a decoder (DEC) 24.
[0025]
For convenience of explanation, only input data "D" of ATM cell, address "A [xxxx ... 0]", and chip select "CS" are shown as input signals of the buffer memory. The three counters of the address generation unit 20, that is, the byte counter 21, the section counter 22, and the cell counter 23 are connected in cascade. In this specific example, a 53-byte ATM cell is divided (divided) and stored in four memory units 111 to 114. A counter that distinguishes the four will be referred to as a section counter.
[0026]
Next, FIG. 3 shows a timing chart for explaining the write operation of the ATM cell shown in FIGS. In FIG. 3, (a) shows the ATM cell input data, (b) shows the output signal of the byte counter 21, (c) shows the output signal of the section counter 22, and (d) shows the output signal of the cell counter 23.
[0027]
In FIG. 3, first, all counter values are “0”. In writing the first four bytes of the ATM cell, the output signal BC [4-0] of the byte counter 21 is incremented from "0" to "3". In the next 1-byte write, the output signal BC [4-0] of the byte counter 21 returns to “0”, and the output signal SC [1-0] of the section counter 22 increments to “1”. Thereafter, while the output signal BC [4-0] of the byte counter 21 returns to “0” for each section, the output signal SC [1-0] of the section counter 22 is incremented. Then, when 53 bytes have been written, the output signal CC [xxxxxx] of the cell counter 23 is incremented at the beginning of the next ATM cell. It should be noted that since the byte counter 21 and the section counter 22 both count the number of 2 n units, the circuit configuration is easy.
[0028]
Regarding the byte counter 21, since the storage amount per cell differs for each memory, the operation of this specific example is satisfied by wiring the address (BC [4-0] in FIG. 2) as follows. . In other words, the lower two BCs [1-0] of the byte counter 21 are connected to the first memory unit (mem0) 111, and no connection is made to the second memory unit (mem1) 112. BC [3-0] is connected to the third memory unit (mem2) 113, and BC [4-0] is connected to the fourth memory unit (mem3) 114. The output signal of the section counter 22 is connected to the CS (chip select) of the four memory units 111 to 114 via the two-to-four decoder 24, and selects the storage destination memory unit. Since the decoder 24 may be a relatively shallow decoder of 2: 4, the circuit scale is small, and there is little possibility that the operation speed is limited.
[0029]
Next, FIG. 4 shows the configuration on the reading side of the memory units 11 to 14 constituting the ATM cell. The reading side has basically the same configuration as the writing side and operates similarly. That is, it is constituted by three counters of a cascade-connected byte counter 31, section counter 32, and cell counter 33 and a selector (SEL).
Then, the output signal of the section counter 32 is input to the selector 34. The selector 34 selects the first memory unit 111 when the value of the section counter 32 is “0”. On the other hand, in the case of “1” to “3”, the second memory unit 112 to the fourth memory unit 114 are selected, respectively.
[0030]
FIG. 5 is a timing chart of the read operation of the ATM cell shown in FIG.
5, (a) shows the output signal of the byte counter 31, (b) shows the output signal of the section counter 32, (c) shows the output signal of the cell counter 33, and (d) to (g) show the first memories 111 to 11. The read state of the fourth memory 114 and (h) show the ATM cell output data output from the selector 34.
[0031]
First, the value of each of the counters 31 to 33 is “0”. The byte counter 31 counts up from “0” to “3”. During this time, data is simultaneously read from the first memory unit 111 to the fourth memory unit 114, but significant data is output data of the first memory unit 111. During this time, the section counter 32 indicates “0”, and the selector 34 selects data in the first memory unit 111. In the next section, the section counter 32 becomes "1" while the byte counter 31 returns to "0". In this section, significant data is data in the second memory unit 112 and the section counter 32 is “1”, so the selector 34 selects data in the second memory unit 112. Thereafter, by repeating the operation in the same manner, the ATM cell is read, and the 53-byte ATM cell is reproduced (see FIG. 5H).
[0032]
The preferred embodiments of the memory mapping method and the buffer memory circuit according to the present invention have been described above in detail. However, such an embodiment is merely an exemplification of the present invention, and the present invention is not limited to such an embodiment. It will be readily apparent to those skilled in the art that various modifications can be made according to a specific application or as appropriate without departing from the spirit of the present invention. In the ATM cell 10 of the preferred embodiment described above, the memory is divided into four (or divided). However, as shown in FIG. 6A, the memory may be divided into four bytes, one byte, and eight bytes × 6. In this case, eight independent memories are prepared, and the byte counter, the section counter, and the cell counter are configured to operate as shown in the timing charts of FIGS. 6B to 6D. The detailed configuration of each counter can be any of a number depending on the cell division order and size, and a description thereof will be omitted.
[0033]
Further, the memory unit for storing the information (payload) of the ATM cell data may be constituted by three memory units having a length of 16 bytes, for example. Also, it is clear that the length of the ATM cell is not limited to 53 bytes and can be applied to a buffer memory circuit for data of any cell length (not 2 n).
[0034]
【The invention's effect】
As understood from the above description, the memory mapping method and the buffer memory circuit according to the present invention have the following practically significant effects. By storing (or mapping) data of a plurality of bytes other than 2 to the power of n in a memory unit divided (divided) into a plurality of length units of 2 to the power of n, the memory can be used without any free space. It is possible to make the most of efficiency. In addition, there is an effect that management and control in a cell unit can be easily performed. Further, the circuit scale of the write and read circuits is relatively small, and there is no limitation on the operation speed of the circuit. The present invention is particularly effective when peripheral circuits including an ATM buffer memory are integrated in devices such as LSIs and FPGAs.
[Brief description of the drawings]
FIG. 1 is a format diagram of an ATM cell according to a preferred embodiment of the present invention.
FIG. 2 is a configuration diagram of a write circuit according to the embodiment of the present invention.
FIG. 3 is a timing chart for explaining a write operation in the embodiment shown in FIG. 2;
FIG. 4 is a diagram illustrating a configuration of a read circuit according to the embodiment of the present invention.
FIG. 5 is a timing chart illustrating a read operation in the embodiment shown in FIG.
FIG. 6 is a diagram illustrating the configuration and operation of another embodiment of the present invention.
FIG. 7 is a first conventional example of memory mapping.
FIG. 8 is a second conventional example of memory mapping.
[Explanation of symbols]
10 ATM cells 11, 111 First memory unit 12, 112 Second memory unit 13, 113 Third memory unit 14, 114 Fourth memory unit 20 Write address generation unit 21, 31 Byte counter 22, 32 Section counter 23, 33 cells Counter 24 decoder 34 selector

Claims (9)

In a memory mapping method of a buffer memory, data to be sequentially input with a byte length other than 2 n is temporarily written and then read.
A memory for dividing the byte length other than 2 to the power of n into a plurality of units of 2 to the power of n, and mapping the data to a plurality of memory units independently prepared for each of the divided units; Mapping method. 2. The memory mapping method according to claim 1, wherein the input data is ATM cell data having a length of 53 bytes. 3. The memory device according to claim 2, wherein the plurality of memory units are a 4-byte first memory unit, a 1-byte second memory unit, a 16-byte third memory unit, and a 32-byte fourth memory unit. Memory mapping method. The memory according to claim 2, wherein the plurality of memory units are a 4-byte first memory unit, a 1-byte second memory unit, and an 8-byte third to eighth memory unit. Mapping method. The memory according to claim 2, wherein the plurality of memory units are a 4-byte first memory unit, a 1-byte second memory unit, and a 16-byte third to fifth memory unit. Mapping method. The method according to claim 1, wherein a header of the ATM cell data is stored in the first memory unit and the second memory unit, and information (payload) of the ATM cell data is stored in a memory unit after the third memory unit. 6. The memory mapping method according to 3, 4, or 5. In a buffer memory circuit, which sequentially writes data having a byte length other than 2 to the power of n and sequentially reads out the data,
The buffer memory is divided into a plurality of memory units each having a length of 2 n bytes, and as an address counter for controlling writing and reading of the plurality of memory units, a byte counter, a section counter, and a cascade-connected byte counter, respectively. A buffer memory circuit comprising a cell counter. 8. The buffer memory circuit according to claim 7, wherein said input data is a 53-byte ATM cell data having a 5-byte header and 48-byte information (payload). The plurality of memory units include a 4-byte first memory unit and a 1-byte second memory unit for storing a header of the ATM cell data, and 8-byte and 16-byte stores information (payload) of the ATM cell data. 9. The buffer memory circuit according to claim 8, wherein said buffer memory circuit is constituted by a plurality of memory units of 32 bytes or more.

Images