JP2000040354A - Storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage device which operates as a FIFO at high speed and with a low power consumption without depending on the capacity of the device. SOLUTION: This device is constituted of a storage element group 3 consisting of storage elements of two or more, a write shift register 1 and a read shift register 5 which respectively have the same number of stages as that of the element group, a decoder circuit which selects an storage element by outputs of respective shift registers and performs the writing and the reading of data and a flag circuit 6 which generates an empty flag and a full flag by outputs of the respective shift registers and the device operates as the FIFO.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a storage device realized by a semiconductor integrated circuit or the like.

[0002]

2. Description of the Related Art FIFO is an abbreviation of first-in first-out, and means a storage device having a mechanism for extracting data stored in a storage device from data stored earlier. It has a function of setting an empty flag when there is no data and a function of setting a full flag when stored data fills the storage area. A conventional FIFO is composed of a storage device, a write counter, and a read counter, generates an address of the storage device based on the value of the counter, selects a storage element by an address decoder of the storage device, and writes / reads data. And a circuit that generates an empty flag and a full flag by calculating the value of the counter.

[0003]

However, the conventional FIF
In O, when the capacity of the storage device is increased, the circuit scale of the counter and the address decoder of the storage device is increased, and accordingly, the circuit for generating the empty flag and the full flag for calculating the value of the counter is also increased. There was a problem that it could not operate.

The present invention solves such a problem, and an object of the present invention is to provide a large-capacity, high-speed FIFO that does not depend on the capacity of a storage device.

[0005]

According to the present invention, there is provided a storage element group including two or more storage elements, a write shift register including the same number of shift registers as the number of storage elements in the storage element group, and A write decoder circuit for writing data to one storage element of the storage element group selected by the output of the write shift register, and a read shift comprising the same number of shift registers as the number of storage elements in the storage element group A register, a read decoder circuit for reading data of one storage element of the storage element group selected by an output of the read shift register, and an empty flag and a full flag generated by outputs of the write decoder circuit and the read decoder circuit. And a flag circuit that operates as a FIFO.

[0006]

According to the above-described circuit configuration of the present invention, data is written to the storage element selected by the output of the write shift register during a write operation, the write shift register is shifted rightward, and a read operation is performed during a read operation. Reads data from the storage element selected by the output of the shift register,
Data is written and read by shifting the shift register to the right. Compared to a conventional FIFO operating a counter and selecting a storage element by an address decoder to write / read data, the FIFO can be operated only by right shift operations of the write shift register and the read shift register, so that high speed operation is achieved. It is possible to operate.
Also, in contrast to a conventional FIFO that generates an empty flag and a full flag by calculating the value of a counter, the empty state and the full state are determined based on the logical product of the outputs of the write decoder circuit and the read decoder circuit. As a result, it is possible to operate at high speed. Further, since the FIFO of the present invention does not depend on the capacity and the peripheral circuit attached to one storage element is the same, when implementing FIFOs with various capacities, the FIFO can be realized by arranging the same layout, and the library can be implemented. Easy.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a circuit diagram showing an embodiment of the first embodiment of the present invention. 1 is a write shift register, 2 is a write decoder circuit, 3 is a storage element group, 4 is a read shift register, 5 is a read decoder circuit, and 6 is a flag circuit. Are connected as shown in FIG.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIGS.

FIG. 2 is a diagram for explaining the operation until an empty flag is generated.

The storage element group 3 is composed of six storage elements, and the write shift register 1 and the read shift register 4 are each composed of a six-stage shift register. FIG.
As shown in FIG.
The bit is set to high level, the second to sixth bits are set to low level, the first bit of the read shift register 4 is set to high level, and the second to sixth bits are set to low level.
In the write operation, data A is written from the write decoder circuit 2 to the storage element 1 connected to the high-level bit of the write shift register 1 at the rise of the write clock signal WCK, and is written at the fall of the write clock signal WCK. -The shift register 1 is shifted right. Similarly, data B and data C are sequentially written to the storage element 2 and the storage element 3, respectively (FIGS. 2B, 2C, and 2C).
(D)). During the read operation, as shown in FIG. 2E, data A is read from the storage element 1 connected to the high-level bit of the read shift register 4 from the read decoder circuit 5 at the rise of the read clock signal RCK. And the read shift register 4 is shifted right. Similarly, data B is read from the storage element 2 and data C is read from the storage element 3 (FIG. 2F,
(G) and (h)). Here, as shown in FIG.
At the end of the shift operation after reading, if the write shift register 1 and the read shift register 4 have selected the same storage element, all the stored data has been read, indicating the empty state. I have. This state can be determined by the logical product of the outputs of the same bits of the write shift register 1 and the read shift register 4. If one of them is at the high level at the end of the shift operation after reading, the empty flag is generated by the flag circuit 6. Let it.

FIG. 3 is a diagram for explaining the operation until the full flag is generated.

A description will be given from the continuation of the empty state in FIG. Here, when the write operation is performed, the data D is written to the storage element 4 and the empty flag is released.
(See FIG. 3 (a)). When write operations are sequentially performed, data E is written to the storage element 5 and data F is written to the storage element 6 (see FIGS. 3B and 3C). The write shift register 1 and the read shift register 4 are connected to the last bit to one bit. When a write operation is further performed, data G is stored in the storage element 1, data H is stored in the storage element 2, and data H is stored in the storage element 3. Data I is written (FIG. 3D,
(E), (f), (g)). Here, as shown in FIG. 3G, when the write shift register 1 and the read shift register 4 select the same storage element at the end of the shift operation after writing, the data cannot be stored any more. Yes, indicating a full state. This state can be determined by the logical product of the outputs of the same bits of the write shift register 1 and the read shift register 4, and when one of them is at the high level at the end of the shift operation after writing, the flag circuit 6 generates a full flag. .

As described above, the circuit shown in FIG. 1 is a storage device having a mechanism for retrieving previously stored data, has a function of generating an empty flag and a full flag, and operates as a FIFO. You can see that.

The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention. In particular, for the flag circuit 6, in addition to the above-described method, as shown in FIGS. 2 (g) and 3 (f), in a state before performing the shift operation after the write operation or the read operation, the write shift register A method is also possible in which the determination is made based on the logical product of the output of one bit and the output of the bit of the read shift register 4 immediately before or after it.

[0016]

As described above, according to the present invention, F
The memory element is selected and written / read only by the shift operation of the write shift register and the read shift register without depending on the capacity of the IFO. Only one bit of the write shift register and the read shift register operates and has excellent effects such as low power consumption. Further, since the circuit configuration of the present invention has the same configuration of the peripheral circuit attached to one storage element, it can be realized by arranging the same layout when configuring FIFOs of various capacities, and the library can be easily formed. Has the effect that

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a circuit operation of the present invention.

FIG. 3 is a diagram for explaining a circuit operation of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Write shift register 2 Write decoder circuit 3 Storage element group 4 Read shift register 5 Read decoder circuit 6 Flag circuit

Claims (1)

[Claims] 1. A storage element group including two or more storage elements, a write shift register including a shift register having the same number of storage elements as the number of storage elements in the storage element group,
A write decoder circuit that writes data to one storage element of the storage element group selected by the output of the write shift register; and a read / write circuit that has the same number of shift registers as the number of storage elements in the storage element group. A shift register, a read decoder circuit for reading data of one storage element of the storage element group selected by an output of the read / shift register, and an empty flag and a full flag based on outputs of the write decoder circuit and the read decoder circuit. And a flag circuit for generating
A storage device that operates as a storage device.