JP3511342B2 - Data storage circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO
Data storage circuits, especially in ATM communication systems
Construct buffer for temporary storage of used ATM cells
The present invention relates to a data storage circuit. [0002] 2. Description of the Related Art As means for realizing multimedia communication,
ATM (Asynchronous Transfer Mode)
Mode) is considered to be prominent, and in particular, LAN (Local Area)
 Network). In the ATM communication system, information data
Columns are divided into fixed-length data blocks called cells
Sending and receiving data. ATM communication method
Can multiplex cell data input from various routes.
And is characterized by the efficient use of lines.
ing. Effective without losing or discarding cell data
Temporarily store cell data to perform efficient multiplexing.
As a buffer for outputting in the stacking order, FIFO (fi
rst-in first-out). Generally, in a FIFO, a data latch section is used.
Data is temporarily stored using a memory, etc.
In the communication system, data writing and reading are frequent
The flip-flop that can operate at high speed
Using a D-latch or the like, or using a data storage circuit shown in FIG.
Used. FIG. 4 shows a conventional data storage having a FIFO function.
FIG. 3 is a diagram illustrating a configuration of an integrated circuit. In FIG. 4, a data storage circuit includes a plurality of data storage circuits.
.., N, a write request and a read request
, N are selected according to the request.
It comprises a memory selector 3. [0007] As shown in FIG.
Access to memory is decentralized instead of concentrating on one memory
The use of multiple memories so that
Noh is realized. [0008] However, this is not the case.
In such a conventional buffer circuit, the ATM communication method is used.
The cell data used is usually 8 bits × 53 bytes.
Since it is composed of data amount, flip-flops and D
-If a data latch is configured using latch elements,
In this case, 424 elements are required to store one cell data.
Required. Therefore, one L including the FIFO
A place to realize multiple functions in an integrated circuit such as SI
Very large circuit only with data latch part of FIFO
Scale, and the area occupied in the LSI chip increases.
There are drawbacks. In particular, multiple cell data in the FIFO
Data can be stored in the same LSI
This puts pressure on the realization of other circuit functions. Further, as shown in FIG.
The data latch unit is configured using the number of memories corresponding to the number of files
In this case, as described above, normal cell data
Memory × 53 bytes, general memory
2 which is a structural unit of^NDoes not match
An unused area will be generated. Further, the F realized by using the distributed memory system
When the IFO is realized on an integrated circuit such as an LSI,
Usually, memory of the same capacity only has a certain shape
Therefore, a plurality of memories are arranged and used on an LSI chip.
In some cases, depending on the layout,
Use that cannot be used for other circuits because it is surrounded by moly
The possibility of creating impossible regions is greatly increased. That is, in the prior art, data such as FIFO is used.
When the data storage function is realized, the circuit becomes large-scale.
Inefficient circuits, such as having circuit areas that are not used at all
Is likely to be realized, and a single LSI
It is very likely that the degree of integration will decrease
I will. In addition to the above problems, the chip area of the LSI
In terms of efficient use of
Used as a circuit realizable area to realize the functions of
Not possible, may cause unusable areas, etc.
There was a problem to be solved. The present invention eliminates the unused area of the memory.
Eliminate inefficient circuits and realize efficient circuits
Data that can avoid large-scale circuits
An object is to provide a storage circuit. [0015] [Means for Solving the Problems]In ATM communication system
The data of the present invention for temporarily storing used cell data, etc.
The data storage circuit has a memory for storing cell data and a
Count the number of written bytes of cell data being written
And write to memory in cell data units
Receive a request signal and write data according to the byte length of the cell data.
Write signal generation and write address writing to memory
Write-side address control unit for control and storage in memory
Storage counter for managing the number of cell data stored
And read address operation to calculate read address
Unit provided to the memory from the write address control unit.
Stored in the memory based on the address value
While managing the data amount,
And a comparison unit that performs generation.
Of the cell data output from the
Is added by an UP signal indicating that the operation has been performed.
In addition, the cell data was read by the comparator
Therefore, it is subtracted, and the address operation unit
Provided by the count value and the write-side address control unit
The read address is calculated using the initial value of the write address.
It is configured to be calculated. [0016] [0017] [0018] [0019] DESCRIPTION OF THE PREFERRED EMBODIMENTS A data storage circuit according to the present invention
Temporary storage of ATM cells used in ATM communication system
To be applied to the data storage circuit that constitutes the product buffer
Can be. FIG. 1 is a data diagram according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating an overall configuration of a data storage circuit. In FIG. 1, a data storage circuit 10
Receive a write request signal to the memory
Write to generate write signal and control write address
Only the address control unit 11 and the write address sequentially
After writing to the highest address of the update memory,
A cyclic flag indicating that writing to the lowest address has been transferred.
Receiving a cell data read request signal from the
To generate a read signal to the memory and read it to the memory.
Read-side address control unit that controls the read address
13, the write address control unit 11 and the read address
Address given to the memory from each of the
Memory values and compare the amount of data stored in memory.
Comparing unit 14 (management means) that performs processing and storage of cell data
And a data storage unit 15 composed of one memory for performing
Has been established. The above write-side address control unit 11
Flag control unit 12 and read-side address control unit 13
Constitute the address control means 16 as a whole. Hereinafter, the data storage configured as described above will be described.
The operation of the circuit 10 will be described. First, in the comparing section 14, the write-side address
The write address given to the memory from the
Address to the memory from the read-side address control unit 13.
Compares with the given read address value, and
If the comparison results are equal, write the EVEN signal
Output to both address control units
I do. Also, as a result of the comparison, the two address values are not equal.
In this case, the output of the EVEN signal is stopped. The traveling flag control section 12 outputs a traveling flag signal
Setting and release operations. Setting the cyclic flag signal
The condition is that the data storage unit 1 configured by one memory
5 during a write operation to the highest address of the memory.
A write operation is performed, and writing to the lowest address of the memory is performed.
When shifting to the write operation, the write-side address control unit 11
Outputs a SET signal, and receives the SET signal.
The cyclic flag control unit 12 sends the cyclic flag signal
Address setting unit, and the write-side address control unit 1
1. A cyclic flag signal is sent to the read-side address control unit 13.
Output a signal. The condition for releasing the cyclic flag signal is as follows.
Data from the data storage unit 15 composed of
Data is stored at the highest address of the memory during a read operation.
The read operation of the read data is performed, and the data is read.
Read out from lowest address of memory
When the operation shifts to the next operation,
A RESET signal is output, and the RESET signal is
Is received, the cyclic flag control unit 12
Release the flag signal and write address
Output to control unit 11 and read-side address control unit 13
The output of the traveling flag signal is stopped. Write address control unit 11, read
In the side address control unit 13, the data is output from the comparison unit 14.
The EVEN signal and the tour output from the tour flag controller 12
The data storage unit 15
It is possible to determine the storage status of data in the
To determine whether to perform the write and read operations.
It becomes possible. Between the EVEN signal and the cyclic flag signal
Table 1 shows the combination conditions. [0028] [Table 1] In Table 1, both the EVEN signal and the cyclic flag signal are set.
The defined state (FULL state in Table 1) is the data
Up to the limit of the number that can be stored in the storage unit (data latch unit) 15
Indicates that data is being stored,
Reading is possible, but new writing is not possible.
Which indicates that. Although the EVEN signal is set,
The cyclic flag signal is released (EMP in Table 1).
(TY state) indicates that all data is stored in the data storage unit 15.
Indicates that the status has not been written.
Possible, but no new read is possible
are doing. If the EVEN signal is released,
Regardless of the setting or cancellation of the lag signal, the data storage unit 15
Of new data, new data from the data storage unit 15
It is necessary to be able to read data
Is shown. The operation of the write-side address control unit 11 is as follows.
When a cell data write request is received,
Check the flag signal and EVEN signal,
When new data can be written to 15
Only necessary processing for writing is performed. Cyclic flag signal,
As a result of the confirmation of the EVEN signal, it is in the FULL state,
If writing is impossible,
Output to the write requester that it was not possible
You. Writing is possible and a writing operation is performed.
In this case, the write-side address control unit 11
Write data, and every time writing is completed,
The write address value output to the storage unit 15 is
One is updated, and the writing process ends. Each time there is a write request, the cyclic flag signal
No. and EVEN signal are confirmed, and the confirmation result is FULL
This operation is sequentially repeated until the state is reached. When the writing operation is repeated, the data
To the highest address of the memory constituting the data storage unit 15
And the write address is the lowest in the memory.
When moving to the address, the traveling flag control unit 12
To output the SET signal. The operation of the read-side address control unit 13 is as follows.
When a cell data read request is received,
Check the flag signal and EVEN signal,
15 when new data can be read from
Performs the processing required for reading. Confirmation of the cyclic flag signal and the EVEN signal
As a result, it is in the EMPTY state and new reading is not possible.
If it is in the state, it means that reading was impossible.
Output to the read request side. Reading is possible and a reading operation is performed.
In this case, the read-side address control unit 13
Reads data, and every time reading is completed,
The read address value output to the storage unit 15 is
One is updated, and the reading process ends. Each time there is a read request, the cyclic flag signal
Signal and EVEN signal are confirmed, and the confirmation result is EMPTY
This operation is sequentially repeated until the state is reached. When the read operation is repeated, the data
The highest address of the memory constituting the data storage unit 15
The data is read out and the read address is
When moving to the lowest address of the
12, the RESET signal is output. As described above, according to the first embodiment,
The data storage circuit 10 writes the cell data to the memory.
Write request signal and generate write signal
Write-side address control unit 11 for controlling addresses
And the write side address is the highest address of the sequential update memory.
Address, then write to the lowest address of the memory.
A traveling flag control unit 12 indicating that the
Data read request signal and read to memory
Signal generation and control of read address given to memory
The read-side address control unit 13 to perform
Each of the address control unit 11 and the read address control unit 13
Compare the address value given to the memory
A comparison unit 14 for managing the amount of data stored in the
Data storage consisting of one memory for storing cell data
And a data storage unit comprising a memory.
15 for writing and reading data.
Since the dress value is given as described above,
2 where the byte length of data is 53 etc.^NPlaces that do not match
Use all of the memory space
And it is possible to eliminate unused areas of memory.
You. Therefore, the circuit area (memory area) that is not used at all
Eliminate inefficient circuits such as
A circuit can be realized. In addition, a flip-flop or a D-latch
Instead, use the data storage circuit according to the present embodiment.
Thus, it is possible to avoid a large-scale circuit. In the present embodiment, the one for ATM cells is used.
Shown when using as time accumulation buffer
However, of course, the present invention is not limited to this. For example, in the above configuration
Write and read processing in 1-byte units
It is possible to use not only ATM cells but also CPU peripherals.
Temporary storage of data in Ral (DMA, cache, etc.)
Also, it can be used in connection with a data path. FIG. 2 is a data diagram according to a second embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a data storage circuit, and is a data storage circuit according to the present embodiment.
Data storage circuit shown in Fig. 1 in describing the data storage circuit
The same components as those in 10 are denoted by the same reference numerals. In FIG. 2, the data storage circuit 20
Receiving a write request signal to the memory
Write signal generation and memory according to the byte length of cell data
Memory write address control and
Counter for counting the number of written bytes of cell data
Write-side address control unit 21 having cell data unit
Receiving the read request signal of the
Generation of read signal to memory and read to memory
Address control and reading of cell data during reading
Read-side address that has a counter that counts the number of
From the dress control unit 22 and the write address control unit 21
UP indicating that the writing of one cell data has been completed
Signal and one cell from the read address control unit 22
Using a DOWN signal indicating that data has been read,
Management of the number of cell data stored in the data storage unit 15
23 (management means) that performs
And a data storage unit 15 using one memory.
Have been. Further, the comparison unit 23 is a data storage unit 1
5 that manages the number of cell data stored in
Counter 23a. The write address control unit 21 and the read
The overflow address control unit 22 controls the address as a whole.
Means 24 constitutes the management means. The data storage constructed as described above will now be described.
The operation of the circuit 20 will be described. First, the comparator 23 has a write-side address.
When all cell data has been written from the data control unit 21
(If the data length of the cell data is 53 bytes, 53 bytes
Output when all the data has been written to the memory)
UP signal indicating that writing of one cell data has been completed
Number is entered. Also, from the read-side address control unit 22
When all cell data has been read,
If the data length of the file data is 53 bytes, 53 bytes
Output when all have been read from memory)
DOW indicating that writing of one cell data has been completed
The N signal is input to the comparison unit 23. In the comparison section 23, when the UP signal is input
Has one storage number counter 23a in the comparison unit 23.
When the DOWN signal is input after being incremented and updated, the comparing unit
Subtracting and updating the accumulation number counter 23a in the memory 23 by one
, The data storage unit 1 constituted by a memory
5 is managed. Further, the write-side address control unit 21
Sent to the memory from the outgoing side address control unit 22
By comparing each address value, the
It manages that simultaneous access does not occur. The power of the accumulation number counter 23a in the comparing unit 23
The count value is stored in the memory constituting the data storage unit 15.
When the number of cell data that can be stored has been reached, a write request
It is not possible to write new data to the source.
FULL signal indicating that a new write
Request not to cause a request. The accumulation number counter 23 in the comparison unit 23
If the count value of “a” becomes “0”, readout is required.
New data cannot be read from the request source.
Outputs the EMPTY signal indicating that there is
And do not make a request. The operation of the write-side address control unit 21 is as follows.
When a cell data write request is received,
Check that no FULL signal is input from unit 23
After that, new data is written to the data storage unit 15.
Performs the necessary processing for writing. When the FULL signal is not input and the
Only when writing operation is performed.
The address control unit 21 receives the write request signal
Later, the internal byte length counter 21a is updated.
Write the number according to the preset cell data length.
Output to the data storage unit 15
Then, writing of 1-byte data of the cell data is completed.
Writing to the data storage unit 15 every time
Only one address value is updated and the internal byte length
Cell data in which the count value of the
Is equal to the byte length value of the
When the write of the data has been completed,
The signal is transmitted once, and the writing process is completed. Every time there is a write request, the FULL signal
After confirming, the FULL signal is output from the comparing unit 23
Until the above, this operation is sequentially repeated. The operation of the read-side address control unit 22 is as follows.
When a cell data read request is received,
Check that the EMPTY signal is not
After the confirmation, new data is read from the data storage unit 15.
Performs the processing required for delivery. When the EMPTY signal is not input,
Data can be read out, and when performing a read operation,
The side address control unit 22 receives the read request signal and
After that, the internal byte length counter 22a is updated.
Read the number according to the preset cell data length
Output to the data storage unit 15,
Reading of 1-byte data of cell data ends.
The readout address output to the data storage unit 15 each time
The address value is updated by one, and the internal byte length counter
22a of the cell data for which the count value is set in advance.
It is equal to the byte length value, and all byte data
When the reading of the data is completed,
The signal is transmitted once, and the reading process is completed. Every time there is a read request, the EMPTY signal
Is checked, and the EMPTY signal is output from the comparator 23.
This operation is repeated until the operation is completed. As described above, according to the second embodiment.
The data storage circuit 20 stores data in the memory in units of cell data.
Receives a write request signal and responds to the byte length of the cell data.
Generated write signal and write address to memory
Control of cell address and cell data being written
Write address with a counter that counts the number of bytes
The control unit 21 receives a read request signal in cell data units.
Of the read signal to the memory according to the cell data length
Control of read address given to generation and memory and read
Count the number of read bytes of cell data being output
A read-side address control unit 22 having a counter;
Manages the number of cell data stored in the data storage unit 15.
Storage address counter 23a for controlling the write address.
Completion of writing one cell data from unit 21
Signal from the read address control unit 22
DOWN signal indicating that one cell data has been read
The cell data stored in the data storage unit 15 is
The comparison unit 23 manages the number of data, and stores the cell data.
A data storage unit 15 using another memory;
Data for the data storage unit 15 composed of memory
Write address value for writing and reading
As described above, the byte length of the cell data is 5
2 of 3 etc.^NMemory does not match
It is possible to use all of the space and unused memory
The use area can be eliminated. So use it at all
Ineffective, such as having a circuit area (memory area)
Efficient circuits can be realized by eliminating efficient circuits. In this embodiment, the data storage unit 15
The capacity corresponding to the number of cell data that can be stored in the memory
By providing the counter 23a in the comparison unit 23,
Easily judge the possibility of writing and reading in data units
Simultaneous access to the same address in memory.
It is possible to avoid the danger of the In addition, a flip-flop or a D-latch
Use memory to avoid large circuit
It is possible to do. In this embodiment, the ATM cell data
The data length of packets and other data is determined to some extent
Can be used for semi-fixed length data such as
You. Also, in the case of a CPU peripheral, 1
When the byte length transferred in each data transfer is fixed
It can be used in any case. Further, the write-side address control unit 21,
Bytes inside each of the read-side address control units 22
Set values of number counters 21a and 22a to external setting
If more variable, the data length can be handled
It becomes unusable and can be used for any data length.
You. FIG. 3 is a data diagram according to a third embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a data storage circuit, and is a data storage circuit according to the present embodiment.
Data storage circuit shown in Fig. 2 in describing the data storage circuit
The same components as those in 20 are denoted by the same reference numerals. In FIG. 3, a data storage circuit 30
Receiving a write request signal to the memory
Write signal generation and memory according to the byte length of cell data
Memory write address control and
Counter for counting the number of written bytes of cell data
A write address control unit 21 having
Address value given to the memory from the address control unit 21
Manages the amount of data stored in memory based on
And a comparison unit 31 for generating a read-side address.
And one memory that stores cell data
And a data storage unit 15. Further, the comparing section 31 stores the data
5 that manages the number of cell data stored in
Counter 31a and a read address calculation unit 31b.
The accumulation number counter 31a controls the write-side address.
Indicates that the cell data output from the unit has been accumulated
In addition to the addition by the UP signal,
Readout of file data
The read address calculation unit 31b subtracts
Count value of counter 31a and write-side address control unit
Read using the write address initial value given from
It has a function to calculate and derive the read address. The write-side address control unit 21 stores
Number counter 31a and read address calculation unit 31b
The comparison unit 31 provided with the address control unit 3 as a whole
Constituting No. 2. The data storage constructed as described above will now be described.
The operation of the circuit 30 will be described. First, the comparison unit 31 has a write-side address.
When a new write request is issued from the
Write address of the address when writing to the
When the initial value of the address and all cell data have been written
(If the data length of the cell data is 53 bytes, 53 bytes
Output when all the data has been written to the memory)
UP signal indicating that writing of one cell data has been completed
Number is entered. In the comparison section 31, when the UP signal is input
The cell data storage number counter 3 in the comparison unit 31
The count value of 1a is updated by one. When a read request occurs, the comparing unit 31
Reads the value of the cell data accumulation number counter 31a,
After confirming that data is stored, write
The write address given by the address control unit 21
From the initial value, the read address calculation unit 31b
Which data is read out of the stored cell data
It should be calculated and derived, and the read address
Set. The setting of the read address is performed as follows.
It is done. First, the cell data storage number counter value is read.
The number of stored cell data "A"
When grasping, as shown in equation (1), “A”
Multiplied by the byte length "B" of the
Subtract from the initial dress value “C”
The period value “D” is derived. [0073]     Read address initial value “D” = C−A × B (1) Read address initial value “D” derived by Equation 1
In contrast, every time 1 byte data is read,
Read data sequentially by adding 1 to the dress value
U. This operation is represented by equation (2). [0074]     E = D + 1 (2) To update the read address value, read 1-byte data.
Each time it issues, the internal byte length counter is updated by 1, and the internal buffer is updated.
Cell where the count value of the site length counter is set in advance
It continues until it becomes equal to the byte length value of the data. Reading of one cell data length is completed.
And the count value of the cell data accumulation number counter 31a
Then, the reading process is completed. The cell data storage number counter as described above
By performing the addition and subtraction processing of 31a, the memory
Is stored in the data storage unit 15 configured as
Manage the number of cell data and read address
Is generated. The number of cell data stored in the comparing unit 31 is
The count value of the counter 31a forms the data storage unit 15.
When the number of cell data that can be stored in the memory
Writes new data to the source of the write request.
Output a FULL signal indicating that the
Instructs not to generate a new write request. The number of cell data stored in the comparing section 31 is
When the count value of the counter 31a becomes "0",
Read new data to read request source
Outputs an EMPTY signal indicating that the
Instructs not to generate a read request. The operation of the write-side address control unit 21 is as follows.
When a cell data write request is received,
Check that no FULL signal is input from unit 31
After that, new data is written to the data storage unit 15.
Performs the necessary processing for writing. When the FULL signal is not input and the
When performing a write operation, the write side
The dress control unit 21 has received the write request signal.
After that, the internal byte number counter 21a is updated.
Write the number according to the preset cell data length.
Output to the data storage unit 15
Then, writing of 1-byte data of the cell data is completed.
Writing to the data storage unit 15 every time
Only one address value is updated, and the internal byte count
Cell data in which the count value of the
Is equal to the byte length value of the
When the writing of the data is completed, the comparing unit 31
P signal is sent once, and a new write request signal is sent.
The address value to write the first byte when the signal is input
Notify the comparison unit 31 as the write address initial value and write
Finish the writing process. Each time there is a write request, the FULL signal
After confirming, the FULL signal is output from the comparison unit 31
Until the above, this operation is sequentially repeated. As described above, according to the third embodiment.
The data storage circuit 30 stores data in the memory in units of cell data.
Receives a write request signal and responds to the byte length of the cell data.
Generated write signal and write address to memory
Control of cell address and cell data being written
Write address with a counter that counts the number of bytes
Control unit 21 and cells stored in data storage unit 15
An accumulation counter 31a for managing the number of data;
And a write address system.
Based on the address value given to the memory from the control unit 21
When managing the amount of data stored in memory,
A comparison unit 31 that mainly generates a read-side address;
Consists of one memory that stores data
Since the data storage unit 15 is provided, the data
The write-in address control unit 21 counts the number of stored data.
By using the signal from the comparing unit 31
Reads data from the configured data storage unit 15
Control of the address and the like for
Reducing the circuit size of the entire circuit constituting the FO
It becomes possible. Also, a data storage unit composed of a memory
15 for writing and reading data.
By giving the dress value as described above,
Even if the byte length of the cell data is 2 such as 53^NMatches
Use all of the memory space, even when not
To eliminate unused areas of memory.
Thus, an efficient circuit can be realized. In particular, in this embodiment, the data storage unit 15
Corresponding to the number of cell data that can be stored in the memory
The comparison unit 31 having the counter 31a writes the cell data.
Integrated readability judgment processing according to the
Access to the same address in memory
It is possible to easily avoid the danger of noise. In the third embodiment, the expression (1) and the expression
The operation (2) is not only realized by a hardware configuration.
Alternatively, it can be realized by software processing. Performance
When the calculation part is realized by software,
Set value of the byte length counter 21a inside the control unit 21
Can also be set by software
Therefore, the variable length of the data to be handled is the same as that of the second embodiment.
As is the case, it can be used for any data length.
You. In the case of the third embodiment, the data to be stored is
The data length of the data has been shown to be several bytes,
To store data in 1-byte units,
(1) may be modified and used as in the following equation (3).
And can be realized by Equation (2) is the third real
Used in the same manner as in the embodiment. [0087]     Read address initial value “D” = CA (3) Where A is the data storage counter value in 1-byte units C: Write address initial value D: Read address initial value In each of the above embodiments, the ATM communication method is used.
Data that constitutes a buffer for temporarily storing ATM cells.
Data storage circuit, but not limited to ATM cells.
What data buffer, eg CPU peripheral
Data (DMA, cache, etc.)
Or, of course, you can use it for the data path.
Absent. The data storage circuit is exchanged with an ATM.
Can be used for machines, workstations, etc.
Can be applied to any terminal, for example, ATM
It may be built-in as a buffer type switch
No. [0089] 【The invention's effect】In the data storage circuit according to the present invention, the cell
Memory for storing data and cell data being written
Has a counter that counts the number of written bytes
Receiving a write request signal to the memory
Write signal generation and memory according to the byte length of cell data
Write side that controls the write address for memory
Address control unit and cell data stored in memory
Stored number counter for managing the number and read address
Has a read address calculation unit for calculating
The address value given to the memory from the
Based on the amount of data stored in the memory
And a comparison unit that generates a read-side address.
The storage counter is provided by the write address control unit.
Indicating that the cell data output from the device has been stored
The signal is added by the signal, and the cell data is
Is decremented by performing the read processing of
The arithmetic operation unit calculates the count value of the storage
Write address initial value given from address control unit
Was used to calculate the read address using
And the byte length of the cell data is 2 such as 53. ^N Does not match
In such cases, use all of the memory space.
Thus, an unused area of the memory can be eliminated. [0090] [0091] [0092] [0093] [0094] Therefore, the circuit area (meaning area) not used at all
Memory area) and eliminate inefficient circuits
To realize an efficient circuit and avoid circuit enlargement.
Can be It also responds to cell data write situations.
The possibility of unified readability judgment processing can be
Easily avoids the risk of simultaneous access to the same address
can do.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a configuration of a data storage circuit according to a first embodiment to which the present invention is applied. FIG. 2 is a diagram illustrating a configuration of a data storage circuit according to a second embodiment to which the present invention has been applied. FIG. 3 is a diagram illustrating a configuration of a data storage circuit according to a third embodiment to which the present invention is applied. FIG. 4 is a diagram showing a configuration of a conventional buffer circuit. [Description of Signs] 10, 20, 30 Data storage circuit, 11, 21 Write-side address control unit, 12 Cyclic flag control unit, 1
3,22 Read-side address control unit, 14,23,3
1 comparison unit (management means), 15 data storage unit, 16,
24, 32 address control means, 21a, 22a byte number counter, 23a, 31a storage number counter, 31
b Read address operation unit

Claims (1)

(57) [Claims] (1)Cell used in ATM communication system
In a data storage circuit that temporarily stores data, etc., A memory for storing cell data; Counts the number of written bytes of cell data being written
To write data to memory in cell data units.
Receive request signal for
Write signal generation and write address to memory
A write-side address control unit for controlling Storage that manages the number of cell data stored in memory
Number counter and read to calculate read address
An address operation unit, and the write address control unit
Memory address based on the address value given to the memory
Manages the amount of data stored in
A comparison unit for generating a source address, The accumulation number counter includes:
U indicating that the cell data output from
The signal is added by the P signal, and the cell is
It is subtracted by performing the data read processing, The address calculation unit is configured to count the accumulation number counter.
Value and the write given from the write-side address control unit.
The read address using the initial value of the embedded address
To A data storage circuit characterized in that: