JP3072175B2 - UPC circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a UPC circuit, and more particularly, to a UPC circuit for controlling the flow rate of a cell based on prescribed information on the traffic of the cell. B-ISD
N (Broadband-Integrated Services Digital Network
ATM) which transfers cells asynchronously (Asy)
nchronous Transfer Mode) technology is being developed. In this ATM network, control is performed to limit the cell flow rate based on the traffic report value of the subscriber. This control is performed by policing control or UPC (Usage Parameter Control).
This technology is indispensable for the smooth operation of ATM networks. However, this makes the realization of the UPC circuit difficult since the traffic report value differs for each subscriber.

[0002]

2. Description of the Related Art FIGS. 21 and 22 are diagrams for explaining various polishing control systems that have been proposed. FIG. 21A shows a time interval method, in which a time interval t at which each cell arrives is measured by a counter circuit, and these are compared with a specified time T to determine the flow rate. FIG. 21B shows the TX method, in which the number of cells x arriving during the specified period T is measured by a counter circuit, and the number of cells x is compared with the specified number of cells X to determine the flow rate. Do. FIG. 21C shows the DB (Da
ngerous Bridge) method, and the transit time of one cell Δt
A counter circuit measures the number x of cells arriving during each of the specified times T, each of which is shifted in phase, and compares these with the specified number of cells X to determine the flow rate.

FIG. 22A shows the CAT-M method, in which the time interval t until the number of arriving cells reaches a value obtained by adding 1 to the specified number of cells X is shifted by a phase every time one cell arrives. The flow rate is determined by measuring and comparing these with the specified time T. FIG. 22B shows the LB method, in which the counter circuit counts up each time one cell arrives, and always counts down at a predetermined rate, and compares this count value with a specified count value to determine the flow rate. Is what you do.

In the time interval method, the time interval t between cells is limited for each cell, so that there is little time for cell density.
On the other hand, according to the TX method, this margin is large, but when cells are concentrated near the boundary of the period T, these cannot be effectively limited. Therefore, attention is paid to the DB method and the CAT-M method. FIG. 23 is a block diagram of a conventional UPC circuit.
1 shows an example of a (DB-Bridge Memory) method. In the figure, 100 is a cell, 101 is a header part, and 102 is a payload (data) part. Further, 1 is a cell information branching unit (SB), 2 is a cell delay unit (SM), 3 is a cell control unit (SC), 21 is a bridge memory (BM) composed of a shift register having a _Tmax length, and 22 is a multi-tap. Circuit (TA
P), 23 ₀ ~23 _m determination unit, SF is the target cell filter identifying each specific header information vp ₀ ~vp _m, C
TR is a counter circuit operating in an up / down mode,
CMP is a comparator, and PM is a declared value X _{0 of the} number of cells.
A parameter memory holding to X _m.

The cell arriving at the IN on the highway receives predetermined header information vp (VPI: Virt) at the cell information branching unit 1.
ual Path Identifier) is branched (copied) and temporarily stored in the cell delay unit 2. On the other hand, the bridge memory 21 stores the branched header information vp in a time-series manner, and the multi-tap circuit 22 reads each time corresponding to the subscriber's reported time values T _{0 to} T _m from the bridge memory 21 having the T _max length. Each of the delay header information vp 'is extracted and the determination unit 23 ₀
２３23 _m .

[0006] In determining section 23 _0, counter circuit CT
R indicates that one of the target cell filters SF is in the bridge memory 2
When the header information vp ₀ input to 1 is identified, the count is incremented. When the other target cell filter SF identifies the header information vp ₀ ′ output from the multi-tap circuit 22, the count is decreased. Thus, the counter circuit CTR outputs the number x ₀ of cells on the bridge in a time series during each specified time T ₀ shifted in phase by one cell transit time Δt. The comparator CMP compares each measured cell number x ₀ with the specified cell number X _{0. When the} comparator CMP determines that x ₀ > X ₀ , the cell control unit 3 discards the cell of the cell delay unit 2, and If it is determined that x ₀ ≦ X ₀ , the cell is passed as it is. Other determination unit 23 ₁ ~ 23 _m in the same manner.

However, if the UPC circuit is provided with a multi-tap circuit as described above, the wiring of the tap circuit becomes enormous, and it is not easy to change the tap. by the way,
Be controlled so as shift register RAM, can be omitted multi-tap circuit made to correspond to the time it reported value T ₀ through T _m of subscribers read address of the RAM. But D
In B-BM method sometimes must read header information vp _{0'~vp m} 'simultaneously from a plurality of read address of the RAM during the arrival 1 cells. For this reason, access competition occurs, and it is difficult to realize such RAM read control. Further, the bridge memory 21 determining section 23 _0-23
There is a configuration provided for each _m (Japanese Patent Application No. 3-204285), but the amount of hardware is enormous.

FIG. 24 is a block diagram of another conventional UPC circuit.
The figure shows an example of the CAT-M method. 4 in the figure
1 is a clock timer (TM) that counts the current time t,
42 ₀~ 42_mIs the determination unit, SF is the target cell filter, S
R is the declared value of the number of cells X₀~ X_mWith the number of stages equivalent to
Shift register (SR), SUB is a subtraction circuit, CM
P is a comparator, and PM is a reported value T at a time interval.₀~
T_mIs a parameter memory that holds.

[0009] In determining unit 42 _0, the target cell filter SF is a shift register for identifying the header information vp ₀ S
The arrival time t _{0 of the} cell is written in R. Since the number of stages of the shift register SR is X ₀ , the target cell filter SF
Identifies the (X ₀ +1) -th header information vp ₀ , the write information t ₀ ′ is read from the shift register SR. The subtraction circuit SUB subtracts the read time t ₀ ′ of the shift register SR from the current time t, and thus the time interval DT ₀ until the number of arriving cells reaches the specified number of cells X ₀ +1.
Is changed every time one cell arrives, and is output momentarily. The comparator CMP compares each measurement time DT ₀ with the specified time T _{0. If the} comparator CMP determines that DT ₀ <T ₀ , the cell controller 3 discards the cell of the cell delay unit 2 and DT ₀ ≧ If it is determined that T ₀ is passed through the cell. Other determination unit 42 ₁ through 42 _m are similar.

However, as described above, the shift register SR
Is provided for each of the determination units 42 _{0 to} 42 _m , the amount of hardware becomes enormous. Since the time information t has a large number of bits, the scale of the shift register SR and the subtraction circuit SUB also increases.

[0011]

As described above, the conventional U
In the PC circuit, since the declared value of the traffic differs for each subscriber, there is a disadvantage that the UPC circuit becomes complicated and enormous if it is attempted to cover all of them. The purpose of the present invention is
It is an object of the present invention to provide a UPC circuit having excellent versatility and expandability by using a simple traffic determination unit as a constituent unit.

[0012]

The above-mentioned problem is solved, for example , by referring to FIG.
Is solved. That is, in the UPC circuit of the present invention, in the UPC circuit that controls the flow rate of the cell based on the regulation information on the traffic of the cell, the bridge memory BM that stores the type information of the arriving cell in time series and the bridge memory BM stores the information. and the fast pointer holding means XP for holding the storage location of the type information of a given cell is, to control these elements, fast pointer holding means
And a control unit CTL that makes a policing determination by directly referring to the storage location information held by the XP .

[0013]

In FIG. 1A, a cell arriving at the IN on the highway has a predetermined header information (cell type information) vp branched by a cell information branching unit SB, and a cell delay unit SM
Is stored temporarily. On the other hand, the bridge memory BM stores the type information vp of the arriving cell in a time series, and the fast pointer holding means XP holds the storage position of the type information vp of the predetermined cell stored in the bridge memory BM. . The control unit CTL controls these elements.
And fast pointer holding means XP holds
The policing determination is performed by directly referring to the storage location information . This
Specifically, the fast pointer holding means XP
For example, since the storage position of the cell type information a is held,
The control unit CTL can access the file without accessing the BM one by one.
Storage location of the cell type a from the pointer storage means XP
Can be obtained directly, and based on this, policing of the incoming cell a
The judgment can be made appropriately. In addition, this control unit CTL
For the next cell type a, the XP value of the cell type a
Policing control of incoming cell a
It is not necessary to detect other cell types b and c.
No. Note that the fast pointer holding means XP is replaced with another cell type.
If it is used for b, c, etc., other cell types b, c, etc.
Can be treated similarly. Therefore, depending on the total number of cell types,
However, the policing control is simple and constant. Scratch
Thus, according to the present invention, a simple traffic determination unit is configured.
Offers UPC circuits with excellent versatility and expandability as a unit.
it can.

Preferably, when a predetermined cell arrives, the control unit CTL determines a violation of the arriving cell by obtaining a time interval from the entrance of the bridge memory BM to the storage position indicated by the fast pointer holding means XP. For example, in FIG. 1B, the arrival cell a is discarded because the measurement time DT is shorter than the specified time Ta. Also, in FIG. 1 (C) where two cell times have passed,
Since the measurement time DT is longer than the specified time Ta, the arrival cell a is not discarded.

Preferably, when the control unit CTL determines that the arrival cell is not a violation, the control unit CTL records the position information of the entrance of the bridge memory BM in the fast pointer holding unit XP. Also preferably, a counting unit CM is provided for counting the number of type information of the predetermined cell stored in the bridge memory BM, and the control unit CTL controls the counting unit CM to count the number of type information of the predetermined cell from the entrance of the bridge memory BM. Control is performed so that counting is performed up to n times in the past. This allows the control unit CTL to consider the type information of up to n past predetermined cells stored in the bridge memory BM as a policing determination target.

Preferably, n is the prescribed number X of predetermined cells. Preferably, when the count value of the counting means CM is smaller than n at the arrival of the predetermined cell, the control unit CTL unconditionally determines that there is no violation. Thus, the control unit CTL can quickly determine that there is no violation without finding the measurement time DT.

Preferably, the control unit CTL causes the fast pointer holding unit XP to hold the storage position of the type information of the predetermined cell that has arrived the number of times previously indicated by the counting unit CM. Thus, the control unit CTL obtains the time interval DT from the entrance of the bridge memory BM to the n-th storage location pointed to by the fast pointer holding unit XP when a predetermined cell arrives.

Preferably, the bridge memory BM includes a next pointer storage area NP in association with the type information storage area VP, and the control unit CTL uses the next pointer storage area NP to store the type information of a plurality of predetermined cells. The areas VP are linked. Also preferably, last pointer holding means LP for holding the storage position of the type information of the predetermined cell lastly stored in the bridge memory BM is provided, and when the control unit CTL determines that the arrival cell is not violated, the last pointer holding means LP Bridge memory B indicated by
The entry position information of the bridge memory BM is recorded in the next pointer storage area NP on M.

Preferably, when the count value of the counting means CM is n at the arrival of a predetermined cell, the control unit CTL stores the information stored in the next pointer storage area NP on the bridge memory BM pointed to by the fast pointer holding means XP. It is recorded in the pointer holding means XP. Preferably, the bridge memory BM includes one or more flag storage areas F in relation to the type information storage area VP, and the control unit CTL uses the flag storage area F to use the storage area on the bridge memory BM. / Control unused.

Preferably, the control unit CTL forcibly sets the contents of the flag storage area F at the storage position to be the entrance of the bridge memory BM to unused. Further, preferably, the control unit CTL forcibly sets the contents of the flag storage area F of the predetermined cell that has arrived before the storage position indicated by the fast pointer holding unit XP to unused.

Preferably, the control unit CTL performs a plurality of policing determinations on a predetermined cell by using a plurality of flag storage areas F. Preferably, the fast pointer holding means XP is provided for each cell type information. Preferably, a counting means CM is provided for each cell type information. Preferably, a last pointer holding means LP is provided for each cell type information.

Preferably, the fast pointer holding means X
P is stored in RAM. Preferably, the bridge memory B
M is composed of a RAM operating in the FIFO mode. Preferably, the bridge memory BM is provided in common for the type information of a plurality of types of cells.

Preferably, the storage capacity of the bridge memory BM is a maximum, a maximum of a plurality of types of specified time intervals T, or a minimum 2 ^k (k is a natural number) larger than the maximum. Preferably, the control unit CTL detects a hardware abnormality by detecting that the count value of the counting means CM is negative or greater than n. Also, preferably, when accessing the bridge memory BM by the fast pointer holding unit XP or the last pointer holding unit LP, the control unit CTL finds a hardware abnormality by checking the type information of the storage location.

Preferably, the control unit CTL resets the counting means CM when detecting a hardware abnormality,
At the same time, at least the flag storage area F of the bridge memory BM is made unused. Also, preferably, the control unit CTL periodically resets the counting means CM, and also makes at least the flag storage area F of the bridge memory BM unused.

Preferably, when resetting the counting means CM, the control unit CTL does not perform processing of the arriving cell for a predetermined time.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described below in detail with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. FIG. 2 shows U of the first embodiment.
FIG. 1 is a block diagram of a PC circuit. In the figure, reference numeral 1 denotes a cell information branching unit (SB), 2 denotes a cell delay unit (SM), 3 denotes a cell control unit (SC), and 4 denotes a (T _max +1) _-length RAM. Bridge memory (BM), 5 is control and parameter memory (CPM), 6 is CPU (control unit CTL in FIG. 1)
3 to FIG. 5 and FIG.
ROM storing the control program of FIGS.
Is a common bus of the CPU 6, 9 is a bus decoder (BD), 1
0 is a 3-state buffer circuit (B).

In the BM 4, F is a flag, NP is a next pointer, and VP is a storage area for cell type information. In CPM5, CM ₀ ~CM _m counter memory, XP ₀ ~XP _m Fast pointer, LP
_{0 to} LP _m is the last pointer, T _{0 to} T _m are the specified time,
X ₀ to X _m are each storage area specified number of cells. CP
In U6, DT is a register, WP is a write pointer, and RVP is a register.

The cell arriving at the IN on the highway receives predetermined header information H (VPI: Virtua) at the cell information branching unit 1.
l Path Identifier, VCI: Virtual Channel Identi
fier, CLP: Cell Loss Priority, etc.), and are temporarily stored in the cell delay unit 2. on the other hand,
The CPU 6 extracts the cell type information vp from the branched header information H, measures the traffic of the arriving cell based on the type information vp, and determines whether or not there is a violation. Then, according to the determination result of the CPU 6, the cell control unit 3 passes the cell of the cell delay unit 2 as it is when the arriving cell is not a violation, and discards or marks the cell if it is a violation.

FIGS. 3 to 5 are flowcharts of the policing control process of the first embodiment. FIG. 3 is a flowchart of the policing determination process, FIG. 4 is a flowchart of the bridge memory pointer process, and FIG. 5 is a flowchart of the bridge memory shift process. is there. In the following description, if it is expressed as for example X (a) = 0, and represents that the contents of the storage area X _a specified number of cells to be indexed by the type information a in CPM5 is 0. Other notations can be similarly interpreted.

When power is supplied to the UPC circuit of the embodiment, FIG.
Is input to the judgment process. <Determination processing> In step S1, the arrival of a cell is waited. When the cell arrives, predetermined header information H is read in step S2. In step S3, cell type information vp (vp = a in this example) is extracted from the read header information H and stored in the register RVP.

In step S4, the specified number of cells X (a) = 0
It is determined whether or not. If X (a) = 0, set cell a to 1
Since no cell is passed, the process proceeds to cell discarding in step S8 and thereafter. If X (a) is not 0, C
The process proceeds to the following step S5 to make a determination based on M. <Determination by CM> In step S5, CM (a) = X
(A) It is determined whether or not. CM (a) <For X (a), T _max number of the number of cells specified cell in X number of cells in naturally T _a because of the less than (a) even if the number of defined cell X
Less than (a). Therefore, in this case, it can be unconditionally determined that the arrival cell a is not a violation. The flow is step S
Go to 10. In step S10, it is determined whether CM (a) = 0. If CM (a) = 0, cell a on BM4
Does not exist, the process proceeds to the pointer creation process of FIG. If CM (a) is not 0, the process proceeds to pointer addition in FIG.

Further, in the determination in step S5, CM (a) =
In the case of X (a), the process proceeds to the following step S6 to make a determination by DT. <Determination by DT> In step S6, the entrance WP of the BM 4
From the storage location pointed to by XP (a). More specifically, when WP ≧ XP (a), DT = WP−XP (a) is calculated, and WP <XP
In the case of (a), for example, DT = WP + _Tmax + 1-XP
The calculation of (a) is performed. In step S7, DT ≧ T (a)
It is determined whether or not. Arrival cell a if DT ≧ T (a)
Is not a violation, the process proceeds to the pointer rewriting process of FIG.
If DT ≧ T (a) is not satisfied, the arriving cell a is a violation, and the process proceeds to the following step S8 in order to discard the cell.

<Cell Discard> In step S8, the flag F
By writing 0 to (WP), the information in the storage area related to the flag F (WP) is invalidated (not used). In step S9, a cell discard command is sent to the bus decoder 9, and the cell a is discarded. Then, the process proceeds to the shift processing of FIG. <Pointer creation processing> In step S20, V of BM4
The type information a of the arriving cell is written in P (WP), and the flag F is set to 1 (valid or used). Step S
21 and S22, LP (a) and XP (a) are both BM4
Point to the entrance WP. In step S19, the CM
(A) is incremented, and the process proceeds to the shift processing in FIG. <Pointer addition processing> First, in processing P3, a pointer of the arrival cell a is added. That is, in step S16, BM4
WP is written to the NP indicated by LP (a). Step S
Reference numeral 17 writes a in the VP (WP) of the BM 4 and also sets the flag F to 1. In step S18, LP (a)
By writing WP to the entry of BM4. In step S19, CM (a) is incremented, and the process proceeds to the shift processing in FIG. <Pointer rewriting process> First, in process P1, the process P3
Similarly, the pointer of the arrival cell a is added. In the subsequent process P2, the pointer of the cell a exceeding CM (a) = X (a) is deleted. That is, in step S14, first, XP
Write 0 to the VP indicated by (a). Step S1
It is not necessary to execute the processing enclosed by the one-dot chain line of No. 4. Next, the flag F is set to 0 in step S14. In step S15, the contents of the NP indicated by XP (a) are written into XP (a), and the process proceeds to the shift processing in FIG. <Shift process> In step S31, WP is incremented. In the step S32, it is determined whether or not F (WP) = 1. If F (WP) = 0, the unused storage area of the BM 4 has reached the entrance, and the flow returns to the determination processing as it is.

When F (WP) = 1, it means that valid cell information comes out of the BM 4, and a process of deleting the pointer of the cell is performed. That is, in step S33, the content of the CM indicated by VP (WP) is decremented. In step S34, XP indicated by VP (WP)
To store the contents of the NP (WP). In step S35, 0 is written to F (WP). Then, the process returns to the determination processing.

FIGS. 6 to 10 are diagrams for explaining the operation of the UPC circuit according to the first embodiment. Here, cell a is targeted,
A specific operation will be described on the assumption that the specified time T = 4 and the specified number of cells X = 2. In FIG. 6A, the cell a in the BM is empty, and the first cell a has arrived here. Since the determination in step S5 is not CM = X (= 2) and the determination in step S10 is CM = 0, the flow proceeds to pointer creation processing. In FIG. 6B, B
F = 1 and VP = a are written in the storage area pointed to by the WP of M4, and both XP and LP point to the location pointed to by the WP. Then, CM = 1. When this is shifted, it becomes (C) of FIG.

In FIG. 7A, the cell a has arrived again after the arrival of empty cells for six cells. Since the determination in step S5 is not CM = X (= 2) and the determination in step S10 is CM = 1, the flow proceeds to pointer addition processing. In FIG. 7B, B
Write the contents of WP to NP pointed by LP of M4, BM
In the storage area pointed to by the WP of No. 4, F = 1 and VP = a are written. And XP is the same, LP is WP
Point to the location pointed by, and CM = 2. Shifting this results in FIG. 7C.

FIG. 8 shows a case where another cell b arrives after FIG. 7C. In FIG. 8A, the determination is not performed for the cell a, but is performed only for the cell b.
In FIG. 8B, the pointer creation processing is performed for the cell a while the cell a remains the same. When this is shifted, it becomes (C) in FIG. 8. At this time, the storage position of the first cell a in which F = 1 (valid) goes around the entrance of the BM4.
(A) is decremented, and XP (a) is
The content of the NP indicated by (a) is loaded, and the flag F indicated by WP is forcibly set to F = 0 (invalid). in this way,
The management of the storage area on the BM 4 is simple because only the flag F needs to be set to 1/0.

FIG. 9 shows a case where the cell a arrives after FIG. 7C. In FIG. 9A, the determination in step S5 proceeds to the determination based on DT based on CM = X (= 2). Since the determination by DT is DT ≧ T (8 ≧ 4), the arrival cell a is not a violation, and the flow proceeds to the pointer rewriting process. In (B) of FIG. 9, N indicated by LP of BM4
The content of WP is written in P, and F = 1 and VP = a are written in the storage area pointed to by WP of BM4. And L
P points to the location to which WP points. further,
The flag F pointed to by XP is set to 0, and then XP returns to its NP
, Ie, in this case, the location pointed to by the LP before the pointer addition processing. In addition, since the value of the CM is + -1, nothing is performed. When this is shifted, it becomes (C) of FIG. At this time, nothing is performed because the storage location of the first cell a, which has already been set to F = 0, goes around the entrance of the BM.

FIG. 10 shows a case where the cell a arrives after FIG. 9C. In FIG. 10A, the determination in step S5 proceeds to the determination based on DT based on CM = X (= 2). Since the determination by DT is not DT ≧ T (3 ≧ 4), the arrival cell a is a violation, and 0
Is written. Then, the arrival cell a is discarded. In FIG. 10B, since the arriving cell a has been discarded, pointer processing is not performed. When this is shifted, it becomes (C) of FIG.

In the above embodiment, the BM length is a plurality of types of prescribed time.
Maximum T of interval T_maxThe description is made assuming that 1 is added to.
However, if you have other suitable buffer means,
BM length is T_maxIt is good. Publicly available RAM
Is 2ⁿConsidering that the storage capacity of T
_maxIs (2ⁿ-1) is desirable. But T
_maxIs (2ⁿ-1) if not T_maxGreater than
Minimum 2^k(K is a natural number) BM may be used.

As described above, the UPC circuit of the embodiment provides complete policing control for all types of cells having an arbitrary combination of T and X, despite a small hardware configuration. In addition, it has an architecture with excellent expandability and flexibility. For example, even if T _max , X or the total number of cell types increases, the policing control can be extended without affecting the number of accesses to the BM 4, that is, the processing speed. it can. In addition, the measurement of the absolute arrival time of a cell as performed by the conventional CAT-M method is unnecessary, and the hardware configuration is significantly reduced.

When a hardware abnormality occurs in the UPC circuit of the first embodiment, it is desired to detect the abnormality at an early stage and quickly return to a normal state. According to the above embodiment, for example, if the count value of the CM is normal, it is 0 to
Should be in the X range. Therefore, hardware abnormality is found by detecting that the CM count value is negative or greater than X. Further, according to the above embodiment, for example, when accessing the BM 4 by XP (a) or LP (a), the cell type information a
Should be remembered. Therefore, a hardware abnormality is found by confirming this.

When such a hardware abnormality is found, preferably, all the CMs are reset, and at least the flag storage area F on the BM 4 is made unused. In this case, the policing control for all types of cells is restarted from the pointer creation processing, and the UP control is performed.
The C circuit can be promptly returned to a normal state. Also,
If any hardware abnormality occurs, the CM count value may differ from the number of cells actually recorded as valid (F = 1) on the BM. However, it is extremely difficult to actually detect such a state. However, if such a state is left as it is, erroneous polishing control is continued, which causes inconvenience. Therefore, in consideration of such a case, all CMs are periodically
Is reset, and at least the flag storage area F on the BM 4 is made unused. In this way, the policing control for all types of cells is periodically restarted from the pointer creation processing, and the UPC circuit can be maintained in a normal state.

FIGS. 11 to 13 are flowcharts of the policing control in consideration of the hardware abnormality of the UPC circuit of the first embodiment. FIG. 11 shows another judgment processing of the first embodiment.
2 is a flowchart of another pointer processing of the first embodiment, and FIG. 13 is a flowchart of error processing of the first embodiment. In FIG. 11, (A) of FIG. 11 replaces the process H1 of FIG. 3, and (B) of FIG. 11 replaces the process H2 of FIG.
In FIG. 11A, the process of step S41 is added before the process of step S1. In this step S41, it is determined whether or not a timer (not shown) has timed out (TOUT). If not, the process proceeds to step S1. In case of timeout,
Proceed to error processing 3. As a result, an error process described later is forcibly executed periodically.

In FIG. 11B, the judgments in steps S42 and S43 are added to the terminal on the NO side of the judgment in step S10. Thereby, CM (a) is obtained in step S10.
If = 0, it is determined in step S42 whether CM (a) <0. When CM (a) <0, the process proceeds to error processing. When CM (a) <0, the process proceeds to step S43.
It is determined whether (a)> X (a). CM (a)> X
In the case of (a), the process proceeds to error processing, and CM (a)> X
If not (a), the process proceeds to the pointer addition process in FIG.

In FIG. 12, (A) of FIG. 12 replaces the processes P1 and P3 of FIG. 4, and (B) of FIG. 12 replaces the process P2 of FIG. In FIG. 12A, the determination in step S51 is added before the processing in step S11. In this step S51, it is determined whether or not the content of the VP indicated by LP (a) is a. If it is not a, the process proceeds to error processing. If it is a, the process proceeds to step S11. The same applies to the process P3.

In FIG. 12B, the determination in step S52 is added before the processing in step S14. In this step S52, it is determined whether or not the content of the VP indicated by XP (a) is a. If it is not a, the process proceeds to error processing. If it is a, the process proceeds to step S14. FIG. 13 is a flowchart of the error processing of the first embodiment. In processing E1, the contents of all CMs are reset. That is, step S61
Then, m is set in the register RVP, and 0 is written in CM (RVP) in step S62. In step S63, RVP is decremented, and in step S64, RVP is decremented.
It is determined whether or not = 0. If RVP = 0, the process returns to step S62, and if RVP = 0, reset of all CMs ends.

In the following processing E2, the contents of all the flags F are invalidated. That is, in step S65, a value L corresponding to the BM length is set for WP, and in step S66, F (W
Write 0 to P). In step S67, WP is decremented, and in step S68, it is determined whether WP = 0. If WP = 0, the process returns to step S66, and WP
When = 0, the contents of all flags F become invalid. The flow returns to the determination processing of FIG.

As described above, during the error processing, the processing of the arriving cell is not performed. After the error processing is completed, all the CM = 0 and all the flags F = 0. 4 is input to the pointer creation process, and the pointer is re-performed. FIG. 14 is a block diagram of a UPC circuit according to a second embodiment. In this second embodiment, a plurality of flag storage areas are used to perform policing determination and peak value declaration for a predetermined cell based on average value declaration. And a policing decision based on the policing decision.

In the figure, reference numeral 4 'denotes a bridge memory (BM) having a plurality of flag storage areas AF and PF. Reference numeral 5' denotes a control for performing a plurality of systems of policing determination on a predetermined cell and a control for holding parameter information. And a parameter memory (CPM). Also BM
In 4 ', AF is a storage area for flags used in the traffic average value control system, and PF is a storage area for flags used in the traffic peak value control system. In CPM5', ACM ₀ ~ACM _m counter memory used by the average value control system traffic, PCM ₀ ~PCM _m is a counter memory used in the peak value control system traffic. Others are the same. In the CPU 6, MC is a mode counter that defines an execution mode of the control program. It should be noted that CM ₀ and CM ₁ in FIG.
Obviously, M ₀ and PCM ₀ may be used respectively.

FIGS. 15 to 17 are flowcharts of the policing control processing of the second embodiment. FIG. 15 shows policing determination processing, FIG.
FIG. 17 is a flowchart of the shift processing of the bridge memory. Note that the same processes as those in FIGS. 3 to 5 are denoted by the same process numbers and description thereof is omitted. Here, the control principle of the second embodiment will be briefly described. First, the processing from the terminal of FIG. 15 to the terminal of FIG. 16 is repeatedly executed for the peak value control of MC = 0 and the average value control of MC = 1. Then, the WP increment of step S31 in FIG. 17 is executed once, and then the process proceeds from step S32 to step S3 in FIG.
The processes up to 5 are repeatedly executed for the peak value control of MC = 0 and the average value control of MC = 1.

In FIG. 15, in a step S71, the mode counter MC is set to 0, and the processing after the step S4 is executed. In FIG. 16, at step S72, M
It is determined whether or not C = 1. If MC is not 1, MC is incremented in step S73, and the process returns to the terminal in FIG. If MC = 1 in step S72, the process proceeds to the shift process in FIG. In FIG. 17, in step S31, WP is incremented. Step S74
Then, MC is set to 0, and the processing after step S32 is executed. Then, in a step S75, it is determined whether or not MC = 1. If MC is not 1, M is set in step S76.
C is incremented, and the process returns to step S32. Also M
If C = 1, the process returns to the determination process in FIG.

The policing control in consideration of the hardware abnormality as shown in FIGS. 11 to 13 may be employed for the UPC circuit of the second embodiment. 18 to 20
FIG. 8 is a diagram illustrating the operation of the UPC circuit according to the second embodiment.
Here, the cell a is targeted, and the specified time P for peak value control is set.
T = 3, prescribed number of cells PX for peak value control = 2, prescribed time AT for average value control = 6, prescribed number of cells for average value control AX =
A specific operation will be described as 3.

In FIG. 18A, the cell a in the BM 4 'is empty, and the first cell a has arrived here.
In the peak value control of MC = 0, the judgment in step S5 is not PCM = PX (= 2), and step S10
Is determined to be PCM = 0, so that the flow proceeds to pointer creation processing. In FIG. 18B, PF = 1 and VP = a are written in the storage area indicated by WP,
PXP and PLP both point to the location pointed to by WP. Then, PCM = 1.

Next, in the average value control of MC = 1, the determination in step S5 is not ACM = AX (= 3), and the determination in step S10 is ACM = 0.
The flow proceeds to pointer creation processing. In FIG. 18B, AF = 1 and VP = a are stored in a storage area pointed to by WP.
And AXP and ALP both point to the location pointed to by WP. Then, ACM = 1. When this is shifted, it becomes FIG. 18C.

In FIG. 19A, the information of the second cell a is recorded at the seventh cell time, and the third cell a has arrived. It is assumed that the policing control based on the average value is actually performed at this timing. First, in the peak value control of MC = 0, the determination in step S5 proceeds to the determination based on the time interval DT by PCM = PX (= 2). Judgment by DT is DT ≧ PT
Based on (8 ≧ 3), it is determined that the arrival cell a is not a violation. Since the policing control based on the average value is actually performed at this timing, the policing control system based on the peak value only updates the information such as the BM 4 'and the related pointers. In this case, the flow proceeds to pointer rewriting processing. In FIG. 19B, the BM
The contents of the WP are written into the NP indicated by the PLP of 4 ′,
The storage area pointed to by the WP of M4 'is PF = 1 and VP = a
And write. Then, the PLP points to the location pointed to by the WP. Further, the flag PF indicated by the PXP is set to 0, and thereafter, the PXP points to the content of the NP, that is, the location pointed to by the PLP before the pointer addition processing. Note that the PCM remains unchanged.

Next, in the average value control of MC = 1, the determination in step S5 is not ACM = AX (= 3), and it is determined that the arriving cell a is not violated unconditionally. Therefore,
The arriving cell a is not actually discarded. Step S10
Is ACM = 2, the flow proceeds to pointer addition processing. In (B) of FIG. 19, BM4 '
Of the WP is written to the NP indicated by the ALP of the BM4.
AF = 1 and VP = a are written in the storage area pointed to by WP ′. And while AXP remains as it is, ALP
Point to the location pointed to by WP, and ACM = 3.

When this is shifted, it becomes FIG. 19C. That is, first, in the peak value control of MC = 0, the storage location of the first cell a already set to PF = 0 is BM
Nothing is done because it goes around the entrance of 4 '. Then MC =
In the mean value control of 1, since the storage position of the first cell a where AF = 1 is wrapped around the entrance of the BM 4 ', the ACM is decremented by this, and the AX is sent to the AXP.
The contents of the NP pointed to by P are loaded, and the flag A pointed to by WP
F is forced to zero.

FIG. 20 shows a case where the fourth cell a arrives after (C) in FIG. It is assumed that the policing control based on the peak value is actually performed at this timing. First, in the peak value control of MC = 0, the determination in step S5 proceeds to the determination based on the time interval DT by PCM = PX (= 2). DT ≧ P in the judgment by DT
Since it is not T (2 ≧ 3), the arrival cell a is determined to be in violation. The cell a is actually discarded. In FIG. 20B, the arriving cell a has been discarded, so BM4 '
Is not written to. Also, no pointer processing is performed.

Next, in the average value control with MC = 1, the determination in step S5 is not ACM = AX (= 3), and the determination in step S10 is ACM = 2.
The flow proceeds to pointer addition processing. In FIG. 20B, WP is written in the NP indicated by the ALP of the BM 4 ′, and AF = 1 and V are written in the storage area indicated by the WP of the BM 4 ′.
Write P = a. Then, while AXP remains as it is, ALP points to the location pointed to by WP.
Then, ACM = 3. When this is shifted, FIG.
(C) of FIG.

Thus, a plurality of flag storage areas AF,
By using the PF, a plurality of systems of policing determination can be performed on the predetermined cell a. According to the above example, the control system based on the average value and the control system based on the peak value respectively perform traffic monitoring and management according to their own setting parameters. At this point, even if switching control such as performing policing control based on the average value is performed,
A policing decision reflecting each monitoring situation can be made.

The polishing control based on the peak value and the polishing control based on the average value may be performed simultaneously in parallel. In the above example, according to the average value control, up to three cells are allowed to pass during the specified time AT = 6. However, when this is simultaneously observed by the peak value control, the specified time PT = In other words, a state where three cells continuously pass during three is not allowed.

In the second embodiment, the cell a actually discarded by the peak value control is recorded in the BM 4 'as not violating the cell a determined by the average value control. However, the present invention is not limited to this. For example, the cell a actually discarded by the peak value control can be forcibly processed as a violation even in the average value control, or can be processed as if the cell a did not come. The same applies to the opposite case. In these cases, it is not necessary to provide a plurality of LPs like PLP and ALP.
One may be provided.

In the above embodiment, all the CMs are reset when a hardware error is detected or periodically, and at least the flag storage area F on the BM is made unused. However, the present invention is not limited to this. In some cases, it is possible to recover from an abnormal state by resetting a specific type of CM and making its flag storage area F unused. Further, in the above-described embodiment, the case where the policing determination based on the declaration of the average value and the policing determination based on the declaration of the peak value are performed on the cell of the predetermined type has been described, but the present invention is not limited to this. There may be three or more flags, and the purpose of using these flags in the control system is arbitrary.

[0065]

As described above, according to the present invention, the bridge memory BM for storing the type information of the arriving cell in time series.
And fast pointer holding means X for holding the storage position of the type information of the predetermined cell stored in the bridge memory BM.
And P, to control these factors, Fast point
And a control unit CTL that makes a policing determination by directly referring to the storage location information held by the data holding unit XP. The circuit can be provided in a small size.

[Brief description of the drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is a block diagram of a UPC circuit according to the first embodiment.

FIG. 3 is a flowchart of a determination process according to the first embodiment.

FIG. 4 is a flowchart of a pointer process according to the first embodiment.

FIG. 5 is a flowchart of a shift process according to the first embodiment.

FIG. 6 is a diagram illustrating the operation of the UPC circuit according to the first embodiment.

FIG. 7 is a diagram illustrating the operation of the UPC circuit according to the first embodiment.

FIG. 8 is a diagram illustrating the operation of the UPC circuit according to the first embodiment.

FIG. 9 is a diagram illustrating the operation of the UPC circuit according to the first embodiment.

FIG. 10 is a diagram illustrating the operation of the UPC circuit according to the first embodiment.

FIG. 11 is a flowchart of another determination process of the first embodiment.

FIG. 12 is a flowchart of another pointer process of the first embodiment.

FIG. 13 is a flowchart of an error process according to the first embodiment.

FIG. 14 is a block diagram of a UPC circuit according to a second embodiment.

FIG. 15 is a flowchart of a determination process according to the second embodiment.

FIG. 16 is a flowchart of a pointer process according to the second embodiment.

FIG. 17 is a flowchart of a shift process according to the second embodiment.

FIG. 18 is a diagram illustrating the operation of the UPC circuit according to the second embodiment.

FIG. 19 is a diagram illustrating the operation of the UPC circuit according to the second embodiment.

FIG. 20 is a diagram illustrating the operation of the UPC circuit according to the second embodiment.

FIG. 21 is a diagram illustrating various policing control schemes already proposed.

FIG. 22 is a diagram illustrating another policing control method already proposed.

FIG. 23 is a block diagram of a conventional UPC circuit.

FIG. 24 is a block diagram of another conventional UPC circuit.

[Explanation of symbols]

 SB Cell information branching unit SM Cell delay unit SC Cell control unit BM Bridge memory XP Fast pointer holding unit CTL control unit 100 cells

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Naoaki Yamanaka 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Yoichi Sato 1-16-1 Uchisaiwaicho, Chiyoda-ku, Tokyo Japan (56) References JP-A-1-183938 (JP, A) 1991 IEICE Fall Conference B- 393 (August 15, 1991) 1992 IEICE Spring Conference B- 681 (March 15, 1992) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 12/28 H04L 12/56

Claims (26)

(57) [Claims] 1. A UPC circuit for controlling the flow rate of the cell on the basis of the definition information about the traffic of the cell, and the bridge memory <br/> for storing the type information of the arrival cell in time series, the bridge memory stores Fast pointer holding means for holding the storage position of the type information of the predetermined cell; controlling these elements and holding the fast pointer
UPC circuit, characterized in that it comprises a control unit means for direct reference to policing determine the storage location that holds the. 2. The control unit , when a predetermined cell arrives, sets a bridge.
2. The UPC according to claim 1, wherein a violation of the arriving cell is determined by obtaining a time interval from an entrance of the memory to a storage position indicated by the fast pointer holding unit.
circuit. 3. The control unit , if it is determined that the arriving cell is not violated, a bridge to the fast pointer holding means.
3. The UPC circuit according to claim 2, wherein position information of an entrance of the memory is recorded. 4. A comprising a counting means for counting the number of type information of a predetermined cell bridge memory has stored, control
The control unit causes the counting means to bridge the number of type information of the predetermined cell.
3. The UPC according to claim 2, wherein the control is performed so as to count from the entrance of the memory to n in the past.
circuit. Wherein the n is UPC circuit according to claim 4, characterized in that a number of provisions cells given cell. 6. The control unit counts when a predetermined cell arrives.
6. The UP according to claim 5, wherein when the count value of the means is smaller than n, it is determined unconditionally that no violation occurs.
C circuit. 7. The control unit according to claim 1, wherein the storage location of the type information of the predetermined cell arriving earlier by the number indicated by the counting means is stored in the fast poi.
6. The UPC circuit according to claim 5, wherein said UPC circuit is held by a center holding means . 8. The bridge memory has a next pointer storage area in association with a type information storage area , and the control unit uses the next pointer storage area to store a plurality of types of predetermined cell type information. 8. The UPC circuit according to claim 7, wherein the storage areas are chained. 9. A last pointer for storing a storage position of the type information of the predetermined cell stored last in the bridge memory.
Means, and when the control unit determines that the arrival cell is not violated, the bridge unit indicated by the last pointer holding means is provided.
Claim, characterized in that to record the position information of the bridge memory <br/> inlet to next pointer storage area on memory 8
UPC circuit. 10. The control unit counts when a predetermined cell arrives.
If the count value of the means is n, the fast pointer
Storage of next pointer on bridge memory pointed to by holding means
10. The UPC circuit according to claim 9, wherein the storage information of the area is recorded in a fast pointer holding unit . 11. A bridge memory stores a type information storage area.
Comprising one or more flag storage areas in relation to
Controller UPC circuit according to claim 10, characterized in that to control the use / unused storage area on the bridge memory using the flag storage area. 12. The UPC circuit according to claim 11, wherein the control section forcibly sets the contents of the flag storage area at the storage position to be the entrance of the bridge memory to unused. 13. The control unit flag memory area of a predetermined cells arriving before storage location pointed to fast pointer holding means
UPC circuit of claim 11, characterized in that the forced unused contents of A. 14. The UPC circuit according to claim 11, wherein the control unit uses a plurality of flag storage areas to make a plurality of policing decisions for a predetermined cell. 15. The UPC circuit according to claim 1, wherein a fast pointer holding means is provided for each cell type information. 16. The UPC circuit according to claim 4, wherein a counting means is provided for each cell type information. 17. The UPC circuit according to claim 9, wherein a last pointer holding means is provided for each cell type information. 18. The UPC circuit according to claim 15, wherein said fast pointer holding means is accommodated in a RAM. 19. The system according to claim 1, wherein the bridge memory is constituted by a RAM operating in a FIFO mode.
PC circuit. 20. The UPC circuit according to claim 1, wherein the bridge memory is provided commonly for a plurality of types of cell type information. 21. The storage capacity of the bridge memory is set to a plurality of types.
2. The maximum of the specified time interval , the maximum +1, or the minimum 2 ^k (k is a natural number) larger than the maximum.
UPC circuit. 22. The apparatus according to claim 11, wherein the control section detects a hardware abnormality by detecting that the count value of the counting means is negative or greater than n.
PC circuit. 23. The control unit, when accessing the bridge memory by the fast pointer holding means or the last pointer holding means , finds a hardware abnormality by confirming the type information of the storage location. The UPC circuit according to claim 11, wherein 24. The control unit resets the counting means if found hardware abnormality, together bridge notes
UPC circuit of claim 22 or 23, characterized in that the unused at least flag storage area of the Li. 25. The control unit periodically resets the counting means, and simultaneously stores at least a flag in the bridge memory.
The U of claim 11, wherein the area is unused.
PC circuit. 26. The UPC circuit according to claim 24, wherein the control unit does not perform processing of the arriving cell for a predetermined time when the counting means is reset.