JP3204765B2 - Policing control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a broadband ISDN (Broadband as
pect of Integrated Service Digital Network,
UPC (Usage) in a subscriber system of B-ISDN.
Prameter Control: This is related to the policing control method that realizes the function.

[0002]

2. Description of the Related Art In B-ISDN, ATM (Asynchronous) is used.
s Transfer Mode: asynchronous transfer network), and all information is transferred using fixed-length packets called cells. In this ATM, the UPC of a device for terminating a subscriber line is used.
In the circuit, different treatment is required for a cell for transferring a normal user signal (hereinafter, referred to as a normal cell) and various special cells (OAM cells, unallocated cells, signaling, etc.) used for network management. is there.

For example, it has been proposed to classify cells into three types as follows. Normal cell (hereinafter, referred to as a cell): A cell for which policing (that is, monitoring whether or not the traffic volume of the cell violates the report parameter) is performed according to the report parameter of the user. Special cell that can be transmitted by the user (hereinafter, referred to as cell): A cell to be policed according to parameters determined by the network side. Special cells that cannot be transmitted by the user (hereinafter, referred to as cells): cells to be discarded.

In order to identify a cell from cell to cell, an ATM cell header (the first 5 bytes of the cell) is usually used.
And, if necessary, collation of the first one or two bytes of the information field (48 bytes following the header) is required. The matching pattern is a wildcard of 1 bit or 1 byte unit (a pattern that is regarded as matching the matching pattern regardless of whether the content of the corresponding bit / byte of the content of the received cell is “0” or “1”). For example, use of a symbol X) shown in Table 1 below has been proposed.

Now, a UPC that performs the above functions
As a circuit, no circuit has been put to practical use at present because the ATM is in the development stage, but a circuit as shown in FIG. 5 has been proposed.

In FIG. 5, 21 is a cell detector for detecting a cell, 22 is a cell detector for detecting a cell, 23 is a cell detector for detecting a cell, and 26 is a cell detector 21 for detecting a cell. A discard processing unit 24 for discarding the cell from the input cell stream when detected, monitors whether the cell of the input cell stream does not violate the specified flow rate when the cell is detected by the cell detector 22. A cell policing unit 27 is a discard processing unit that discards cells in the input cell stream when a violation is detected by the cell policing unit 24, and 25 is an input cell stream when a cell is detected by the cell detector 23. The cell policing unit 28 monitors whether or not the cell violates the specified flow rate. A discard processing unit 28 discards cells in the input cell flow when the cell policing unit 25 detects a violation.

[0007]

The above-mentioned UPC circuit has the following problems.

(A) The discarding priority in the case where a plurality of matching patterns are simultaneously matched by a wild card is fixed in hardware, and there is no flexibility in policing. For example, even when the input cell is determined to match both the cell and the cell by the wild card, the circuit of FIG.
First, if the cell is determined to be a cell,
At the same time, the possibility of being treated as a cell is eliminated.

(B) Since the cells, cells, and cell detectors 21 to 23 are circuits fixed in hardware, the number of cells, cells, and cell collation patterns is also fixed in hardware. No policing flexibility.

(C) A plurality of circuits, such as a detector, a policing unit, and a disposal unit, whose functions are duplicated, are used, and the hardware scale is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to enable policing to be performed flexibly in setting a discard priority or a collation pattern, and to reduce the hardware scale. It is also possible to reduce the amount.

[0012]

FIG. 1 is an explanatory view of the principle according to the present invention. The policing control method according to the present invention is, as a first mode, provided in parallel with an input cell flow, and checks an input cell against individual conditions corresponding to each of a plurality of types of cells. A plurality of detectors 30 that output detection signals of the cells corresponding to them, and the types of input cells are determined while prioritizing the types of cells by logically processing the detection signals of the plurality of detectors 30. A logic circuit 31, and a policing process is performed on an input cell based on a result determined by the logic circuit 31.

Further, the policing control method of the present invention
In the policing control method according to the first embodiment, the logic circuit is constituted by a programmable logic array so that the priority between cell types can be controlled from the outside.

Further, the policing control method of the present invention has a third
As an embodiment, a register for storing a collation pattern of a plurality of types of cells together with attribute information and priority information of the cell, and a comparator for comparing the input cell with the contents of the register to determine the type of the input cell are provided. In addition, a policing process is performed on an input cell in accordance with the priority based on the determination result of the comparator.

[0015]

The policing control method of the present invention has a fourth
In the third mode, the priority of the cell in the third mode is determined by an address of a register in which a collation pattern of the cell is written.

Further, the policing control method of the present invention has the fifth
In the embodiment, a discard processing unit through which an input cell flow passes is provided in the first to fourth embodiments, and the discard processing unit performs a discard process on cells of each type collectively. It was done.

[0018]

According to the policing control method of the first embodiment, a plurality of detectors 30 detect whether an input cell is of a predetermined type, and a logic circuit 31 logically processes a detection signal of the input cell to detect the cell type. The type of the input cell is determined while assigning priorities in between. The policing unit 32 causes the input cell to perform a policing process based on the determination result of the logic circuit 31.

In the policing control system of the second embodiment, the priority order between cell types can be externally controlled by configuring the logic circuit with a programmable logic array.

In the policing control method of the third embodiment, the type of the input cell is determined by comparing the input cell with the contents of a register by a comparator, and the policing unit gives priority to the input cell based on the comparison result. The policing process according to the order is performed.

[0021]

The priority of the cell can be determined based on the address of the register in which the cell collation pattern is to be written, for example, the lower the address, the higher the priority.

In each of the above-mentioned policing control systems, the discard processing section through which the input cell flow passes performs collective discard processing on each type of cell, thereby reducing the hardware scale. Can be.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a UPC circuit according to a policing control system as one embodiment of the present invention. In FIG. 2, 1
Is a cell detector that detects cells from the input cell stream, 2
Is a cell detector for detecting cells.

The cell detection signal of the detector 1 is
Is input to one input terminal of the AND gate 4 through
A cell detection signal from the detector 2 is input to the other input terminal of the AND gate 4. Therefore, this AN
A cell detection signal is output from the D gate 4 when the detector 1 is not detected and a cell is detected by the detector 2, but when a cell is also detected by the detector 1 at the same time. The output of the cell detection signal is masked. That is, a function of giving priority to cell detection is realized.

The cell detection signal from the detector 1 is input to one input terminal of the NOR gate 5, and the other input terminal of the NOR gate 5 receives the cell detection signal from the AND gate 4. As a result, when both detectors 1 and 2 are not detecting, NOR gate 5 outputs a signal indicating neither a cell detection signal nor a cell detection signal, that is, a cell detection signal.

Upon receiving the cell detection signal from the AND gate 4, the cell policing unit 6 monitors the traffic volume of the cells in the input cell flow based on the report parameters and the like. Output a signal.

Upon receiving the cell detection signal from the NOR gate 5, the cell policing unit 7 monitors the traffic volume of the cells in the input cell flow based on the report parameters and the like. Output a signal.

The OR gate 8 outputs a cell detection signal from the detector 1, a violation detection signal from the cell policing unit 6,
And a violation detection signal from the policing unit 7 of the cell is input, and when these signals are input, a discard instruction signal is output to the discard processing unit 9.

The discard processing unit 9 receives the input cell flow,
This circuit discards an input cell when a discard instruction signal is input from the gate 8.

The operation of this embodiment will be described below. First, when an input cell is a cell, it is detected by the detector 1, and a cell detection signal is input to the discard processing unit 9 as a discard instruction signal via the OR gate 8, and the cell is detected from the input cell stream. Discarded unconditionally (ie, top priority).

When the input cell is a cell, the detector 2
, And a cell detection signal is input to the policing section 6 via the AND gate 4, where policing is performed on the cell. As a result of this policing,
If there is a violation of the traffic amount or the like, a cell violation detection signal is generated. This signal is input to the discard processing unit 9 via the OR gate 8 as a discard instruction signal, and the cell is discarded from the input cell stream.

By the above-mentioned wild card or the like,
At the same time that the detector 2 detects a cell, the detector 1 may detect a cell. In this case, since the AND gate 4 is closed by the cell detection signal of the detector 1, the cell detection signal of the detector 2 is masked, so that the detection of the cell by the detector 1 is given priority. become.

When the input cell is a cell, the detector 1
And 2 do not output a detection signal. As a result, a cell detection signal is output from the NOR gate 5 and the policing unit 7
, And the policing unit 7 performs policing on the cell. As a result of this policing, if there is a violation of the traffic amount or the like, a violation detection signal is generated, and this is input to the discard processing unit 9 as a discard instruction signal via the OR gate 8, and cells are discarded from the input cell stream. You.

According to such an apparatus configuration, the cell detector can be constituted only by the NOR gate, and the discard processing section can execute the discard processing of the cell, the cell, and the cell collectively. Can be reduced. Further, for example, a change in the priority order between cells can be realized only by exchanging the output of the detector 1 and the output of the detector 2, and the circuit change accompanying the priority change can be reduced in scale.

In implementing the present invention, various modifications are possible. FIG. 3 shows a UPC circuit based on a policing control method as another embodiment. In the figure, blocks having the same functions as those in the embodiment of FIG. 2 are denoted by the same reference numerals. As a difference, in this embodiment, the logic circuit including the inverter 3, the AND gate 4, and the NOR gate 5 in the embodiment of FIG. 2 is a PLA (Programmable Logic).
Array: Programmable Logic Array) Circuit 10
It is composed of That is, the input cell, the cell detection signal of the detector 1, and the cell detection signal of the detector 2 are input to the PLA circuit 10, respectively. The cell detection signal generated by the internal logic is input to the OR gate 8, and the cell detection signal is output to the OR gate 8. The cell detection signal is sent to the policing unit 6 by the policing unit 7.
Respectively. At this time, for example, the priority order between cells can be arbitrarily set from the outside according to the setting contents of the PLA circuit 10. That is, it is possible to freely set whether to give priority to a cell or to give priority to a cell.

FIG. 4 shows a UPC circuit according to a policing control system as still another embodiment of the present invention. FIG.
In the figure, reference numeral 12 denotes a register formed of a RAM or the like for storing a cell-to-cell collation pattern.
And the attribute information (that is, cell or cell or cell type information) of the matching pattern is stored in the flag area.

[0038]

The comparator 11 compares the matching pattern stored in the register 12 with the input cell, and compares a match signal indicating whether or not the input cell matches, and attribute information of the input cell according to the comparison result with the policing unit 13. Output to When the attribute information is a cell, the policing unit 13 unconditionally instructs the discarding unit 8 to discard the cell. 8 and, if the cell is a cell, performs policing of the cell in the input cell flow, and if the cell is violated, notifies the discard processing unit 8 of the violation detection.

In this embodiment, the only specification of the register 12 in terms of hardware is that it has a capacity capable of storing the total number of types of cell collation patterns and types of cell collation patterns. The stored contents can be arbitrarily rewritten from outside by a soft strap. As a result, the type of cell-to-cell collation pattern, or the distribution of the number of types of cell collation patterns and the number of types of cell collation patterns can be arbitrarily set by a soft strap, thereby increasing the flexibility of policing.

Further, as still another embodiment of the present invention,
In the apparatus configuration of FIG. 4 described above, collation information as shown in Table 2 below is stored in the register 12, and as a result of comparing the input cell with the register contents, the priority information is also notified from the comparator 11 to the policing unit. You may do so.

[0042]

In this way, for example, when a cell and a cell are detected simultaneously, it is possible to determine which cell is to be prioritized, and it is possible to soft-strap the priority for each collation pattern. And the flexibility of polishing increases.

As a method of determining the priority, the priority is determined in accordance with the address of the register 12 in which the cell matching pattern is written, for example, by giving higher priority to the matching pattern of the lower address. You can also decide.

[0045]

As described above, according to the present invention, a flexible polishing process can be realized. Further, the device can be configured with a circuit having a small hardware scale.

[Brief description of the drawings]

FIG. 1 is an explanatory view of the principle according to the present invention.

FIG. 2 is a diagram illustrating a UPC circuit according to a policing control method as one embodiment of the present invention;

FIG. 3 is a diagram showing a UPC circuit according to a policing control method as still another embodiment of the present invention.

FIG. 4 is a diagram showing a UPC circuit according to a policing control method as still another embodiment of the present invention.

FIG. 5 shows a proposed UPC circuit.

[Explanation of symbols]

 1 Cell Detector 2 Cell Detector 3 Inverter 4 AND Gate 5 NOR Gate 6 Cell Policing Unit 7 Cell Policing Unit 8 OR Gate 9 Discarding Unit 10 PLA Circuit 11 Comparator 12 Register for Matching Pattern Storage 13 Policing Unit 21-23 Detector 24, 25 Policing unit 26-28 Discarding unit

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Naoaki Yamanaka 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Yoichi Sato 1-16-1 Uchisaiwaicho, Chiyoda-ku, Tokyo Japan (56) References JP-A-4-291549 (JP, A) JP-A-5-244189 (JP, A) JP-A-6-37790 (JP, A) JP-A-5-276188 ( JP, A) JP-A-5-227190 (JP, A) JP-A-5-191433 (JP, A) JP-A-5-284172 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , (DB name) H04L 12/56 H04L 12/28

Claims (5)

(57) [Claims] 1. A provided in parallel with the input cell stream, input
The force cells are divided into individual cells corresponding to each of several types of cells.
And if the condition is satisfied, the corresponding
Comprising a plurality of detectors for outputting detection signals Le and a logic circuitry to determine the type of the input cell while prioritizes between types of cells by logic processing the detection signals of the plurality of detector A policing control method for performing a policing process on an input cell based on a decision result of the logic circuit. 2. The policing control method according to claim 1, wherein said logic circuit is constituted by a programmable logic array so that the priority between cell types can be controlled from outside. 3. A register for storing a collation pattern of a plurality of types of cells together with attribute information and priority information of the cell, and a comparator for comparing the input cell with the contents of the register to determine the type of the input cell. wherein the Yu for the input cell based on the determination result of the comparator
A policing control method that performs policing processing in accordance with the priority order . 4. The policing control method according to claim 3, wherein the priority of said cell is determined by an address of a register in which a collation pattern of said cell is written. 5. providing the discard processing unit for input cell stream passes, by the disposal processing section to any one of claims 1 to 4 as constructed carried out collectively disposal for each type of cell The policing control method described.