JPH09330588A - Sequential data memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To store a data indicating significant information with a plurality of data as one set by providing an RAM means on the input side of a memory part. SOLUTION: There are arranged an internal RAM array 5 as memory part managed by a writing pointer 7 and a reading pointer 9, an input RAM array 1 provided on the input side thereof and an output RAM array 3 provided on the output side thereof. An input section of data 21 is provided with the RAM array 1 and an input address decoder 2 and an input data selection address AIO-AIm22 is inputted into the decoder 2 to write the input data 21 into the RAM array 1. Then, an output data selection address AOO-AOm24 is inputted into an output address decoder 4 to select a reading destination of a data 23 and an OE signal 28 is inputted to read the output data 23 from an output RAM array 3 through an output buffer 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequential data storage device for sequentially inputting and storing data and outputting the stored sequential data in a predetermined priority order.

[0002]

2. Description of the Related Art As a concrete example of such a sequential data storage device, a so-called first-in first-out (first-in first-out) system in which priority is given to the reading of data by reading the first written stored data first -In First-O
ut) type memory (hereinafter referred to as "FIFO memory")
On the contrary, the so-called first-in-last-out (First-In Last-
Out) type memory (hereinafter referred to as "FILO memory")
It has been known.

FIG. 2 shows a general structure of a conventional sequential data storage device.

In the sequential data storage device shown in FIG. 2, an internal RA is constituted by a plurality of random access memories (hereinafter referred to as "RAM") as a storage unit whose access position is managed by a write pointer 57 and a read pointer 59.
An M array 55, an input register 51 for sequentially holding data D0 to Dn71 to be written in the RAM array 55, and RA
The output register 53 sequentially holds the data Q0 to Qn73 read from the M array 55.

In this device, a write pointer 57 is controlled by a write control circuit 56, and WC (write control) is performed.
The timing of the writing system is set by the signal 76. Further, the read pointer 59 is controlled by the read control circuit 58, and a read system timing is set by an RC (read control) signal 77. The output of the read data Q0 to Qn73 is
The output buffer 60 is driven by an OE (output enable) signal 78. An RST (reset) signal 79 is issued as needed to drive the reset control circuit 61.

Whether the memory is a FIFO memory or a FILO memory is determined by the control method of the pointers 57 and 59.

FIG. 3 is a block diagram showing the structure of the FIFO memory disclosed in Japanese Patent Laid-Open No. 5-128839, and FIG. 4 is a block diagram of the FIFO memory disclosed in Japanese Patent Laid-Open No. 5-159561.

The FIFO memory shown in FIG. 3 includes a memory 101 having a management mechanism 111 as a storage unit, and the memory 10
And a circuit 102 that arbitrates access to the PID 1.

The circuit 102 cooperates with the management mechanism 111, and the memory 10 receives the write data input from the data terminal 103 according to the write signal received from the signal terminal 104.
1 is sequentially written, and the data stored in the memory 101 is read in the first-in first-out order according to the read signal received from the signal terminal 107, and is output from the data terminal 106. Addresses for writing and reading data are counted by counters 105 and 108, respectively, and the count value is cleared by signals from clear terminals 109 and 110.

The circuit 102 further includes terminals 113 and 11
4 and 115 are used to insert and delete data in the memory 101, and an address therefor is designated from the terminal 112.

The FIFO memory of FIG. 4 has a write pointer 2
04 and the read pointer 205, an array 201 of memory cells as a storage unit, and this cell array 20.
It has buffers 202 and 203 for temporarily holding the data 211 and 216 which are input to and output from each other.

The write pointer 204 sends a point signal 217 that shifts in accordance with the clock 212 to the signal line 221-.
1 to 221-32 are supplied to the cell array 201 to serially select a cell column, and the data group 214 is serially written therein. Read pointer 205 is clock 2
The point signal 218 that shifts according to 13
The data groups 215 are supplied from 22-1 to 222-32 to the cell array 201 to serially select cell columns.
Are read serially. Each point signal 217 or 218 is processed by the test circuit 206 or 207 and used as an external test signal.

In such a conventional sequential data storage device, one register holds data on the input side and the output side.

[0014]

Therefore, the data that can be designated by one pointer is limited to one register, and it is difficult to apply it when a plurality of data form a set and represent significant information. It was

The present invention has been made in view of the above points, and an object of the present invention is to provide a sequential data storage device suitable for storing data in which a plurality of data form one set and represent significant information. To provide.

[0016]

A sequential data storage device according to the present invention has first RAM means on the input side of its storage section.

In the sequential data storage device according to the present invention, the first RAM means is composed of a plurality of RAMs.
It further comprises first address decoder means capable of selecting one of the above.

In the sequential data storage device according to the present invention, a plurality of data can be written in the first RAM means.

The sequential data storage device according to the present invention further has means for writing a plurality of data written in the first RAM means as a set to a position in the storage section indicated by the write pointer means.

The sequential data storage device according to the present invention has second RAM means on the output side of the storage section.

Further, the sequential data storage device according to the present invention has the second RAM means on the output side of the storage portion.

The sequential data storage device according to the present invention further comprises means for reading a plurality of data written at the position in the storage portion indicated by the read pointer means as one set into the second RAM means.

In the sequential data storage device according to the present invention, the second RAM means comprises a plurality of RAMs.
It further has a second address decoder means capable of selecting one of the above.

The sequential data storage device according to the present invention can read a plurality of data from the second RAM means.

In the sequential data storage device according to the present invention, the storage section comprises a RAM array.

In the sequential data storage device according to the present invention, the storage unit first-in first-out or first-in first-out as a set of a plurality of data.

[0027]

Therefore, according to the present invention, the first side is provided on the input side of the storage section.
The sequential data storage device including the RAM means and the second RAM means on the output side performs a first-in first-out or first-in first-out operation on the storage unit as a set of a plurality of data.

More specifically, a plurality of RAMs (for example, the input RAM array 1) and a first address decoder means (for example, an input address) are provided in a data input section of a storage section (for example, the internal RAM array 5 in FIG. 1) including a RAM array. And a decoder 2) for writing a set of plural data to the storage unit.

These plurality of data are written as a group of data to the position in the storage section indicated by the write pointer means (for example, the write pointer 7). Further, from the position in the storage section indicated by the read pointer means (for example, the read pointer 9), the plurality of data written therein are read as a set of data.

In this respect, in the sequential data storage device, the data output section of the storage section has a plurality of RAMs (for example, output RAs).
It has an M array 3) and a second address decoder means (for example, an output address decoder 4), by which a set of a plurality of data is read from the storage section.

Therefore, the sequential data storage device according to the present invention holds a plurality of input data at a plurality of addresses in the first RAM means sequentially designated by the first address decoder means, and writes the plurality of held data. The data is written as a set of data to a position in the storage unit designated by the pointer unit, and the position of one set of the plurality of sets of data written in the storage unit is designated by the read pointer unit. The plurality of data forming one set of data is read and held at a plurality of addresses in the second RAM means sequentially designated by the second address decoder means, and this is used as output data.

[0032]

Next, embodiments of the present invention will be described in detail.

FIG. 1 is a block diagram showing the configuration of a sequential data storage device according to a preferred embodiment of the present invention.

The sequential data storage device of FIG. 1 is provided with an internal RAM array 5 as a storage unit managed by a write pointer 7 and a read pointer 9, an input RAM array 1 provided on the input side thereof, and an output side. And an output RAM array 3 that has been set.

The write pointer 7 is a WC (write control)
It is controlled by the write control circuit 6 responding to the signal 26, and the read pointer 9 is controlled by the read control circuit 8 responding to the RC (read control) signal 27.

The input RAM array 1 is addressed by the input address decoder 2 and receives a WE (write enable) signal 2
Input data D0 to Dn21 are written according to 5. Output RA
The M array 3 is addressed by the output address decoder 4 and reads in response to the RC signal 27. The read data Q0 to Qn23 are OE (output enable) signal 28
Is output via the output buffer 10 in response to the. 11
Is a reset control circuit for performing a pointer reset operation in response to an RST (reset) signal 29.

That is, the sequential data storage device of FIG. 1 is provided with the input RAM array 1 and the input address decoder 2 at the input portion of the data 21, and the input data selection addresses AI0 to AIm.
22 is input to the input address decoder 2 to select the write destination of the data 21, and the WE signal 25 is input to write the input data 21 to the input RAM array 1. The plural data 21 can be written by inputting the WE signal 25 while changing the input data selection address 22.

Next, when the WC signal 26 is input, the input RA
The plurality of data in the M array 1 are transferred as a group of data to the position in the internal RAM array 5 indicated by the write pointer 7. When this group of data is transferred, the write control circuit 11 advances the write pointer 7 by one.

Further, an output RAM array 3 and an output address decoder 4 are provided at the data output section, and when the read control signal 27 is inputted, a group of a plurality of data in the internal RAM array 5 is read by the read pointer 9.
Is transferred to the output RAM array 3 from the position indicated by. When this set of data is transferred, the read pointer 9 is advanced by one.

Next, output data selection addresses AO0 to AOm
24 is input to the output address decoder 4 to select the read destination of the data 23, and the OE signal 28 is input to read the output data 23 from the output RAM array 3 through the output buffer 10. A plurality of data can be read by inputting the OE signal 28 while changing the output data selection address 24.

In addition, the reset control circuit 111
By inputting the ST signal 29, the write pointer 7
Also, the read pointer 9 can be cleared.

Next, the detailed operation of the sequential data storage device shown in FIG. 1 will be described for the case where four 32-bit data are handled as one set of data.

The data input section is provided with an input RAM array 1 composed of four arrays and an input address decoder 2 for dividing AI0 to AI1 of the two input data selection addresses 52 into four signals.

Input data selection address 52 to "00"
And WE signal 25 are input to write D0 to D31 of the 32-bit input data 21 into the 0th array of the input RAM array 1.

Similarly, by inputting "01", "10" and "11" from the input data selection address 22 and inputting the WE signal 25, the 32-bit input data 2 is input.
D0 to D31 of 1 are written to the 1st to 3rd arrays of the input RAM array 1.

Next, when the WC signal 26 is input, the input RA
The four pieces of data in the M array 1 are transferred as a group of data to the position indicated by the write pointer 7 in the internal RAM array 5. When this batch of data is transferred,
The write control circuit 6 advances the write pointer 7 by one. In the case of the first-in first-out method, the write control circuit 6 advances the read pointer 9 by one.

On the other hand, the data output section is provided with an output RAM array 3 composed of four arrays and an output address decoder 4 for dividing AO0 to AO1 of the two output data selection addresses 24 into four signals.

When the RC signal 27 is input, a set of four data in the internal RAM array 5 is read by the read pointer 9
From the position indicated by to the output RAM array 3. When this group of data is transferred, the read control circuit 8 advances the read pointer 9 by one. In the case of the first-in last-out method, the read control circuit 8 returns the read pointer 9 by one, and also returns the write pointer 7 by one.

Next, the output data selection address 24 is changed to "0".
By inputting 0 ”and inputting the OE signal 28, 32
Q0 to Q31 of the bit input data 23 are read from the 0th array of the output RAM array 3 through the output buffer 10.

Similarly, by inputting "01", "10" and "11" from the output data selection address 24 and inputting the OE signal 28, the 32-bit output data 2
Q0 to Q31 of 3 are read from the 1st to 3rd arrays of the output RAM array 3 through the output buffer 10.

The 0th array of the input RAM array 1 corresponds to the 0th array of the output RAM array 3, and the selection of each array does not have to be performed sequentially from the 0th, but can be performed randomly. Moreover, the write pointer 7 and the read pointer 9 can be cleared by inputting the RST signal 29 to the reset control circuit 11.

[0052]

As is apparent from the above description, according to the present invention, the RAM means is provided on the input side and the output side of the storage unit, and a plurality of data are stored in the storage unit as first-in first-out or first-in first-out. Since it can be output later, the present invention can be applied to data in which a plurality of pieces of data form one set and indicate one piece of information.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a sequential data storage device according to a preferred embodiment of the present invention.

FIG. 2 is a block diagram showing a general configuration of a conventional sequential data storage device.

FIG. 3 is a block diagram of a conventional FIFO memory.

FIG. 4 is a block diagram of a conventional FIFO memory.

[Explanation of symbols]

 1 Input RAM Array 2 Input Address Decoder 3 Output RAM Array 4 Output Address Decoder 5 Internal RAM Array 7 Write Pointer 9 Read Pointer

Claims (12)

[Claims] 1. A sequential data storage device comprising first random access memory means on the input side of the storage section. 2. The first random access memory means comprises a plurality of random access memories, and further comprises first address decoder means capable of selecting one of the random access memories. Sequential data storage device. 3. The sequential data storage device according to claim 1, wherein a plurality of data can be written in the first random access memory means. 4. The method according to claim 1, further comprising means for writing a plurality of data written in the first random access memory means as a set to a position in the storage section indicated by the write pointer means. A sequential data storage device according to claim 1. 5. The sequential data storage device according to claim 1, further comprising a second random access memory means on the output side of the storage section. 6. A sequential data storage device comprising second random access memory means on the output side of the storage section. 7. The unit according to claim 5, further comprising a unit for reading a plurality of data written in a position in the storage section indicated by the read pointer unit to the second random access memory unit. Sequential data storage device. 8. The second random access memory means comprises a plurality of random access memories, and further comprises second address decoder means capable of selecting one of the random access memories. A sequential data storage device according to any one of 1. 9. The sequential data storage device according to claim 5, wherein a plurality of data can be read from the second random access memory means. 10. The sequential data storage device according to claim 1, wherein the storage unit comprises a random access memory array. 11. The sequential data storage device according to claim 1, wherein the storage unit first-in first-out stores a plurality of data as a set. 12. The sequential data storage device according to claim 1, wherein the storage unit stores a plurality of data as a set in a first-in first-out basis.