JP2004214673A - ｐ型ドープされたポリシリコン又はポリシリコン・ゲルマニウムの仕事関数を定めるためのインジウムの使用 - Google Patents

ｐ型ドープされたポリシリコン又はポリシリコン・ゲルマニウムの仕事関数を定めるためのインジウムの使用 Download PDF

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Publication number
JP2004214673A
JP2004214673A JP2003433002A JP2003433002A JP2004214673A JP 2004214673 A JP2004214673 A JP 2004214673A JP 2003433002 A JP2003433002 A JP 2003433002A JP 2003433002 A JP2003433002 A JP 2003433002A JP 2004214673 A JP2004214673 A JP 2004214673A
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JP
Japan
Prior art keywords
silicon
layer
sige
sige layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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JP2003433002A
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English (en)
Japanese (ja)
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JP2004214673A5 (enExample
Inventor
Antonio Rotondaro
ロトンダロ アントーニ
James J Chambers
ジェイ、チャンバース ジェイムズ
Amitabh Jain
ジャイン アミタブー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JP2004214673A publication Critical patent/JP2004214673A/ja
Publication of JP2004214673A5 publication Critical patent/JP2004214673A5/ja
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/2807—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2003433002A 2003-01-03 2003-12-26 ｐ型ドープされたポリシリコン又はポリシリコン・ゲルマニウムの仕事関数を定めるためのインジウムの使用 Abandoned JP2004214673A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/336,563 US6803611B2 (en) 2003-01-03 2003-01-03 Use of indium to define work function of p-type doped polysilicon

Publications (2)

Publication Number Publication Date
JP2004214673A true JP2004214673A (ja) 2004-07-29
JP2004214673A5 JP2004214673A5 (enExample) 2007-02-08

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ID=32507419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003433002A Abandoned JP2004214673A (ja) 2003-01-03 2003-12-26 ｐ型ドープされたポリシリコン又はポリシリコン・ゲルマニウムの仕事関数を定めるためのインジウムの使用

Country Status (3)

Country Link
US (2) US6803611B2 (enExample)
EP (1) EP1435663A3 (enExample)
JP (1) JP2004214673A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007027500A (ja) * 2005-07-19 2007-02-01 Toshiba Corp 半導体装置およびその製造方法
JP2008135726A (ja) * 2006-10-23 2008-06-12 Interuniv Micro Electronica Centrum Vzw 主電極を含むドープされた金属を含む半導体装置
JP2009295802A (ja) * 2008-06-05 2009-12-17 Seiko Epson Corp 半導体装置及びその製造方法

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KR101258864B1 (ko) * 2004-12-07 2013-04-29 썬더버드 테크놀로지스, 인코포레이티드 긴장된 실리콘, 게이트 엔지니어링된 페르미－ｆｅｔ
US20060151846A1 (en) * 2005-01-13 2006-07-13 International Business Machines Corporation Method of forming HfSiN metal for n-FET applications
JP2008059641A (ja) * 2006-08-29 2008-03-13 Fujitsu Ltd 磁気ヘッドおよび記録媒体駆動装置
KR100861835B1 (ko) * 2006-08-31 2008-10-07 동부일렉트로닉스 주식회사 듀얼 게이트 ｃｍｏｓ형 반도체 소자의 제조 방법
US7858471B2 (en) * 2006-09-13 2010-12-28 Micron Technology, Inc. Methods of fabricating an access transistor for an integrated circuit device, methods of fabricating periphery transistors and access transistors, and methods of fabricating an access device comprising access transistors in an access circuitry region and peripheral transistors in a peripheral circuitry region spaced from the access circuitry region
US8940645B2 (en) 2007-05-25 2015-01-27 Cypress Semiconductor Corporation Radical oxidation process for fabricating a nonvolatile charge trap memory device
US9449831B2 (en) 2007-05-25 2016-09-20 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US8633537B2 (en) 2007-05-25 2014-01-21 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US20090179253A1 (en) 2007-05-25 2009-07-16 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US9299568B2 (en) 2007-05-25 2016-03-29 Cypress Semiconductor Corporation SONOS ONO stack scaling
US9431549B2 (en) 2007-12-12 2016-08-30 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a high dielectric constant blocking region
US20090152621A1 (en) * 2007-12-12 2009-06-18 Igor Polishchuk Nonvolatile charge trap memory device having a high dielectric constant blocking region
US20100052076A1 (en) * 2008-09-04 2010-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating high-k poly gate device
JP4837011B2 (ja) * 2008-09-18 2011-12-14 株式会社東芝 半導体装置、及び半導体装置の製造方法
US7968434B2 (en) * 2008-11-14 2011-06-28 Nec Corporation Method of forming of a semiconductor film, method of manufacture of a semiconductor device and a semiconductor device
US8124515B2 (en) 2009-05-20 2012-02-28 Globalfoundries Inc. Gate etch optimization through silicon dopant profile change
US8390063B2 (en) * 2010-01-29 2013-03-05 Broadcom Corporation Semiconductor device having a lightly doped semiconductor gate and method for fabricating same
KR102178827B1 (ko) 2014-02-13 2020-11-13 삼성전자 주식회사 Mosfet, 그 제조 방법, 및 mosfet을 구비한 반도체 장치
JP2016225421A (ja) * 2015-05-28 2016-12-28 セイコーエプソン株式会社 熱電変換素子及び焦電センサー
RU2674413C1 (ru) * 2017-12-29 2018-12-07 Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" Способ изготовления полупроводникового прибора
KR102612404B1 (ko) * 2019-03-08 2023-12-13 삼성전자주식회사 반도체 소자 및 그의 제조 방법
US20240413155A1 (en) * 2023-06-06 2024-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked multi-gate device with diffusion stopping layer and manufacturing method thereof

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US82863A (en) * 1868-10-06 Necticut
US201499A (en) * 1878-03-19 Improvement in digging-machines
US146457A (en) * 1874-01-13 Improvement in scissors
JP3246189B2 (ja) * 1994-06-28 2002-01-15 株式会社日立製作所 半導体表示装置
EP0707346A1 (en) * 1994-10-11 1996-04-17 Advanced Micro Devices, Inc. Method for fabricating an integrated circuit
DE19526184A1 (de) * 1995-07-18 1997-04-03 Siemens Ag Verfahren zur Herstellung eines MOS-Transistors
US6030874A (en) * 1997-01-21 2000-02-29 Texas Instruments Incorporated Doped polysilicon to retard boron diffusion into and through thin gate dielectrics
US6218274B1 (en) * 1997-10-28 2001-04-17 Sony Corporation Semiconductor device and manufacturing method thereof
US6124620A (en) * 1998-05-14 2000-09-26 Advanced Micro Devices, Inc. Incorporating barrier atoms into a gate dielectric using gas cluster ion beam implantation
US6130123A (en) * 1998-06-30 2000-10-10 Intel Corporation Method for making a complementary metal gate electrode technology
US5998847A (en) * 1998-08-11 1999-12-07 International Business Machines Corporation Low voltage active body semiconductor device
US6160300A (en) * 1999-01-26 2000-12-12 Advanced Micro Devices, Inc. Multi-layer gate conductor having a diffusion barrier in the bottom layer
KR100316707B1 (ko) * 1999-02-05 2001-12-28 윤종용 모스 트랜지스터 및 그 제조방법
US6376323B1 (en) * 2001-04-04 2002-04-23 Advanced Micro Devices, Inc. Fabrication of gate of P-channel field effect transistor with added implantation before patterning of the gate
KR100400323B1 (ko) * 2001-11-01 2003-10-01 주식회사 하이닉스반도체 반도체 소자의 시모스(ｃｍｏｓ) 및 그의 제조 방법
JP3976577B2 (ja) * 2002-02-01 2007-09-19 エルピーダメモリ株式会社 ゲート電極の製造方法
US6667525B2 (en) * 2002-03-04 2003-12-23 Samsung Electronics Co., Ltd. Semiconductor device having hetero grain stack gate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007027500A (ja) * 2005-07-19 2007-02-01 Toshiba Corp 半導体装置およびその製造方法
US7629243B2 (en) 2005-07-19 2009-12-08 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device
US7795121B2 (en) 2005-07-19 2010-09-14 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device
JP2008135726A (ja) * 2006-10-23 2008-06-12 Interuniv Micro Electronica Centrum Vzw 主電極を含むドープされた金属を含む半導体装置
JP2009295802A (ja) * 2008-06-05 2009-12-17 Seiko Epson Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
US20040129988A1 (en) 2004-07-08
US7026218B2 (en) 2006-04-11
US6803611B2 (en) 2004-10-12
EP1435663A2 (en) 2004-07-07
EP1435663A3 (en) 2004-12-15
US20040222443A1 (en) 2004-11-11

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