JP2004207749A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, such as a microprocessor, which is provided with rapidity, low electric power, and reliability at the same time. <P>SOLUTION: The device has a main circuit (LOG) which comprises a transistor configured on a semiconductor substrate, and a substrate bias control circuit (VBC) which controls voltage imposed to the substrate. The main circuit has a switching transistor (MN1, MP1) which controls voltage imposed to the substrate. A control signal outputted from the substrate bias control circuit is inputted into a gate of the switching transistor, and the control signal is returned to the substrate bias control circuit. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having both high speed and low power.

  Currently, CMOS integrated circuits are widely used for realizing semiconductor integrated circuit devices such as microprocessors. Various types of power consumption in CMOS circuits include dynamic power consumption due to charging and discharging at the time of switching and static power consumption due to subthreshold leakage current. Of these, the dynamic power consumption consumes a large amount of power in proportion to the square of the power supply voltage VDD, so it is effective to lower the power supply voltage to reduce power consumption. Is declining.

  On the other hand, some current low-power microprocessors include a power management mechanism, provide the processor with a plurality of operation modes, and stop supplying a clock to an execution unit during standby according to the operation modes.

  By stopping the clock supply, dynamic power consumption in unnecessary execution units can be reduced as much as possible. However, static power consumption due to the sub-threshold leakage current cannot be reduced and remains.

  Since the operating speed of a CMOS circuit decreases as the power supply voltage decreases, it is necessary to lower the threshold voltage of the MOS transistor in conjunction with the lowering of the power supply voltage in order to prevent the operating speed from deteriorating. However, when the threshold voltage is lowered, the sub-threshold leakage current extremely increases. Therefore, as the power supply voltage decreases, the static power consumption due to the sub-threshold leakage current, which was not so large in the past, becomes remarkable. Was. Therefore, there is a problem in realizing a semiconductor integrated circuit device such as a microprocessor that achieves both high speed and low power.

  As a method of solving the above problem, there is a method of controlling the threshold voltage of a MOS transistor by variably setting a substrate bias as disclosed in, for example, Japanese Patent Application Laid-Open No. 6-54396.

In an active state in which high-speed operation of a CMOS circuit is required, the substrate bias is set to a power supply potential for a PMOS (P-channel MOS transistor) and to a ground potential for an NMOS (N-channel MOS transistor). On the other hand, in the standby state where the CMOS circuit does not need to operate at high speed, the substrate bias is applied to a potential higher than the power supply voltage for the PMOS and a lower potential for the NMOS (hereinafter, this operation is referred to as `` pull the substrate ''). Express).

  By pulling the substrate during standby, the threshold value of the MOS transistor forming the CMOS circuit can be increased, and static power consumption due to subthreshold leakage current can be reduced.

JP-A-6-54396

  In order to realize a semiconductor integrated circuit device such as a microprocessor that achieves both high speed and low power, the above-described substrate bias control is performed for the CMOS circuit, and the threshold voltage of the MOS transistor is set to be active when it is active. It is necessary to reduce the subthreshold leakage current by lowering the threshold voltage of the MOS transistor during standby to increase the speed, thereby reducing the subthreshold leakage current.

However, according to studies made by the inventors, the following problems remain to control the substrate bias in an actual circuit device.
(1) Ensure testability of the substrate bias control circuit.
(2) Prevent malfunction of CMOS circuit by controlling substrate bias.
(3) Minimize increase in circuit area due to substrate bias control.
(4) To prevent malfunction of the semiconductor integrated circuit device when switching the substrate bias.

  The main means presented in the present invention for solving the above problems are as follows.

  By outputting the output of the negative voltage generation circuit in the substrate bias control circuit to the pad, the circuit test was facilitated. That is, it is necessary for the negative voltage generating circuit to check whether the level of the voltage as the output signal is the set voltage, and therefore, it is convenient to provide a terminal from which the output is directly output. .

  Further, a plurality of substrate drive MOS transistors for driving the substrate bias in the active state are arranged in the main circuit for controlling the substrate bias, so that the substrate impedance is reduced. In this case, since the circuit in the main circuit operates in the active state, it is necessary to lower the impedance, fix the substrate potential, and suppress variations in the transistor threshold.

  At this time, the driving force in the active state is larger than that in the standby state, and for example, the driving force is desirably five times, ideally, ten times or more.

  Furthermore, in order to ensure the stability of the circuit when switching the substrate bias, the gate control signal for controlling the gate voltage of the substrate drive MOS transistor is returned to the substrate bias control circuit after being connected to the gate of the substrate drive MOS transistor. The gate control signal is wired so that the substrate bias control circuit can detect that the substrate bias of the main circuit is stabilized based on the potential of the returned signal.

  The semiconductor integrated circuit device includes a power-on reset circuit. The power-on reset circuit detects that the power of the main circuit is turned on, and the power-on reset circuit turns on the power of the main circuit for a predetermined time. During this time, the substrate drive MOS transistor is set in an active state in which the substrate bias is driven shallowly.

  Further, the substrate bias control circuit controls the output impedance of the gate control signal during the transition from the standby state to the active state to be larger than the impedance after completely transitioning to the active state.

  Further, the semiconductor integrated circuit device has a negative voltage generating circuit, and the substrate bias control circuit controls the output impedance of the negative voltage generating circuit in the standby state to be smaller than the output impedance of the negative voltage generating circuit in the active state. I do.

  The main circuit is composed of a plurality of cells, the power supply nets of the plurality of cells are supplied with power by a first wiring layer, and a power supply net using a second wiring layer orthogonal to the first wiring layer is provided. A switch cell is arranged at an intersection of a power supply net formed by the first wiring layer and a power supply net formed by the second wiring layer. The connection between the power supply net formed by the first wiring layer and the power supply net formed by the second wiring layer is made within the switch cell. Further, the substrate drive MOS transistor is arranged in a switch cell.

  The substrate bias supply line of the MOS transistor constituting the cell is provided by the first wiring layer in parallel with the power supply net formed by the first wiring layer, and the second wiring is formed in parallel with the power supply net formed by the second wiring layer. In the same manner as the power supply net, the substrate bias supply line of the first wiring layer and the substrate bias supply line of the second wiring layer are connected in the switch cell, and the gate voltage of the substrate driving MOS transistor is connected. Is supplied by the second wiring layer above the switch cell in parallel with the power supply net by the second wiring layer, and is connected to the gate terminal of the substrate drive MOS transistor in the switch cell.

  More specifically, the present invention provides a main circuit including at least one transistor, a substrate bias control circuit that controls a voltage applied to a substrate of the transistor, and a main circuit that controls the substrate bias control circuit. A standby control circuit that switches between at least two states, an active state in which a large sub-threshold leakage current flows through the sub-threshold leakage current, and a standby state in which the sub-threshold leakage current is small. It has a terminal for outputting a negative voltage generated by the voltage generation circuit to the outside of the device.

  At this time, the semiconductor integrated circuit device has a semiconductor chip having an output pad, a package incorporating the semiconductor chip and having external pins, using one of the output pads as a terminal, and the terminal is connected to the external pin. Not.

  In another example, a main circuit composed of at least one MOS transistor, a substrate bias control circuit for controlling a voltage applied to a substrate of the MOS transistor, and a substrate bias control circuit for controlling the main circuit to flow through the main circuit. It has a standby control circuit that switches between at least two states, an active state with a large sub-threshold leakage current and a standby state with a small sub-threshold leakage current.The active state controls the substrate bias shallowly, and the standby state deepens the substrate bias. The driving force for controlling and driving the substrate bias shallower in the active state is at least 10 times greater than the driving force for driving the substrate bias deeper in the standby state.

  At this time, when the substrate bias is deeply controlled, it is desirable that the main circuit including the transistor pulling the substrate is not operated. When the substrate is pulled, since the impedance of the substrate is high, the substrate potential is liable to change by operating the MOS transistor. Therefore, the MOS transistor may malfunction.

As a device structure, there are at least two or more substrate driving MOS transistors for driving the substrate bias shallowly in the active state at a distance of 20 μm or more,
The gate potential of the substrate drive MOS transistor is controlled by a substrate bias control circuit.

  A gate control signal for controlling the gate voltage of the substrate drive MOS transistor is returned to the substrate bias control circuit after being connected to the gate of the substrate drive MOS transistor, and the potential of the returned signal causes the substrate bias control circuit to operate the main circuit of the main circuit. It is possible to detect that the substrate bias is stabilized.

  It is desirable that the threshold voltage of the substrate drive MOS transistor is higher than the threshold voltage of the MOS transistor forming the main circuit. In addition, when an I / O circuit that interfaces with the outside is provided, the oxide film thickness of at least one MOS transistor that forms the I / O circuit is the oxide film of the MOS transistor that forms the main circuit. It is preferable that the thickness is larger than the thickness. As described above, it is desirable to increase the withstand voltage mainly in a portion to which a high voltage is applied.

The power supply circuit further includes a power-on reset circuit for detecting that the power of the main circuit is turned on, and controls the substrate drive MOS transistor to be in an active state in which the substrate bias is driven to be shallow during a certain period after the power of the main circuit is turned on.

  In another aspect of the system to which the present invention is applied, the semiconductor integrated circuit device has a first (VDDQ) and a second (VDD) power supply voltage, and the first power supply voltage has an absolute value higher than the second power supply voltage. The second power supply voltage is 2 V or less, the second power supply voltage (VDD) is supplied to the main circuit (LOG), and the first power supply voltage (VDDQ) is connected to the substrate bias control circuit (VBC). The first power supply voltage is supplied to the standby control circuit (VBCC) before the second power supply voltage, and the substrate bias control circuit operates the main circuit for a predetermined time after the second power supply voltage is supplied. Is controlled to the active state.

  Further, by controlling the output impedance of the gate control signal of the substrate drive MOS transistor during the transition from the standby state to the active state to be larger than the impedance after completely transitioning to the active state, By adjusting the transition speed of transition to the state, the inrush current in the transition process can be controlled to be small.

  Further, by controlling the output impedance of the gate control signal of the substrate drive MOS transistor during the transition from the standby state to the active state to be larger than the impedance after completely transitioning to the active state, the active state is changed from the standby state to the active state. The transition speed of the transition to the state is adjusted, the inrush current in the transition process is controlled to be small, and the complete transition to the active state can be detected by the returned signal described above.

  The amplitude of the gate control signal can be larger than the gate breakdown voltage of the substrate drive transistor.

  Further, the semiconductor integrated circuit device includes a negative voltage generating circuit, and the substrate bias control circuit controls the output impedance of the negative voltage generating circuit in the standby state to be smaller than the output impedance of the negative voltage generating circuit in the active state. be able to.

  Further, the negative voltage generation circuit has a first charge pump circuit and a second charge pump circuit, and the substrate bias control circuit generates a negative voltage using the first charge pump circuit in the standby state, and generates the negative voltage in the active state. A negative voltage is generated by using a second charge pump circuit, and a capacity of a pumping capacitor of the first charge pump circuit is smaller than a capacity of a pumping capacitor of the second charge pump circuit. 14. A semiconductor integrated circuit device according to claim 13.

A first power supply voltage that is higher than a second power supply voltage, and a second power supply voltage is 2 V or less. The main circuit is supplied with a second power supply voltage, the substrate bias control circuit and the standby control circuit are supplied with at least a first power supply voltage, and in a standby state, the substrate bias control circuit The substrate bias of the PMOS transistor is controlled to the second power supply voltage potential, and the substrate bias of the NMOS transistor is controlled to the third power supply voltage potential, (third power supply voltage) = (first power supply voltage) − (Second power supply voltage)
It may be.

  Further, the negative voltage generation circuit includes at least one charge pump circuit, a comparator, a first reference voltage circuit for generating a potential half of the second power supply voltage, a first power supply voltage and a third power supply. A second reference voltage circuit for generating an intermediate potential of the voltage, wherein the comparator compares an output voltage of the first reference voltage circuit with an output voltage of the second reference voltage generation circuit, At least one of them can be controlled to stabilize the third power supply voltage.

  The first and second reference voltage generating circuits each include a series circuit in which MOS transistors of the same conductivity type each having a substrate terminal connected to a source terminal and a gate terminal connected to a drain terminal are connected in series, A plurality of MOS transistors can be selected to operate in a saturation region. The device can also be configured to have Schmitt characteristics.

  The main circuit is composed of a plurality of cells, the power supply nets of the plurality of cells are supplied with power by a first wiring layer, and a second wiring layer perpendicular to them is used above the first wiring layer. A switch cell is arranged at the intersection of the power supply net formed by the first wiring layer and the power supply net formed by the second wiring layer, and the connection between the power supply net formed by the first wiring layer and the power supply net formed by the second wiring layer is established. The operation is performed in the switch cell, and a substrate drive MOS transistor is further arranged in the switch cell.

  The switch cell may further include a decoupling capacitor disposed between the power supply and the ground.

  Furthermore, above the power supply net formed by the second wiring layer, there is a power supply net formed by a fourth wiring layer parallel to the power supply net formed by the second wiring layer. The connection of the power supply net by the wiring layer may be performed outside the switch cell.

  Further, there is a power supply net formed by a fifth wiring layer, and the connection between the power supply net formed by the fourth wiring layer and the power supply net formed by the fifth wiring layer is performed in the switch cell. The power mesh composed of the power net formed by the net and the fifth wiring layer is rougher than the power mesh composed of the power net formed by the first wiring layer and the power net formed by the second wiring layer. The thickness of the fifth wiring layer may be larger than both the thickness of the first wiring layer and the thickness of the second wiring layer.

  The substrate bias supply line of the MOS transistor constituting the cell is provided by the first wiring layer in parallel with the power supply net by the first wiring layer, and is also provided by the second wiring layer in parallel with the power supply net by the second wiring layer. As in the case of the power supply net, the substrate bias supply line of the first wiring layer and the substrate bias supply line of the second wiring layer may be connected in the switch cell.

  A gate control signal for controlling the gate voltage of the substrate driving MOS transistor is supplied by a second wiring layer above the switch cell in parallel with the power supply net by the second wiring layer, and the gate of the substrate driving MOS transistor is provided in the switch cell. It may be connected to a terminal.

  The substrate bias supply line wired by the second wiring layer above the switch cell and the gate control signal may be arranged between the power supply nets wired by the second wiring layer above the switch cell.

  The semiconductor integrated circuit device may include a data path circuit, and a data flow direction of the data path circuit may be parallel to a power supply net formed by the first wiring layer of the plurality of cells.

  The substrate bias may be set so that the threshold value of at least one MOS transistor is high when the semiconductor integrated circuit device is selected.

  Further, in another aspect, the first pumping capacitor, the second pumping capacitor, the first and second two P-channel transistors, the first and second two N-channel transistors, and the oscillation circuit. In the charge pump circuit, when the output of the oscillation circuit is “H”, the charge of the first pumping capacitor is pumped using the first pumping capacitor, the first P-channel transistor, and the first N-channel transistor; When the output of the oscillation circuit is “L”, the charge of the second pumping capacitor is pumped by using the second pumping capacitor, the second P-channel transistor, and the second N-channel transistor.

  In another aspect, the semiconductor device includes a main circuit including a transistor formed on a semiconductor substrate (LOG), and a substrate bias control circuit (VBC) for controlling a voltage applied to the substrate, wherein the main circuit is applied to the substrate. Switch transistor (MN1, MP1) for controlling the voltage applied to the switch transistor, the control signal output from the substrate bias control circuit is input to the gate of the switch transistor, and the control signal returns to the substrate bias control circuit. It is configured.

  In addition, it is preferable in terms of layout that the switch transistor is arranged in a rectangular switch cell, the transistor is arranged in a rectangular standard cell, and one switch cell and a plurality of standard cells are arranged in a line.

  Furthermore, the wiring of the drive power supply (VSS, VDD) for driving the transistors (MN2, MP2) of the main circuit and the wiring of the substrate bias power supply (vbp, vbn) supplied from the substrate bias control circuit are connected to the switch cell and the plural It is preferable that the standard cells are longitudinally cut in the direction in which the cells are arranged.

  From the standpoint of transistor durability, it is desirable that the threshold value of the switch transistor be larger than the threshold value of the transistor.

  The switch transistor (MN1, MP1) is inserted between the drive power supply (VSS, VDD) for driving the transistor (MN2, MP2) of the main circuit and the substrate bias power supply (vbp, vbn) supplied from the substrate bias control circuit. It is desirable from the layout to be done.

  Further, the source or the drain of the transistor can be connected to the drive power supply (VSS, VDD), and the substrate potential of the transistor can be connected to the substrate bias power supply.

  After outputting the control signal (vbp, vbn), the substrate bias control circuit detects that the control signal (vbpr, vbnr) returned via the main circuit has reached a predetermined voltage, and outputs a detection signal (vbbenbr). By forming, the operation of the main circuit can be stabilized.

As described above, according to the present invention, it is possible to realize a semiconductor integrated circuit device such as a microprocessor which satisfies both the high speed and the low power satisfying the following problems.
(1) Testing of the substrate bias control circuit is easy.
(2) The malfunction of the CMOS circuit due to the substrate bias control can be prevented.
(3) Minimizing area increase by controlling substrate bias
(4) The malfunction of the semiconductor integrated circuit device when switching the substrate bias can be prevented.

  FIG. 1 shows a conceptual diagram of a semiconductor integrated circuit device 100 using the substrate bias control circuit of the present invention. VBC is a substrate bias control circuit. LOG is a main circuit controlled by the substrate bias, and is composed of a logic circuit and a memory circuit. VBCC indicates a standby control circuit for controlling the substrate bias control circuit. The I / O is an I / O circuit that interfaces with the outside of the semiconductor integrated circuit device 100. Here, the wirings between the circuit blocks which are not particularly necessary for the board control are omitted. Reference numerals 109a and 109b denote substrate drive circuits.

  There are three types of power supplies, indicated by VDDQ, VDD, and VWELL, respectively. VSS and VSSQ indicate ground potentials with respect to VDD and VDDQ, respectively. VDDQ and VSSQ are power supplies for the I / O circuit, VDD and VSS are power supplies for the main circuit, and VWELL is a power supply for the substrate bias control circuit VBC.

  As shown in FIG. 1, VDD and VSS are also supplied to the substrate bias control circuit VBC. Further, the substrate bias control circuit VBC has a built-in negative voltage generation circuit therein, and generates a negative voltage VSUB having a polarity opposite to that of VDD or VDDQ. Here, VDDQ = VWELL = 3.3 V, VDD = 1.8 V, VSUB = -1.5 V, and two types of power supply voltages are assumed.

  Reference numerals 101, 102, 103, and 104 denote pads of the semiconductor integrated circuit device 100, 102 is supplied with a 3.3 V VWELL power supply, 103 is supplied with a 1.8 V VDD power supply, and 104 is supplied with 0 V VSS (ground). Reference numeral 101 denotes a VSUB pad, which is used as a pad for outputting a negative voltage generated inside the substrate bias control circuit VBC. By monitoring the voltage of the pad 101 during the wafer test of the semiconductor integrated circuit device 100, it is possible to detect a failure of the negative voltage generation circuit in the substrate bias control circuit VBC. Normally, pads 102 to 104 are bonded to external pins of semiconductor integrated circuit device 100, but 101 is not bonded to external pins. In this way, this test method saves on external pins.

  vbbenb is a substrate bias control start signal, and vbbenbr is a substrate bias control signal. On the other hand, reset is a reset signal which is connected to the reset signal of the semiconductor integrated circuit device 100. vbp is a PMOS substrate bias line, vbn is an NMOS substrate bias line, cbp is a PMOS substrate control line, cbn is an NMOS substrate control line, cbpr is a PMOS substrate control return line, and cbnr is an NMOS substrate control return line. The board control return lines cbpr and cbnr are return signals after the cbp and cbn signals have passed through the main circuit, and the nets are the same net. That is, the drive voltages of cbp and cbn will appear in cbpr and cbnr, respectively, after a certain delay. (See FIG. 2 described below). Cbp, vbp, cbn, and vbn are connected to the substrate drive circuits 109a and 109b, respectively.

  FIG. 2 shows a method of connecting the six substrate bias control lines vbp to cbnr in the main circuit LOG. VBCR is a return cell, which internally connects the PMOS substrate control line cbp and the PMOS substrate control return line cbpr, and connects the NMOS substrate control line cbn and the NMOS substrate control return line cbnr.

  ncell indicates a standard cell. Here, all ncells are shown as CMOS inverters composed of PMOS MP2 and NMOS MN2 for simplicity. Of course, more complicated cells such as NAND gates and latches may be independently used. As shown in FIG. 2, the substrate potential of the MOS transistor constituting the ncell is connected to vbp for the PMOS and vbn for the NMOS.

  The swcell is a switch cell, and includes a substrate driving circuit (corresponding to 109a and 109b in FIG. 1) composed of a PMOS MP1 and an NMOS MN1, and decoupling capacitors CP1 and CP2. The gate of MP1 is connected to cbp, the drain is connected to VBP, and the source is connected to VDD. Therefore, when cbp is lower than VDD-Vthp (Vthp is the absolute value of the threshold voltage of MP1), MP1 turns on and vbp is driven to the VDD potential (1.8 V).

  On the other hand, the gate of MN1 is connected to cbn, the drain is connected to VBN, and the source is connected to VSS (0V). Therefore, when cbn is higher than Vthn (Vthn is the absolute value of the threshold voltage of MN1), MN1 turns on and vbn is driven to the VSS potential (0 V).

  Generally, one or more large numbers of ncells are arranged. Also, as for the swcell, one or more swcells are arranged. By increasing the number of ncells, more complicated circuits can be integrated on the main circuit LOG. Also, by increasing the number of swcells, vbp and vbn can be driven to VDD and VSS, respectively, with lower impedance when MP1 and MN1 are turned on.

  Further, independently of the decoupling capacitor built in the switch cell swcell, a decoupling capacitor can be built in the space cell. The space cell is, for example, a cell inserted into a space generated for securing a wiring area when standard cells nsell are arranged side by side. By incorporating a decoupling capacitor also in the space cell, the capacity of the decoupling capacitor of the entire chip is increased, and power supply noise can be further reduced. Since the space cell is originally a free space only for the wiring layer, there is no fear of increasing the area by inserting a capacitor here.

  MP1 and MN1 in the swcell need to have a higher threshold value than the MOS transistor in the ncell. This is because the substrate potential of the MOS transistor in ncell (connected to vbp or vbn, respectively) is independent of its source potential, but the substrate potential of MP1 and MN1 in swcell is always the same as the drain potential. This is because a substrate bias effect cannot be expected and a subthreshold leak current flows.

  For example, assuming that vbp = 3.3V, vbn = -1.5V, VDD = 1.8V, VSS = 0V for the NMOS transistors MN1 and MN2, the source potential S, drain potential D, and substrate potential B of MN2 in ncell are respectively S = 0.0V, D = 1.8V, B = -1.5V, the threshold voltage of MN2 increases due to the substrate bias effect, and the sub-threshold leakage current decreases. However, the source potential S, drain potential D, and substrate potential B of MN1 in the swcell are S = 0.0V, D = -1.5VV, B = -1.5V, respectively. It doesn't show up. Therefore, a large sub-threshold leak current flows through MN1 between VSS and vbn.

  To increase the threshold voltage of MP1 and MN1 in the swcell compared to the MOS transistor in the ncell, change the implantation amount, change the gate length (L) size, or change the gate oxide film thickness. Can be realized. Although this method is not particularly limited, it is realized here by changing the L size and the gate oxide film thickness. With this method, a high-voltage MOS transistor used for a circuit of an input / output portion with the outside of the microcomputer (hereinafter, referred to as an I / O circuit) can be diverted.

  FIG. 3 shows an embodiment of the I / O circuit. Here, only one bit is shown. The input / output circuit performs signals inside and outside the chip via an input / output terminal PAD. When SEL is 'L', PAD is an input terminal, and when SEL is 'H', it is an output terminal. LC1 is a level conversion circuit that converts a signal having a VDD amplitude into a signal having a large amplitude of VDDQ. Therefore, the transistor between the level conversion cell LC1 and the input / output terminal PAD is constituted by a thick oxide transistor driven by VDDQ. Here, when the pull-up needs to be pulled up, it is set to “L” and pulled up by the PMOS pull-up transistor. This PMOS is also composed of a thick oxide film transistor.

  On the input side, a signal having an amplitude of VDDQ input from the outside is converted into an amplitude of VDD by an inverter composed of 110P and 110N. Therefore, since these two transistors handle signals before level conversion, they are constituted by thick oxide film transistors. The resistor 111R, the diodes 111D1, 111D2, and the transistor 111 are an input protection circuit. Note that the diodes 111D1 and 111D2 may be configured by MOS transistors. The transistors in this input protection circuit are constituted by thick oxide film transistors.

  Since the thick oxide film transistor described above does not require a very high switching speed and handles a higher voltage than VDD, the threshold voltage can be set higher. Can be higher than transistors used in ncells. Thereby, the sub-threshold leakage current of these thick oxide film transistors when they are off can be suppressed to a small value. This thick oxide film transistor can be used for MP1 and MN1 constituting the switch cell swsell of FIG. In this way, there is no need to newly complicate the process for MP1 and MN1.

FIG. 4 shows the internal configuration of the substrate bias control circuit VBC. The VBC80 is supplied with VDD and VSS as power supplies, the VBC30 is supplied with VWELL and VSS, the VBC85 is supplied with VDD and VSUB, and the VSUBGEN is supplied with VWELL, VDD and VSS, respectively.
Therefore, the power supply voltage applied to the internal circuits of VBC30, VBC85, and VSUBGEN is at most 3.3V. By setting VDDQ = VWELL in this way, since the power supplied to the I / O circuit is 3.3 V at VDDQ and VSSQ, it is used for the device used for the I / O circuit and the substrate bias control circuit. Devices can be shared.

  On the other hand, the power supply of VBC80 is 1.8V. Therefore, the signal lines from VBC80 to VBC30 and VBC85 use dual rail signals (balanced signals used in pairs that use positive logic signals and negative logic signals), and perform level conversion inside the VBC30 and VBC85. (Converted to V amplitude signal).

  VBC80 is an interface circuit block between the input signals cbpr, cbnr, vbbenb, reset and VBC30, VBC85 from the outside of the substrate bias control circuit VBC, VBC30 is a circuit block for controlling the substrate bias of PMOS, and VBC85 is a substrate bias of NMOS. VSUBGEN is a negative voltage generation circuit block.

  FIG. 5 shows an example of an operation waveform. After the power supply VDDQ for the power supply I / O circuit and the power supply VWELL for the substrate bias control circuit VBC are turned on, the power supply VDD for the main circuit is turned on. As a result, the negative voltage generation circuit block VSUBGEN is activated, and the negative voltage VSUB is generated. On the other hand, when the power supply VDD is turned on, the d_reset signal is asserted for a certain time. When this signal is asserted, the substrate bias control circuit does not subtract the substrate bias of the main circuit. (Hereinafter, subtracting the substrate or substrate bias means that the substrate bias is set to the VDD potential for PMOS and the substrate bias is set for NMOS. Substrate or substrate bias is subtracted by setting the substrate bias of a PMOS to a potential higher than the VDD potential, and setting the substrate bias of an NMOS to a potential lower than the VSS potential. State), that is, the active state.

  In this state, the PMOS substrate bias line vbp = 1.8V, the NMOS substrate bias line vbn = 0V, the PMOS substrate control line cbp = 0V, and the NMOS substrate control line cbn = 1.8V. Since the board control return lines cbpr and cbnr are return signals of cbp and cbn signals, cbpr = cbp = 0V and cbnr = cbn = 1.8V.

  When the d_reset signal is negated a predetermined time after the power supply VDD is turned on, the substrate bias is controlled by the vbbenb signal. When vbbenb is 3.3V, the state transits to the standby state where the substrate is pulled, and when vbbenb is 0V, the state transits to the active state where the substrate is not pulled.

  That is, when vbbenb changes from 0V to 3.3V, it changes to vbp = cbp = 3.3V and vbn = cbn = -1.5V. After that, the state transits to cbpr = cbp = 3.3V and cbnr = cbn = -1.5V. vbbenbr becomes 3.3V when cbpr = 3.3V and cbnr = 0V. Therefore, when vbbenb transitions from 0 V to 3.3 V, the voltage becomes 3.3 V after a certain time has elapsed (after the return signals cbpr and cbnr of cbp or cbn have returned).

  When vbbenb transitions from 3.3V to 0V, it transits to vbp = 1.8V, cbp = 0V, vbn = 0V, cbn = 1.8V. After a lapse of a certain period of time, the state transits to cbpr = cbp = 0V, cbnr = cbn = 1.8V, and vbbenbr = 0V. Thus, vbbenbr acts as a return signal for vbbenb. Further, since the substrate potential is determined by the cbp and cbn potentials as described with reference to FIG. 2, monitoring the vbbenbr obtained from the cbp and cbn potentials can be equivalent to detecting the potential state of the substrate.

  FIG. 6 shows another example of the operation waveform. Only parts different from FIG. 5 are shown. When cbp and cbn are controlled as shown in FIG. 6, the control circuit becomes slightly complicated, but the voltage applied to the source and gate terminals of MP1 and MN2 in FIG. Can drive vbp and vbn. In this case, the amplitudes of cbp and cbn corresponding to the gate control signals are larger than the gate breakdown voltages of the substrate drive transistors MP1 and MN1. However, as can be seen from Fig. 6, by slowly changing cbp and cbn, the voltage between the gate terminal and drain terminal and the gate terminal and source terminal of MP1 and MN1 becomes 3.3V at most, and must be kept below the gate withstand voltage. Can be.

  The following is a detailed circuit diagram example of each circuit block. For the sake of simplicity, the following example of each circuit block shows a circuit example that realizes the waveform of FIG.

  FIG. 7 is a circuit diagram of the VBC80. Reference numeral 120 denotes a two-input NAND, 121 denotes a two-input AND having Schmitt characteristics, 122 denotes an inverter, 123 denotes NOR, 124 denotes a buffer having Schmitt characteristics, and 125 denotes a buffer having a differential output. 126 is a power-on reset circuit whose output 127 is gradually charged from 0 V to 1.8 V after the power supply VDD is turned on. Therefore, the output of 121 outputs 0V for a fixed time, and outputs 1.8V after a certain time. This output causes the d_reset signal to be asserted for a certain time when the power supply VDD is turned on as shown in FIG. In FIG. 7, the power-on reset circuit 126 uses a simple circuit composed of a resistor and a capacitor, but another circuit system may be used. In short, any device can be used as long as it can detect until the power supply VDD is stabilized.

  d_vbbenb, d_cbpr, and d_cbnr are signals obtained by converting vbbenb, cbpr, and cbnr into dual rails, respectively. During the power-on reset period, the substrate control state is set to the active state. d_vbbenbr is a dual rail signal for making vbbenbr of FIG. 5, and is made from cbpr and cbnr.

  FIG. 8 is a circuit diagram of the VBC 30. Reference numeral 130 denotes a level conversion circuit which generates a 3.3V amplitude signal 133 from VWELL to VSS from a dual rail signal of d_vbbenb and d_reset from 1.8V amplitude from VDD to VSS. 133 becomes 'L' during the active state or the power-on reset period.

  A level conversion circuit 131 also generates a 3.3V amplitude signal 134 from VWELL to VSS from a dual rail signal d_cbpr and d_reset of 1.8V amplitude from VDD to VSS. 134 becomes 0 V when cbpr is 0 V or during the power-on reset period. When 133 becomes 0V, vbp becomes a high impedance state, cbp becomes 0V, and cbpenbr becomes 0V. When cbp becomes 0V, MP1 in all the swcells in the main circuit is turned on, and vbp is driven to 1.8V.

  A level conversion circuit 132 outputs the d_vbbenbr signal from the VBC 80 described in FIG. 7 as a 3.3 V amplitude vbbenbr signal.

  FIG. 9 shows the state of the transition of cbp. The output impedance of cbp changes in two stages. cbp is driven by an inverter 135 controlled by a 133 signal. When 133 is 0 V and 134 is 0 V, the NMOS 136 is turned on and driven by the NMOS. Here, the gate width of the NMOS 136 is set sufficiently larger than the gate width of the NMOS in the inverter 135. The state transits to the active state. When 133 becomes 0V, the inverter 135 drives cbp to 0V. However, cbp is wired throughout the main circuit, and its load capacity is large. This results in cbp being slowly driven to 0V. The transition is detected by the transition of the return signal cbpr of cbp, and the d_cbpr signal changes. As a result, 134 becomes 0V, and the NMOS 136 turns on. This drives cbp to 0V with low impedance. Thus, in the active state, cbp is driven to low impedance, and the influence of noise due to the operation of the main circuit can be reduced. When cbp is driven to 0V, MP1 in all swcells in the main circuit is turned on.However, driving cbp to 0V slowly as shown in FIG. MP1 simultaneous switching noise can be reduced.

  FIG. 10 is a circuit diagram of the VBC85. Reference numeral 140 denotes a level conversion circuit which generates a signal 142 having a 3.3V amplitude from VDD to VSUB from a dual rail signal having a 1.8V amplitude from VDD to VSS of d_vbbenb and d_reset. 142 becomes 1.8 V during the active state or the power-on reset period.

  A level conversion circuit 141 also generates a 3.3V amplitude signal 143 from VDD to VSUB from a 1.8V amplitude dual rail signal from VDD to VSS of d_cbnr and d_reset. 143 becomes 1.8 V when cbnr is 1.8 V or during the power-on reset period. When 142 becomes 1.8V, vbn becomes a high impedance state, and cbn becomes 1.8V. When cbn becomes 1.8V, MN1 in all the swcells in the main circuit is turned on, and vbn is driven to 0V.

FIG. 11 shows the state of the transition of cbn, but the output impedance of cbn changes in two stages as in the case of cbp. The cbn is driven by the inverter 144 controlled by the signal 143. When the voltage 142 is 1.8V and the voltage 143 is 1.8V, the PMOS 145 is turned on and driven by the PMOS 145. Here, the gate width of the PMOS 145 is made sufficiently larger than the gate width of the PMOS in the inverter 144. The state transits to the active state, and when 142 becomes 1.8V, cbn is driven to 0V by the inverter 144. However, cbn is wired throughout the main circuit, and its load capacity is large. From this, cbn is slowly driven to 0V. The transition is detected by the transition of the return signal cbnr of cbn, and the d_cbnr signal changes. As a result, 143 becomes 1.8V, and the PMOS 145 is turned on. This drives cbn to 1.8V with low impedance. In this manner, in the active state, cbn is driven to have a low impedance like cbp, and the influence of noise due to the operation of the main circuit can be reduced. When cbn is driven to 1.8V, MN1 in all the swcells in the main circuit is turned on.However, by driving cbn to 1.8V slowly as shown in FIG. Can reduce simultaneous switching noise.

  As is clear from the above description, in the substrate bias control method of the present invention, the driving impedance of the substrate is such that the active state where the substrate is not pulled (substrate driving by all swcells) is in the standby state where the substrate is pulled (the substrate is Drive). Therefore, as described above, by transitioning to the active state in which the substrate is not pulled when the power is turned on, it is possible to avoid the problem of an increase in the through-current between power sources and the latch-up problem when the power is turned on due to the unstable substrate potential. In addition, when active, the main circuit operates and a lot of substrate noise is generated. However, by lowering the driving impedance of the substrate, the substrate noise can be reduced, and malfunction and latch-up of the main circuit can be prevented. .

  FIG. 12 shows the internal configuration of the negative voltage generation circuit VSUBGEN. VSUBSEN is a substrate bias sense circuit, PMP1 is a charge pump circuit 1, and PMP2 is a charge pump circuit 2. The substrate bias sense circuit VSUBSEN monitors the VSUB potential, and also monitors the active and standby states with the vbpenb signal, and controls PMP1 and PMP2 using the control signals pmp1enb and pmp2enb so as to satisfy VSUB = VDD + VSS-VWELL I do.

  PMP1 operates when the pmp1enb signal is asserted, and PMP2 operates when pmp2enb is asserted. The difference between PMP1 and PMP2 is the difference in pumping ability, and PMP1 has a larger pumping ability than PMP2. Whether to use PMP1 or PMP2 is determined by the vbpenb signal. PMP2 is used in the active state, and PMP1 is used in the standby state.

  In the active state, the VSUB potential is used only in the substrate bias control circuit VBC, so that current does not flow much to VSUB. For this reason, PMP2 having a small pumping ability is used. In the standby state, the VSUB potential is supplied to the entire main circuit, so that a current such as a junction current flows through VSUB. For this reason, PMP1 having a large pumping ability is used.

  FIG. 13 shows a circuit diagram of the charge pump circuit 1 PMP1 of the present invention. OSC is a ring oscillator that oscillates only when pmp1enb is asserted and charges VSUB to a negative voltage.

  Figure 14 shows the addition of PMOS 162 and 163 to the charge pump circuit described in Kiyoo Ito, "Super LSI Memory", Baifukan, p266.One cycle period of the ring oscillator using 160, 161 PMOS. This is a charge pump circuit that performs charge pump twice. In the present invention, NMOSs 164 and 165 are further added as shown in FIG. This eliminates the influence of the threshold values of the PMOSs 160 and 161 and provides a sufficiently deep VSUB even at low voltage operation. When VWELL is 3.3V, in the configuration of FIG. 14, only VSUB = -3.3 + vthp (vthp = absolute value of threshold of PMOS 160, 161) can be obtained, and at most VSUB = -2.3V On the other hand, in the method of the present invention, it is possible to obtain up to about VSUB = -3.3V.

  Although a circuit diagram of the charge pump circuit 2 PMP2 is not particularly shown here, the capacitance of the capacitor may be reduced by reducing the PMOS CP3, CP4 used as a capacitor in FIG. Of course, the size of the other MOSs may be optimized according to CP3 or CP4.

FIG. 15 shows a circuit diagram of the substrate bias sense circuit VSUBSEN. VREFGEN is a reference voltage generation circuit, and obtains an output of VREF = (VDD-VSS) / 2 by serially connecting NMOSs denoted by 150 and 151. V1GEN is a VSUB potential sense circuit, and obtains an output of V1 = (VWELL-VSUB) / 2 by serially connecting NMOSs 152 to 155. Only a potential difference of about 1 V is applied between the source and the drain of each NMOS, and the gate length is further increased. As a result, the through current from VDD to VSS or VWELL to VSUB can be reduced. Further, since the operation is performed in the saturation region, VREF or V1 can be obtained insensitively to variation. Further, in the present invention, an NMOS is used instead of a PMOS. Since the NMOS has better saturation characteristics than the PMOS, VREF or V1 can be obtained more insensitively to the variation between NMOSs without applying a potential of about 1 V between the source and the drain.
AMP1, AMP2, and AMP3 are differential amplifiers, respectively, and constitute one differential amplifier. VREF and V1 are input to the differential amplifier composed of AMP1, AMP2, and AMP3. When VREF <V1, pmp1enb or pmp2enb is asserted. As a result, VSUB is charged in the negative voltage direction. When VREF> V1, pmp1enb or pmp2enb is negated. Since VSUB has some leakage current in the VSS, VWELL, and VDD directions, if both pmp1enb and pmp2enb are negated, VSUB is discharged in the positive potential direction. By repeating the assertion / negation of pmp1enb or pmp2enb, V1 = VREF, that is, VSUB = VDD-VSS-VWELL is maintained. As described above, pmp1enb is asserted when vbpenb is 3.3 V (during a standby state), and pmp2enb is asserted when vbpenb is 0 V (during an active state).

  Also, there is a feedback path between AMP1 and AMP2, and the differential amplifier composed of AMP1, AMP2, and AMP3 has hysteresis characteristics. The hysteresis characteristic here means that the differential point of the differential amplifier changes according to the output of the amplifier, that is, has a so-called Schmitt characteristic. This prevents excessive pmp1enb or pmp2enb from repeatedly asserting and negating near V1 = VREF, thereby preventing an increase in power consumption.

  Furthermore, the operating current of the differential amplifier from AMP1 to AMP3 is changed when vbpenb is asserted and negated. During standby when vbp is asserted, VSUB is connected to vbn of the main circuit, so that a large substrate capacity is connected. Therefore, VSUB changes slowly. Since AMP1 to AMP3 do not need to operate at high speed, the operating current can be limited. Thereby, the power consumption of AMP1 to AMP3 can be reduced. On the other hand, when vbp is negated and active, only the substrate bias control circuit VBC is connected to VSUB, so that a relatively small capacitance is connected to VSUB. Therefore, VSUB changes quickly, and AMP1 to AMP3 need to operate at high speed. In addition, when active, the power consumption is not so noticeable. For this reason, the operating current of AMP1 to AMP3 is increased to operate at high speed.

  Hereinafter, a more detailed embodiment of the substrate bias feeding method will be described.

FIG. 16 shows a layout example of the ncell and the swcell. The swcell is arranged continuously in the vertical direction (Y direction). In addition, the cell heights of the swcell and the ncell are unified to the same height, and the interval L in the horizontal direction (X direction) between the swcell and the swcell is made variable within a certain value. Of course, the intervals may be fixed, but the degree of freedom increases to some extent if they are made variable. In any case, the interval L may be determined in consideration of the following items.
(1) Power line impedance
(2) Power wiring migration
(3) Substrate noise generated in vbp or vbn by operation of ncell FIG. 17 shows a layout example of ncell. As in the case of FIG. 2, an inverter is taken as an example. vbp, vbn, VDD, and VSS are supplied by four parallel first-layer metal wirings (hereinafter referred to as M1). vbp and vbn are each also supplied by the surface high concentration layer. H is a cell height, which indicates a basic repeating unit in the vertical direction. The mirrors are arranged vertically mirror-symmetrically with respect to this height. Thereby, vbp and vbn can be shared with the upper and lower adjacent ncells, and the area can be reduced.

  FIG. 18 is a cross-sectional view taken along line AB in FIG. N-well is an N-type well for forming MP2, and P-well is a P-type well for forming MN2. Deep-N is an N-type well located deeper than N-well and P-well, and has a so-called triple well structure.

  FIG. 19 shows a layout example of the swcell. The height of the cell is H as in the case of ncell, and the power supply lines for vbp, vbn, VDD, and VSS by M1 are at the same position as ncell. As shown in FIG. 16, swcells are continuous in the vertical direction, and are arranged at intervals within a certain interval in the horizontal direction. With such an arrangement, the power supply reinforcement line can be arranged at the location of the swcell. In FIG. 19, the second layer metal wiring (hereinafter, referred to as M2) wired in parallel in the vertical direction is the two power supply reinforcing wires. Two vbp and vbn reinforcing lines and two cbp and cbn lines are arranged in parallel between the two power supply reinforcing lines. The power supply enhancement lines VDD and VSS at both ends can protect four substrate bias control lines having relatively high impedance from external noise.

  MP1 is formed by being divided into six transistors, and its gate is connected to cbp, its drain is connected to vbp, and its source is connected to VDD. MN1 is formed by being divided into three transistors, the gate of which is connected to cbn, the drain of which is connected to vbn, and the source of which is connected to VSS. Each of the decoupling capacitors CP1 and CP2 is separated into two transistors and formed at both ends of MP1 and MN1, and a capacitance is formed using a MOS gate capacitance.

  The ratio between the size of the decoupling capacitors CP1 and CP2 and the size of MP1 and MN1 is not particularly limited. In an extreme case, one or both of the decoupling capacitors CP1 and CP2 may be omitted. Power supply noise can be reduced by increasing the size of the decoupling capacitor. On the other hand, if MP1 and MN1 are increased, when the microcomputer is in the normal state, the substrate bias can be connected to the power supply with a lower impedance, the resistance against noise is increased, and the latch-up hardly occurs.

  The VIA hole between the VDD line of M1 and the VDD line of M2 and the VIA hole between the VSS line of M1 and the VSS line of M2 are omitted for simplicity. A hole may be provided.

  FIG. 20 shows a cross-sectional view taken along line AB in FIG. As in FIG. 18, P-well is a P-type well for forming MN1, Deep-N is an N-type well located deeper than the P-well, and has a so-called triple well structure. . Here, a VIA hole between the VSS line of M1 and the VSS line of M2 omitted in FIG. 19 is also illustrated. As described in the description of FIG. 2, a thick oxide film transistor is used for MN2 to increase the threshold value.

  FIG. 21 shows a more specific example of a wiring method of the power supply lines VDD and VSS and the substrate bias control lines vbp, vbn, cbp, and cbn. This figure is obtained by adding the above wiring to FIG. In the horizontal direction, VDD, VSS, vbp, and vbn wired by M1 are wired in parallel. As described with reference to FIG. 17, vbp is shared by the upper and lower cells, and VDD is wired above and below it in parallel. Also, vbn is shared by the upper and lower cells, and VSS is wired above and below it in parallel. Of course, it is better to make VDD and VSS thicker than vbp and vbn.

  As described in FIG. 19, VDD, VSS, vbp, vbn, cbp, cbn wired in M2 in the vertical direction are wired on the swcell, and at the intersection of M1 and M2, VDD, VSS, vbp , Vbn are connected in a mesh.

  FIG. 22 shows how the power supplies VDD and VSS are reinforced. Power supply lines VDD and VSS formed of a fourth metal wiring layer (hereinafter, referred to as M4) and a fifth metal wiring layer (hereinafter, referred to as M5) are further wired in the basic repeating unit of FIG.

  Although VDD and VSS wired by M4 are wired above the VDD and VSS of M2 wired in the vertical direction, the third metal wiring layer (hereinafter referred to as M3) is necessary. If this connection is made on all the swcells, M3 is wired in the vertical direction, and there is a problem that the horizontal path of M3 is lost.

  In FIG. 22, the power supply lines of M2 and M4 are connected only on every three swcells indicated by swcell2 or swcell3. By doing so, a wiring path in the horizontal direction of M3 can be secured.

  The power supply line of M5 is provided only on every sixth swcell indicated by swcell3, and is connected at the intersection with the power supply line of M4 on swcell3.

  As described above, the impedance of the power supply lines VDD and VSS can be reduced by reinforcing the power supply mesh of the fine pitch of M1 and M2 with the power supply mesh of the coarse pitch of M4 and M5.

  In FIG. 22, the power supply lines in the vertical direction of M4 are wired on all the swcells, but may be coarsely wired in every two or three in the horizontal direction. Although the impedance of the power supply line increases, a vertical path of M4 can be secured.

  FIG. 23 shows the relationship between the arrangement of the swcell shown in FIG. 22 and the wells. P-type wells P-wells and N-type wells are alternately arranged in a strip shape, and two ncells are arranged so as to share one well.

FIG. 24 shows a layout example of the swcell and the power supply line of the memory circuit. Although word lines and bit lines are not shown here, word lines are arranged in the horizontal direction and bit lines are arranged in the vertical direction. The power lines of the memory mat run in the memory cell in the horizontal direction, but they are reinforced by power lines 200, 201, and 202 at both ends of the memory mat. 203 denotes a power supply line for supplying power to each word driver and word decoder, and 204 denotes a power supply line for supplying power to each sense amplifier. The swcell is arranged on the power supply lines from 200 to 204 as shown in FIG.
Normally, only one or two of a plurality of word drivers and word decoders operate simultaneously. Therefore, since the amount of substrate noise is not so large, only two swcells are arranged at both ends of 203 as shown in the figure.

  Conversely, many sense amplifiers operate simultaneously. However, the number of nodes transitioning from 'L' to 'H' and the number of nodes transitioning from 'H' to 'L' are almost the same as the potential inside the sense amplifier. Therefore, even if many sense amplifiers operate at the same time, the substrate noise does not increase so much. Here, as shown in the figure, swcells are arranged at positions other than both ends of the power supply line 204 to reduce substrate noise.

  In addition, various methods of arranging swcells are conceivable, but as the ratio of devices operating in the same well increases, more swcells may be arranged in the well. In a diffusion layer in one well, the potential change of the diffusion layer is expressed as | NH-NL | / NA (NH = area of the diffusion layer excluding the diffusion layer connected to the power supply, NH = potential of 'H The area of the diffusion layer that changes from 'L' to 'L', NL = the area of the diffusion layer where the potential changes from 'L' to 'H'), and the number of swcells, the interval L of the swcell, and The size of the MOS transistor in the swcell may be determined. The point is that the value of | NH-NL | / NA should be as small as possible.

  For example, in the case of a circuit having a regular data flow such as a data path, the data flow direction of the data path may be set to the X direction in FIG. | NH-NL | / NA is reduced because simultaneously operating cells are dispersed in a plurality of wells.

  FIG. 25 is a sectional view of the semiconductor integrated circuit device 100 of the present invention. As shown in FIG. 18, N indicated by 302, 304, 306, 308, 310 is the same as the N-well, and is an N-type well for forming a PMOS transistor, 301, 303, 305, 307, 309, 311. P indicated by is the same as the P-well and is a P-type well for forming an NMOS transistor. Deep-N indicated by 312 and 313 is an N-type well located deeper than N and P, and has a so-called triple well structure.

  Deep-N 312 and 313 are electrically separated by 310 p-substrates and 307 P-wells. Therefore, the substrate potential of the MOS transistor A formed on 302, 304, 306, 308, 310 is independent of the substrate potential of the MOS transistor B formed on 301, 303, 305, 307, 309, 311. An electric potential can be applied. Further, it is possible to reduce the influence of noise or the like generated in the MOS transistor A on the MOS transistor B.

  FIG. 26 shows the structure of Deep-N of the semiconductor integrated circuit device of the present invention. CPG is a clock control unit and includes an analog circuit such as a PLL (Phase Locked Loop). TLB indicates an address conversion unit, CACHE indicates a cache memory, CPU indicates a central processing unit, FPU indicates a floating point arithmetic unit, LOG1 indicates random logic 1, LOG2 indicates random logic 2, and PAD indicates an I / O unit. Thus, each circuit block is formed on a different Deep-N.

  As described with reference to FIG. 25, it is possible to reduce the influence of noise generated in each circuit block on other blocks. For example, a PAD generates large noise because it drives an external pin with a larger amplitude than the internal signal amplitude. This noise can be prevented from affecting an analog circuit such as a CPG.

  Further, since the substrate potentials can be given independently of each other, for example, a circuit that does not perform substrate control by vbp, vbn, cbp, and cbn can be arranged in LOG2. That is, a circuit in which the power supply and the substrate potential are connected (VDD = vbp, VSS = vbn) can be arranged.

  FIG. 27 shows a guard band arranged between Deep-N and Deep-N. As shown in FIG. 27, a guard band gband1 is arranged between Deep-N and Deep-N.

  FIG. 28 shows a cross-sectional view. The P well 307 between Deep-N is grounded to the VSS potential through the P + diffusion layer 314. Noise propagation between Deep-N can be further reduced. For example, the substrate noise generated by the MOS on the P-well 305 propagates as noise to the Deep-N 312 by capacitive coupling because the impedance of the Deep-N 312 is not so low. This noise also attempts to propagate to the p-substrate 300 by capacitive coupling, but the p-substrate is fixed to the ground potential at low impedance by a guard band. Therefore, noise appearing on the p-substrate is reduced. In this way, the propagation of noise from the MOS transistors formed on 302, 304, 306, 308, 310 to the MOS transistors formed on 301, 303, 305, 307, 309, 311 is reduced. You.

  FIG. 29 shows a layout image of cbp and cbpr on a semiconductor integrated circuit and the position of the return cell VBCR in FIG. Since cbn and cbnr can be similarly performed, they are omitted here. As shown in FIG. 21, vbp and vbn are wired in a mesh by arranging swcells, but cbp and cbn are not wired in a mesh, but are wired in a stripe. FIG. 29 shows a state in which stripe-shaped wirings arranged by arranging swcells are connected so as to shunt. Also, the return cell is a cell for returning the input cbp and cbn to the substrate bias control circuit VBC as cbpr and cbnr, and the return timing is within each swcell, and the return timing is based on the slowest swcell cbp arrival timing of the cbp propagation time. Is arranged so that cbpr can return at a later timing. For example, it may be arranged at a position farthest from the substrate bias control circuit VBC.

  In the above embodiment, the potential applied to the substrate bias is 1.8 V and 0.0 V during active, and 3.3 V and -1.5 V during standby, but is not particularly limited. When active, an appropriate potential may be applied to the substrate bias so that the variation in the threshold value of the MOS transistor can be adjusted.

  In addition, the main circuit may be divided into a plurality of circuit blocks, and control circuits such as VBC30 and VBC85 may be individually provided in each circuit block, and the active state and the standby state may be independently provided. If control is performed for each circuit block, a circuit block that is not operating can be placed in a standby state, and power consumption can be more finely controlled and power consumption can be reduced. In some circuit blocks, it is not necessary to apply a substrate bias even in the standby state. This is the case, for example, when the circuit block is composed of MOS transistors with a high threshold value and the sub-threshold leakage current can be ignored.

  In the above embodiment, the threshold value of the MOS transistor is set to a low threshold value when the operation mode of the circuit is active and to a high threshold value when the circuit is in the standby mode. Pp. 71, 1996 (1996 IEEE SPECTRUM, pp. 66-71), the substrate bias may be set so as to have a high threshold during the IDDQ test.

At this time, it is desirable that the substrate potential applied to the substrate during the IDDQ test is higher than the substrate potential applied during standby. That is, a higher potential is applied to the PMOSFET than in the standby state, and a lower potential is applied to the NMOSFET.
By doing so, the sub-threshold leakage current flowing during the IDDQ test can be further reduced, so that the accuracy of failure detection is improved.

  To enable such an operation, the VWELL potential is increased from, for example, 3.3 V to 4.0 V during the IDDQ test, and the VSUB potential is decreased from -1.5 V to -2.2 V. In terms of a circuit, it is necessary to prevent a through current from flowing even if the VWELL potential is different from the VDDQ potential. For this purpose, for example, all signals to the substrate bias control circuit VBC are used after being leveled down by the VBC 80 and then converted to the VWELL potential or the VSUB potential. This can be realized by providing a voltage buffer.

  In the above embodiments, the substrate structure is assumed to have a triple well structure, but the structure is not particularly limited. It may have a double well structure with a so-called twin tub structure or an SOI (Silicon on insulator) structure.

  Further, as shown in FIGS. 17, 19, and 21, in the present invention, the substrate bias in the cell is supplied by M1, but the structure is not particularly limited. See, for example, 1997 Symposium on VLSI circuits Digest of Technical Papers, pp. 95-96, pages 95-96, 1997 Symposium on VLSI Circuits Digest of Technical Papers, pp. 95-96. As described above, power may be supplied by a diffusion layer or a silicified diffusion layer.

FIG. 1 is a block diagram of a semiconductor integrated circuit device according to the present invention. FIG. 3 is a circuit diagram illustrating the contents of a main circuit in more detail. FIG. 2 is a circuit diagram of an I / O circuit. FIG. 3 is a circuit block diagram of a substrate bias control circuit. FIG. 4 is a diagram illustrating operation waveforms of a substrate bias control circuit. FIG. 6 is a waveform chart showing an operation waveform of the substrate bias control circuit according to another embodiment different from FIG. 5. Circuit diagram of VBC80. Circuit diagram of VBC30. FIG. 4 is an operation waveform diagram of VBC30. Circuit diagram of VBC85. FIG. 4 is an operation waveform diagram of VBC85. The block diagram of each circuit of VSUBGEN. FIG. 2 is a circuit diagram of a charge pump. FIG. 2 is a circuit diagram of a charge pump. VSUBSEN circuit diagram. FIG. 3 is a layout diagram of the switch cell of the present invention. Layout diagram of a standard cell. FIG. 18 is a sectional view of FIG. 17. FIG. 3 is a layout diagram of a switch cell. FIG. 20 is a sectional view of FIG. 19; Power supply wiring and wiring diagrams of vbp, vbn, cbp, cbn. The wiring diagram of a power supply reinforcement line. FIG. FIG. 3 is a layout diagram of switch cells in a memory circuit. Sectional drawing of a well. Layout diagram of Deep-N well. Layout diagram of Deep-N well and guard band. FIG. 28 is a sectional view of FIG. 27; Layout diagram of cbpr, cbnr, and VBCR.

Explanation of reference numerals

VBC: substrate bias control circuit, LOG: main circuit, VBCC: standby control circuit, I / O: I / O circuit, vbbenb: substrate bias control start signal, vbbenbr: substrate bias control signal, vbp …… PMOS substrate bias line, vbn …… NMOS substrate bias line, cbp …… PMOS substrate control line, cbn …… NMOS substrate control line, cbpr …… PMOS substrate control return line, cbnr …… NMOS substrate control return line, AMP1 , AMP2 ... Differential amplifier, AMP3 ... Schmitt input differential amplifier, VBCR ... Return cell, swcell ... Switch cell, ncell ... Standard cell, P-sub ... P substrate, PLL ... Phase locked Loop, CPG: Clock control unit, TLB: Address conversion unit, CACHE: Cache memory, CPU: Central processing unit, FPU: Floating point arithmetic unit, PAD: I / O unit

Claims (35)

A main circuit composed of at least one transistor;
A substrate bias control circuit that controls a voltage applied to the substrate of the transistor;
By controlling the substrate bias control circuit, having a standby control circuit that switches to at least two states of an active state in which the sub-threshold leakage current flowing through the main circuit is large and a standby state in which the sub-threshold leakage current is small,
A semiconductor integrated circuit device having a built-in negative voltage generating circuit in the substrate bias control circuit and having a terminal for outputting a negative voltage generated by the negative voltage generating circuit to the outside of the device.   The semiconductor integrated circuit device includes a semiconductor chip having an output pad, a package containing the semiconductor chip and having external pins, using one of the output pads as the terminal, and the terminal being connected to the external pin. 2. The semiconductor integrated circuit device according to claim 1, wherein the terminals are not connected. A main circuit composed of at least one MOS transistor;
A substrate bias control circuit for controlling a voltage applied to the substrate of the MOS transistor;
By controlling the substrate bias control circuit, there is a standby control circuit that switches to at least two states of an active state in which the sub-threshold leak current flowing through the main circuit is large and a standby state in which the sub-threshold leak current is small,
In the active state, the substrate bias is controlled shallowly, and in the standby state, the substrate bias is controlled deeply.
A semiconductor integrated circuit device, wherein a driving force for driving a substrate bias shallowly in an active state is larger than a driving force for driving a substrate bias deeply in a standby state. 4. The substrate driving MOS transistor for driving the substrate bias shallowly in the active state is at least two with a distance of 20 μm or more, and the gate potential of the substrate driving MOS transistor is controlled by the substrate bias control circuit. 13. The semiconductor integrated circuit device according to claim 1.   A gate control signal for controlling the gate voltage of the substrate drive MOS transistor is returned to the substrate bias control circuit after being connected to the gate of the substrate drive MOS transistor, and the substrate bias control circuit is controlled by the potential of the returned signal. 5. The semiconductor integrated circuit device according to claim 4, wherein said gate control signal is wired so as to detect that the substrate bias of said main circuit is stabilized.   5. The semiconductor integrated circuit device according to claim 4, wherein a threshold voltage of said substrate drive MOS transistor is higher than a threshold value of a MOS transistor forming said main circuit.   An I / O circuit for interfacing with the outside is provided, and the oxide film thickness of at least one MOS transistor forming the I / O circuit is larger than the oxide film thickness of the MOS transistor forming the main circuit. 5. The semiconductor integrated circuit device according to claim 4, wherein said semiconductor integrated circuit device is also thick.   A power-on reset circuit for detecting that the power of the main circuit is turned on, and for a certain period of time after the power of the main circuit is turned on, the substrate driving MOS transistor is in an active state in which the substrate bias is driven shallowly. 5. The semiconductor integrated circuit device according to claim 4, wherein the control is performed. The semiconductor integrated circuit device has first and second power supply voltages,
The first power supply voltage has an absolute value greater than the second power supply voltage, and the second power supply voltage is 2 V or less,
The second power supply voltage is supplied to the main circuit;
The first power supply voltage is supplied to the substrate bias control circuit and the standby control circuit;
The first power supply voltage is turned on before the second power supply voltage,
5. The semiconductor integrated circuit device according to claim 4, wherein said substrate bias control circuit controls the main circuit to be in an active state for a predetermined time after the second power supply voltage is turned on.   The transition speed of transition from the standby state to the active state by controlling the output impedance of the gate control signal in the process of transitioning from the standby state to the active state to be larger than the impedance after completely transitioning to the active state. 5. The semiconductor integrated circuit device according to claim 4, wherein the inrush current in the transition process is controlled to be small.   The transition speed of transition from the standby state to the active state by controlling the output impedance of the gate control signal in the process of transitioning from the standby state to the active state to be larger than the impedance after completely transitioning to the active state. 6. The semiconductor integrated circuit device according to claim 5, wherein the inrush current in the transition process is controlled to be small, and the complete transition to the active state is detected by the returned signal.   12. The semiconductor integrated circuit device according to claim 10, wherein an amplitude of said gate control signal is larger than a gate breakdown voltage of said substrate drive transistor. The semiconductor integrated circuit device includes a negative voltage generation circuit,
5. The semiconductor according to claim 4, wherein the substrate bias control circuit controls an output impedance of the negative voltage generation circuit in a standby state to be smaller than an output impedance of the negative voltage generation circuit in an active state. Integrated circuit device. The negative voltage generation circuit has a first charge pump circuit and a second charge pump circuit,
The substrate bias control circuit generates a negative voltage using the first charge pump circuit in a standby state, generates a negative voltage using the second charge pump circuit in an active state,
14. The semiconductor integrated circuit device according to claim 13, wherein a capacity of a pumping capacitor of the first charge pump circuit is smaller than a capacity of a pumping capacitor of the second charge pump circuit. First and second power supply voltages, wherein the negative voltage generation circuit generates a third power supply voltage;
The first power supply voltage is higher than the second power supply voltage, and the second power supply voltage is 2 V or less;
The second power supply voltage is supplied to the main circuit,
At least a first power supply voltage is supplied to the substrate bias control circuit and the standby control circuit,
In a standby state, the substrate bias control circuit controls the substrate bias of the PMOS transistor to a second power supply voltage potential, controls the substrate bias of the NMOS transistor to a third power supply voltage potential,
(Third power supply voltage) = (first power supply voltage)-(second power supply voltage)
The semiconductor integrated circuit device according to claim 13, wherein: The negative voltage generation circuit includes at least one charge pump circuit, a comparator, a first reference voltage circuit that generates a half of a second power supply voltage, a first power supply voltage, and a third power supply voltage. And a second reference voltage circuit for generating an intermediate potential of
The comparator compares an output voltage of a first reference voltage circuit with an output voltage of a second reference voltage generation circuit, and controls at least one of the charge pumps to stabilize a third power supply voltage. 16. The semiconductor integrated circuit device according to claim 15, wherein:   The first and second reference voltage generating circuits each comprise a series circuit in which MOS transistors of the same conductivity type, each having a substrate terminal connected to a source terminal and a gate terminal connected to a drain terminal, are connected in series. 17. The semiconductor integrated circuit device according to claim 16, wherein said plurality of MOS transistors are selected to operate in a saturation region.   17. The semiconductor integrated circuit device according to claim 16, having a Schmitt characteristic.   The main circuit is composed of a plurality of cells, a power supply net of the plurality of cells is supplied with power by a first wiring layer, and a second wiring layer perpendicular to them is provided above the first wiring layer. There is a power supply net used, and a switch cell is arranged at an intersection of the power supply net by the first wiring layer and the power supply net by the second wiring layer, and the power supply net by the first wiring layer and the power supply net by the second wiring layer 5. The semiconductor integrated circuit device according to claim 4, wherein the connection of the power supply net is performed in the switch cell, and the substrate drive MOS transistor is arranged in the switch cell.   20. The semiconductor integrated circuit device according to claim 19, wherein a decoupling capacitor is further arranged between the power supply and the ground in the switch cell.   Above the power supply net formed by the second wiring layer, there is a power supply net formed by a fourth wiring layer parallel to the power supply net formed by the second wiring layer. 20. The semiconductor integrated circuit device according to claim 19, wherein the connection of the power supply net by the wiring layer is performed outside the switch cell.   Further, there is a power supply net formed by a fifth wiring layer, and the connection between the power supply net formed by the fourth wiring layer and the power supply net formed by the fifth wiring layer is performed in a switch cell. The power supply mesh composed of the power supply net formed by the nets and the fifth wiring layer is rougher than the power supply mesh formed by the power supply net formed by the first wiring layer and the power supply net formed by the second wiring layer. 22. The semiconductor integrated circuit device according to claim 21, wherein the thickness of the first wiring layer and the thickness of the fifth wiring layer are larger than both the thickness of the first wiring layer and the thickness of the second wiring layer.   A substrate bias supply line of a MOS transistor constituting the cell is provided by a first wiring layer in parallel with a power supply net formed by the first wiring layer, and a second wiring is formed in parallel with the power supply net formed by the second wiring layer. 20. The semiconductor according to claim 19, wherein the switching is performed by a layer, and a substrate bias supply line formed by a first wiring layer and a substrate bias supply line formed by a second wiring layer are connected in the switch cell in the same manner as the power supply net. Integrated circuit device.   A gate control signal for controlling a gate voltage of the substrate drive MOS transistor is supplied by a second wiring layer above the switch cell in parallel with the power supply net by the second wiring layer, and the substrate drive is performed in the switch cell. 24. The semiconductor integrated circuit device according to claim 23, wherein the device is connected to a gate terminal of a MOS transistor.   The substrate bias supply line and the gate control signal, which are wired by the second wiring layer above the switch cell, are arranged between the power supply nets which are wired by the second wiring layer above the switch cell. The semiconductor integrated circuit device according to claim 24, wherein:   The semiconductor integrated circuit device includes a data path circuit, and a data flow direction of the data path circuit is parallel to a power supply net formed by a first wiring layer of the plurality of cells. 20. The semiconductor integrated circuit device according to item 19.   5. The semiconductor integrated circuit device according to claim 4, wherein said substrate bias is set such that a threshold value of at least one of said MOS transistors is high when said semiconductor integrated circuit device is selected. A first pumping capacitor, a second pumping capacitor,
First and second two P-channel transistors;
First and second two N-channel transistors;
In a charge pump circuit composed of an oscillation circuit,
When the output of the oscillation circuit is “H”, the charge of the first pumping capacitor is pumped by using a first pumping capacitor, a first P-channel transistor, and a first N-channel transistor;
When the output of the oscillation circuit is 'L', the charge of the second pumping capacitor is pumped by using a second pumping capacitor, a second P-channel transistor, and a second N-channel transistor. Charge pump circuit. A main circuit including a transistor formed on a semiconductor substrate, and a substrate bias control circuit for controlling a voltage applied to the substrate,
The main circuit has a switch transistor that controls a voltage applied to the substrate,
A semiconductor integrated circuit device, wherein a control signal output from the substrate bias control circuit is input to a gate of the switch transistor, and the control signal is configured to return to the substrate bias control circuit.   30. The semiconductor integrated circuit according to claim 29, wherein the switch transistor is arranged in a rectangular switch cell, the transistor is arranged in a rectangular standard cell, and the one switch cell and the plurality of standard cells are arranged in a line. Circuit device.   A wiring of a driving power supply for driving the transistor of the main circuit and a wiring of a substrate bias power supply supplied from the substrate bias control circuit traverse the switch cell and the plurality of standard cells in a direction in which the cells are arranged. The semiconductor integrated circuit device according to claim 30.   32. The semiconductor integrated circuit device according to claim 38, wherein a threshold value of said switch transistor is larger than a threshold value of said transistor.   33. The switch transistor according to claim 29, wherein the switch transistor is inserted between a driving power supply for driving the transistor of the main circuit and a substrate bias power supply (vbp, vbn) supplied from the substrate bias control circuit. 3. The semiconductor integrated circuit device according to 1.   34. The semiconductor integrated circuit device according to claim 33, wherein a source or a drain of the transistor is connected to the drive power supply, and a substrate potential of the transistor is connected to the substrate bias power supply. 35. The substrate bias control circuit according to claim 29, wherein after outputting the control signal, the substrate bias control circuit detects that the control signal returned via the main circuit has reached a predetermined voltage, and forms a detection signal. The semiconductor integrated circuit device according to any one of the above.

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