JP5085701B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device such as a system LSI for a portable device or a microprocessor.

  As a technique examined by the present inventor, for example, the following technique is conceivable in a semiconductor integrated circuit device such as a system LSI for a portable device or a microprocessor.

  In recent portable devices, I / O (input / output) voltages have been diversified. This is because a low voltage for obtaining lower power consumption and a conventional interface that operates at a high voltage are used in order to effectively utilize existing assets. With regard to lowering the voltage, there is a strong tendency to reduce power for the interface part of a random access memory (DRAM), which is a general-purpose storage element, and this is driving the standardization of low voltage I / O. For example, in portable devices, the interface voltage of SDRAM, DDR-SDRAM, and the like is becoming 1.8 V, which is a low voltage compared to 3.3 V, which is the current industry standard.

  On the other hand, it is also important to maintain the traditional interface. This is because a removable nonvolatile memory (such as a flash) is designed to operate at a high voltage (3.3 V), and this interface specification is also standardized in the industry. Such a conventional interface is adopted for various models with different product generations, and has an advantage of cost reduction due to mass production effect. Therefore, there is a high demand for continuing to use such conventional I / O.

  Therefore, in view of cost and low power, it is extremely difficult to unify the power sources of all I / O circuits (input / output circuits) mounted on the LSI (for example, to a voltage of 1.8 V) at this stage. difficult.

  Until now, low-voltage (1.8 V) I / Os have not required much high-speed operation. Therefore, it is possible to use a 1.8V system I / O by operating a low voltage (1.8 V) transistor on the premise that the 1.8 V system I / O is operated at a standard voltage (for example, 3.3 V). However, recent portable devices have more application functions, and the need to transfer a large amount of data at a high speed is increasing. For this reason, there is an increasing demand for high-speed operation even in low-voltage operation I / O, and in the future, it will be essential to increase the speed of 1.8V I / O.

US Pat. No. 5,969,542 JP 2003-152096 A

  By the way, as a result of examination of the above-described technique by the present inventor, the following has been clarified.

SoC (System-on-a-Chip) LSI, which is currently mainstream, has a core voltage (for example, 1.2 V) that is a supply voltage to a transistor that constitutes a logic circuit such as a CPU and an I / I for matching with an external device. On the premise of operating at an O voltage (for example, 3.3 V), the gate insulating film thickness of the MISFET is designed with two types. When designing a 1.8V I / O under such design boundary conditions, it is conceivable to operate 1.8V using the 3.3V MISFET. In this case, as is apparent from the so-called MISFET current-voltage relationship that the saturation current Ids of the MISFET is proportional to the square of the difference between the gate voltage Vg and the threshold voltage Vth (Ids∝ (Vg−Vth) ² ). There is a difference of about 6 times between the saturation current at the time of 3.3V operation and the saturation current at the time of 1.8V operation, assuming that Vth = 0.7V, and when converted to the delay time (Tpd), the delay Since the time is a quotient (Tpd≈C × V / Ids) obtained by dividing the product of the power supply voltage V and the gate capacitance C by Ids, it can be seen that the time is about three times slower. Therefore, high-speed operation at 1.8 V using a 3.3 V transistor is difficult.

  In order to increase the operation speed of 1.8V, it is conceivable to design a MISFET for 3.3V using a low threshold MISFET by adding an implantation process. When used for the entire low-power I / O circuit from the pre-buffer to the main buffer, the amount of leakage current increases, resulting in a demerit that the low-power property that is essential for portable devices is lost.

  A method of designing an I / O of 1.8 V operation using a MISFET for a logic circuit operating at 1.2 V is also conceivable. There is an example described in Patent Document 1. In this document, it is disclosed that a 2.5V I / O is configured using a 1.8V device. A withstand voltage relaxation technique that relaxes the maximum applied voltage applied to the MISFET is used. However, when such an example is applied and a 1.8V I / O circuit is constructed with a 1.2V MISFET, the threshold value of the 1.2V MISFET is generally set to a low value by the so-called scaling law. Therefore, there is a problem of an increase in leakage current. Furthermore, countermeasures against electrostatic breakdown (ESD countermeasures) must be newly implemented, which requires additional man-hours and costs.

  The above example is a method with less impact on the LSI manufacturing process and the number of masks. However, if this point need not be conscious, a method using a plurality of MISFETs having different gate insulating film thicknesses. There is also. When a MISFET designed with a gate insulating film thickness that can obtain a large current at 1.8 V is used, the on-current of the MISFET is proportional to the inverse of the gate insulating film thickness. If you can add, you can achieve high speed. In this case, leakage current is not a problem, but since three types of gate insulation film thickness are created, the manufacturing process is complicated, the number of masks is increased, and the man-hours for quality control are unavoidable. End up.

  Consumer devices such as portable devices are highly cost-conscious products in order to win the competition with competitors. Therefore, it is desired to narrow down the device types when manufacturing SoC LSIs, reduce the number of masks to be used, and simplify the process steps. Therefore, as an I / O circuit for portable devices, it is a problem to design a low-cost 1.8 V high-speed I / O using 3.3 V transistors.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device including an I / O circuit capable of low-voltage and high-speed operation at low cost.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the present invention, when the I / O voltage vcc is lowered in the I / O circuit, the part that causes the speed deterioration is the level conversion part and the pre-buffer part for driving the main large buffer. Paying attention, the low voltage high speed operation I / O which is the above-mentioned problem is realized by applying a high voltage to the circuit of this part.

  That is, a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a circuit that operates at a first power supply voltage and an output circuit that operates at a second power supply voltage higher than the first power supply voltage, Upon signal transmission from the circuit operating at the first power supply voltage to the output circuit operating at the second power supply voltage, the signal voltage amplitude is once amplified to a third power supply voltage higher than the second power supply voltage; Thereafter, there is provided means for converting into a signal having the amplitude of the second power supply voltage.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, a semiconductor integrated circuit device including an I / O circuit can be operated at a low voltage and a high speed at a low cost.

1 is a block diagram showing a main configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. (A), (b) is a figure which shows the structural example of the I / O circuit of an output side in the semiconductor integrated circuit device by one embodiment of this invention. FIG. 3 is a waveform diagram showing an operation of the output side I / O circuit of FIG. 2. It is a figure which shows the structure of the transistor (MISFET) used with the semiconductor integrated circuit device by one embodiment of this invention. FIG. 3 is a diagram illustrating a layout example of the I / O circuit of FIG. 2 and a cross-sectional structure thereof. FIG. 3 is a diagram illustrating another layout example of the I / O circuit of FIG. 2 and a cross-sectional structure thereof. (A), (b) is a figure which shows another example of a structure of the I / O circuit of an output side in the semiconductor integrated circuit device by one embodiment of this invention. It is a figure which shows another structural example of the main buffer of FIG. FIG. 8 is a diagram illustrating a layout example of the I / O circuit of FIG. 7 and a cross-sectional structure thereof. (A), (b) is a block diagram which shows an example of a power supply connection structure in the semiconductor integrated circuit device by one embodiment of this invention. In the semiconductor integrated circuit device by one embodiment of this invention, it is a figure which shows an example of the power supply connection structure on a package. 1 is a block diagram showing a configuration example when the present invention is applied to a semiconductor integrated circuit device having a plurality of I / O power supplies. It is a block diagram which shows another structural example at the time of applying this invention to the semiconductor integrated circuit device with a some I / O power supply. FIG. 14 is a circuit diagram showing a configuration example of the I / O circuit (withstand voltage relaxation circuit) of FIG. 13. FIG. 15 is a waveform diagram showing an operation of the I / O circuit of FIG. 14. 1 is a circuit diagram showing a configuration example of a level conversion circuit in a semiconductor integrated circuit device according to an embodiment of the present invention. It is a block diagram which shows the structural example of the input circuit at the time of applying this invention to SSTL2. FIG. 18 is a circuit diagram illustrating a configuration example of the differential amplifier in FIG. 17. FIG. 18 is a circuit diagram illustrating a configuration example of the differential amplifier in FIG. 17. FIG. 18 is a waveform diagram showing an operation of the input circuit of FIG. 17. In the semiconductor integrated circuit device by one embodiment of this invention, it is a block diagram which shows the structural example of the termination resistance of an input circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a diagram showing a main configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. In this embodiment, in an output buffer for sending a signal from a logic circuit inside an LSI (semiconductor integrated circuit device) to the outside of the LSI, first, it is converted into a signal having a voltage amplitude higher than the power supply voltage used for the interface unit. After that, it is characterized in that it is converted to the power supply voltage amplitude for the interface.

  FIG. 1 shows a power supply vdd (for example, 1.2 V, first power supply voltage) used in a logic circuit (logic unit) LGC such as a CPU in the LSI, and a standard interface power supply vcc (for example, 3.3 V, third). And a low voltage interface power supply vcc_18 (for example, 1.8 V, the second power supply voltage) are shown. A block diagram showing a path in which an interface signal of 1.8 V is input to the LSI, the signal is processed by internal logic, and output from the LSI. A signal input from the input pad PAD_I passes through an input buffer IBF and a signal level conversion circuit (level down converter LDC) from an I / O (input / output) voltage (1.8 V) to a power supply vdd of the logic circuit. To the internal logic circuit LGC.

  On the other hand, the signal level from the logic circuit LGC needs to be converted from the power supply voltage vdd of the logic circuit to the power supply vcc_18 for I / O. At this time, the feature of the present embodiment is that the level up converter LUC once amplifies the signal amplitude to the higher voltage vcc level, and then amplifies the signal by the pre-buffer PBF, and the main buffer at the final stage This is converted to the interface voltage vcc_18 by the MBF and transmitted. As a result, the level conversion unit and the pre-buffer unit that have been deteriorated in operating speed can be operated at high speed, so that high-speed operation can be performed at a low voltage while using a high voltage MISFET. The level conversion circuit used here can be realized, for example, by using the level conversion circuit described in Patent Document 2.

  In addition, the fact that the level up converter LUC can be shared by the low voltage vcc_18 I / O and the high voltage vcc I / O eliminates the need for redesigning the level conversion circuit, which has the effect of reducing the design man-hours. The level up converter described in Patent Document 2 is a circuit that converts a signal amplitude of a lower voltage (1 V or less) to a high voltage (3.3 V) at a high speed, and the structure is somewhat complicated. If it can be shared by all I / O circuits (input / output circuits), the design cost can be reduced.

  By the way, in the present embodiment, when the signal amplitude is converted from the vdd power supply level to the vcc_18 power supply level, the signal amplitude is boosted and driven by the level conversion saturation circuit and the pre-buffer in the middle. Concerned. However, in a general I / O circuit, there is no problem because the load driven by the I / O circuit is much larger than the gate capacitance of an internal transistor. For example, the specification defines a very large external output load CL of 15 pF. On the other hand, the gate of the I / O circuit is at most about 100 μm, and its capacity is about several hundred fF. Therefore, it can be seen that the power consumed by the main buffer MBF at the final stage is dominated by the charge / discharge of the load capacitance CL, and the power consumed by the level up converter LUC and the prebuffer PBF is negligible.

  Also, the leakage current is at a negligible level. This is because the leakage current tends to be proportional to the drain-source voltage, so it increases compared to when 1.8V is applied. Originally, the high breakdown voltage MISFET is set to a higher threshold value, so the entire SoC chip This is because the amount becomes negligible when the leakage current is taken into consideration.

  Further, in this embodiment, the low-voltage I / O circuit and the high-voltage I / O circuit share the level-up converter and the pre-buffer, so that the level-up converter that determines the characteristics of the I / O circuit The configuration of the pre-buffer is determined almost independently of the final stage voltage. Therefore, rough adjustment of characteristics and fine adjustment to some extent can be performed with only one type of voltage specification (for example, in the case of 3.3V of high voltage, as a margin in the future, for example, 3V which is a voltage value expected to decrease by 10%). . Therefore, there is an effect that stable performance can be realized at a short TAT and at a low cost.

  Therefore, according to the semiconductor integrated circuit device of the present embodiment, the operation speed of 1.8 VI / O can be increased by driving the level conversion unit and the pre-buffer unit at a high voltage.

  In addition, if the level conversion unit and the pre-buffer unit can be shared by 3.3 VI / O and 1.8 VI / O, and if the applied voltage is the same 3.3 V, the sharing of parts and the extraction of cell characteristics are possible. Becomes easy.

  In FIG. 1, the ground potential of the input circuit and the ground potential of the level conversion circuit of the output circuit are set to the same vss as the internal logic circuit. The reason is that the main buffer MBF of the output circuit is composed of very large transistors, and a large noise is placed on the ground potential vssc of the pre-buffer PBF and the main buffer MBF of the output circuit when the transistor is turned on / off. There is a fear. If the input circuit and the level conversion circuit do not take in such noise, there are effects such as deterioration of the operation speed and improvement of signal quality. If there is a product in which such a situation cannot occur, the input circuit and the level conversion circuit can be designed using the ground potential vssc for I / O.

  Next, the configuration of the output I / O circuit IOOC will be described. FIG. 2 shows the configuration of the I / O circuit IOOC on the output side. FIG. 2A is a schematic diagram of the output-side I / O circuit IOOC, and FIG. 2B shows the power supply of each terminal of the transistor.

  First, an outline of the I / O circuit IOOC on the output side will be described with reference to FIG. The level-up converter LUC is a circuit having a function of increasing a signal amplitude, and is operated by applying a vdd power supply used in an internal logic circuit and a vcc power supply having a high potential. The pre-buffer PBF is driven with a high voltage vcc.

  The main buffer MBF at the final stage is driven by a vcc_18 power source that is an interface power source. FIG. 2 shows an example in which the substrate terminal of the P-type MISFET is connected to vcc and the source terminal is connected to vcc_18 as the configuration of the main buffer MBF. Further, the case where the threshold voltage of the P-type MISFET is set small is described.

  Although not shown here, when the P-type MISFET of the main buffer MBF is configured without using a MISFET having a small threshold voltage, the drive current of the P-type MISFET is secured by increasing the gate width W. What should I do?

  However, in a general process, an analog transistor for handling a mixed signal is often set, and in many cases, the transistor is configured by a MISFET having a small threshold voltage. Therefore, when such a MISFET is used, a high-speed low-voltage I / O circuit can be realized without increasing the number of process steps and the number of masks. Therefore, the embodiment will be mainly described here.

  FIG. 2B is a circuit diagram of the pre-buffer PBF and the main buffer MBF shown in FIG. In general, an I / O circuit is complicated with an enable signal, a drive boost switching signal, and the like. Here, an inverter as the simplest amplifier circuit will be described. The present embodiment can be applied to an I / O circuit having a complicated function other than an inverter.

  The pre-buffer PBF is composed of a MISFET that assumes the application of vcc, and its threshold voltage is also designed as a standard circuit to which vcc is supplied.

  On the other hand, the N-type MISFET of the main buffer MBF uses a MISFET similar to the pre-buffer, but the P-type MISFET uses a MISFET in which the channel implant of the MISFET is changed to reduce the threshold voltage of the so-called MISFET. In this P-type MISFET, since the potential of the substrate electrode VB is vcc and the source electrode VS is vcc_18, a substrate bias effect occurs. Further, since the pre-buffer PBF at the previous stage has an operating voltage of vcc, the output of the pre-buffer PBF is at the vcc level in the high output state. Therefore, under the condition that the P-type MISFET of the main buffer MBF is turned off (when the gate voltage of the P-type MISFET is vcc), the so-called negative gate voltage effect (here, since it is a P-type MISFET, the gate voltage is the source voltage). It is possible to reduce the leakage in synergy with the higher value).

  FIG. 3 is an operation waveform diagram of the output I / O circuit shown in FIG. The case where the output node nd1 from the internal logic circuit LGC has the amplitude of the vdd voltage and transitions from the low level (vss level) to the high level (vdd level) at time T1 will be described. Hereinafter, the definition of transition here is the time when the signal crosses half the amplitude. The node nd1 is then input to the level up converter LUC where the signal amplitude is converted to the vcc level. Since there is a delay time of the level-up circuit, the output node nd2 of the level-up circuit transitions from the low level (vssc level) to the high level (vcc level) at time T2. In this example, since the buffer type level up converter is assumed, the logics of the nodes nd1 and nd2 are the same. However, when the inverter type level up converter is used, the logic is the same except that the logic is inverted. Signal level conversion is performed. Thereafter, the node nd2 is input to the pre-buffer PBF, and the driving force is amplified to a driving force sufficient to drive the main buffer MBF. Since the prebuffer PBF is also operated with the vcc power supply, the signal amplitude of the output node nd3 of the prebuffer PBF is the same as the amplitude of the vcc power supply as with the node nd2. In this example, the case of transition from the low level (vssc level) to the high level (vcc level) at time T3 in consideration of the delay amount of the prebuffer PBF is shown. Thereafter, the node nd3 is input to the main buffer MBF, and the main buffer MBF drives an external high load through the output pad PAD_O. Since the main buffer MBF is driven by the vcc_18 power supply, the amplitude of the output node nd4 becomes the amplitude of the vcc_18 power supply. In addition, this example shows that the output waveform of the main buffer MBF is dull due to a large external load, and shows an example of changing from a low level (vssc level) to a high level (vcc_18 level) at time T4.

  Next, a case where a transition from a high level (vdd level) to a low level (vss level) at time T5 will be described. The node nd1 is then input to the level up converter LUC where the signal amplitude is converted to the vcc level. Since there is a delay time of the level-up circuit, the output node nd2 of the level-up circuit transits from the high level (vcc level) to the low level (vssc level) at time T6. Since this example assumes a buffer type level-up converter, the logic of the node nd1 and the node nd2 are the same. However, when an inverter type level-up converter is used, the same signal except that the logic is inverted. Level conversion is performed. Thereafter, the node nd2 is input to the pre-buffer PBF, and the driving force is amplified to a driving force sufficient to drive the main buffer MBF. Since the prebuffer PBF is also operated with the vcc power supply, the signal amplitude of the output node nd3 of the prebuffer PBF is the same as the amplitude of the vcc power supply as with the node nd2. In this example, the case of transition from the high level (vcc level) to the low level (vssc level) at time T7 in consideration of the delay amount of the prebuffer PBF is shown. Thereafter, the node nd3 is input to the main buffer MBF, and the main buffer MBF drives an external high load through the output pad PAD_O. Since the main buffer MBF is driven by the vcc_18 power supply, the amplitude of the output node nd4 becomes the amplitude of the vcc_18 power supply. In this example, the output of the main buffer MBF is dull due to a large external load, and an example is shown in which the level changes from high level (vcc_18 level) to low level (vssc level) at time T8.

  FIG. 4 shows an example of a MISFET used in this embodiment together with a cross-sectional view thereof. Here, VG is a gate electrode, VD is a drain electrode, VS is a source electrode, and VB is a substrate electrode. In this figure, a thin MISFET with a gate electrode symbol indicated by a line segment, and a thick MISFET with a gate electrode indicated by a square box, an N type and a P type, The threshold voltage is classified and displayed.

  The gate insulating film thickness of the MISFET used in the internal logic circuit is designed with a thickness of, for example, about 2 nm, whereas the thick MISFET used in the I / O circuit has a thickness of the internal logic circuit. It is designed to be thicker than the S gate insulating film thickness of MISFET, for example, about 6 to 7 nm.

  The TNS-NMISFET is a thin film standard threshold voltage N-type MISFET used in an internal logic circuit, and the TNS-PMISFET is a thin film standard threshold voltage P-type MISFET.

  The TNL-NMISFET is a thin film low threshold voltage N-type MISFET used in an internal logic circuit, and the TNL-PMISFET is a thin film low threshold voltage P-type MISFET.

  TCS-NMISFET is a thick film standard threshold voltage N-type MISFET used in an I / O circuit, and TCS-PMISFET is a thick film standard threshold voltage P-type MISFET.

  TCL-NMISFET is a thick film low threshold N-type MISFET used in an I / O circuit, and TCL-PMISFET is a thick film low threshold P-type MISFET.

  In these transistors, a deep N well DNW is formed on a P type semiconductor substrate P-sub, and an N well NW for forming a P type MISFET and a P well PW for forming an N type MISFET are formed thereon. Although a so-called triple well configuration has been described, a double well configuration of only the N well NW and the P well PW is possible without using this deep N well DNW. The low threshold voltage MISFET reduces the threshold voltage of the MISFET by implanting additional implantation into the channel portion of the transistor. The N-type diffusion layer NL is an N-type MISFET diffusion layer implantation region and a P-type MISFET substrate feeding diffusion layer implantation region, and the P-type diffusion layer PL is a P-type MISFET diffusion layer implantation region and an N-type MISFET substrate feeding. This is a diffusion layer implantation region.

  FIG. 5 shows a layout example of the I / O circuit. This layout example assumes the output side I / O circuit shown in FIG. 2, and the layout area is divided into four areas. Here, a schematic plan view of the layout is shown at the bottom, and a cross-sectional view between A-A 'shown in the drawing is shown at the top. For simplification, FIG. 5 shows an example in which two cells are laid out back to back in each region (an example in which two sets of N-type MISFETs and P-type MISFETs are configured). The actual layout may be determined by determining the size of each area from the restrictions in the vertical and horizontal directions, and may be realized by a number other than those shown here.

  The first area AREA1 is an area to which vdd, which is a power supply for an internal logic circuit, is applied, and power of vdd and vss is supplied.

  The second area AREA2 is an area to which vcc is applied, and a vcc power supply and a vssc power supply are applied.

  The third area AREA3 is an area to which vcc_18 is applied, and vcc_18 and vssc are applied.

  The fourth area AREA4 is a well isolation region for electrically isolating the first region from the second and third regions. The area of the fourth region can be reduced when a double well structure is used. When the ground level power supply vssc in the second and third regions is the same as the ground level power supply vss in the first region, an LSI can be configured without providing a deep N well DNW. Since the separation of the substrate of vcc and vdd can be performed only by the P well PW, the well separation region is not necessary. However, since the deep N-well DNW is effective for noise separation, separating the power supply in the first region and the second and third regions where the power supply noise is most severe has an effect of improving noise resistance.

  In the first region, the control logic of the I / O circuit and the vdd application unit of the level up converter and the level down converter are laid out. In the second area, the vcc application unit and pre-buffer of the level up converter are laid out. In the third region, the vcc_18 application unit of the level down converter, the main buffer, and the ESD protection element are laid out.

  The third area AREA3 to which vcc_18 is applied differs in layout from the second area AREA2 because the power supply of the P-type MISFET of the main buffer MBF and the substrate power supply are different. In this example, since the power supply wiring in the cell is implemented in the metal first layer, an example in which the layout is made with one vcc power supply and two vcc_18 power supplies is shown. Since the vcc power supply is supplied only to the substrate of the P-type MISFET, the amount of current supply may be smaller than that of vcc_18. Therefore, a thin metal wiring is sufficient in this layout.

  Subsequently, a cross-sectional structure will be described. In the upper part of FIG. 5, a cross section between A-A 'shown in the drawing is schematically shown. This is a case of a so-called triple well structure, in which a deep N-well DNW is formed on a P-type semiconductor substrate P-sub, and an N-well NW for a P-type MISFET and an N-well MISFET for the N-type MISFET are formed thereon. A MISFET is configured by making a P-well PW. The internal logic circuit transistor is composed of a MISFET having a thin gate insulating film, and this MISFET is composed of polysilicon poly12 as a gate electrode. The I / O gate insulating film is formed of a thick MISFET, and the MISFET is formed using a polysilicon poly33 as a gate electrode. Power supply to the substrate and source of each transistor is performed using the metal first layer M1, and power is supplied to the substrate and source from the metal first layer M1 through the contact CT. Although only the power supply to the substrate is shown here, the power supply to the source electrode of the MISFET may be performed by a method well known to those skilled in the art.

  FIG. 6 is a modified example of the layout shown in FIG. 5, and is an embodiment in which two layers of metal wiring can be used for power supply wiring. The cross section between B-B 'in the drawing is also shown. Similarly to FIG. 5, the power supply wiring is performed in the metal first layer M1, but the power supply is strengthened by using the metal 0th layer M0. As described above, when the two-layer power supply wiring is used, it is possible to supply the substrate with the metal 0th layer M0 wiring and supply the power to the source of the MISFET with the metal first layer M1 wiring. This has the effect of improving the degree of freedom of wiring. The example shown in FIG. 6 shows that the P-type MISFET substrate of the main buffer MBF and the source electrode are wired with different wiring layers.

  As is apparent from FIG. 6, this layout is that each cell requires only two power sources for the metal first layer. As shown in the cross-sectional view, the portion to which vcc_18 is applied is that there is no contact CT between the metal first layer M1 and the metal 0th layer M0 in order to separate the vcc_18 and the vcc power supply. Other power sources connect the metal first layer M1 and the metal 0th layer M0 with the contact CT. By implementing such a layout, there is an effect that the degree of freedom of wiring of the metal first layer M1 is increased and the layout is facilitated.

  FIG. 7 is a diagram showing another embodiment of the present invention. As in FIG. 2, the output side I / O circuit is shown. FIG. 7A is an outline of the output I / O circuit, and FIG. 7B shows the power supply of each terminal of the transistor.

  First, an outline of the output I / O circuit will be described with reference to FIG. The level-up converter LUC is a circuit having a function of increasing a signal amplitude, and is operated by applying a vdd power supply used in an internal logic circuit and a vcc power supply having a high potential. The pre-buffer PBF is driven with a high voltage vcc. The main buffer MBF at the final stage is driven by a vcc_18 power source that is an interface power source. In FIG. 7, unlike FIG. 2, the case where the substrate electrode VB of the P-type MISFET is connected to vcc_18 and the P-type MISFET is configured by a MISFET having a standard threshold voltage is described as the configuration of the main buffer.

  FIG. 7B shows a configuration of the pre-buffer PBF and the main buffer MBF shown in FIG. In general, an I / O circuit is complicated with an enable signal, a drive boost switching signal, and the like. Here, an inverter circuit as the simplest amplifier circuit will be described. The present embodiment can be applied to an I / O circuit having a complicated function other than an inverter. The pre-buffer PBF is composed of a MISFET that assumes the application of vcc, and its threshold voltage is also designed as a standard circuit that is supplied with vcc. On the other hand, the N-type MISFET of the main buffer MBF uses the same MISFET as the pre-buffer PBF. Since the potential of the substrate electrode is vcc_18 and the source electrode VS is vcc_18 in this P-type MISFET, under the condition that the P-type MISFET is turned off (when the gate voltage of the P-type MISFET is vcc), the negative gate voltage effect Therefore, low leakage is possible.

  FIG. 8 shows another embodiment of the main buffer MBF. Here, the MISFET having a small threshold voltage is used as the P-type MISFET of the main buffer shown in FIG. As a result, since the driving force of the P-type MISFET is increased, the pull-up of the output node is accelerated, and as a result, there is an effect that the I / O circuit on the output side can be increased in speed.

  Although not shown here, shortening the gate length LG of the MISFET is also effective for increasing the speed. This is because the current of the MISFET is substantially proportional to the reciprocal of the gate length.

  FIG. 9 is a layout example of the configuration of FIG. This layout example assumes the I / O circuit on the output side shown in FIG. 7, and the layout area is divided into five areas. A conceptual plan view of the layout is shown at the bottom, and a cross-sectional view between C and C ′ shown in the drawing is shown at the top. For simplification, FIG. 9 shows an example in which two cells are laid out back to back in each region (an example in which two sets of N-type MISFET and P-type MISFET are configured). The actual layout may be determined by determining the size of each area from the restrictions in the vertical and horizontal directions, and may be realized by a number other than those shown here. These five areas are divided by the substrate power supply of the MISFET.

  The first area AREA1 is an area to which vdd, which is a power supply for an internal logic circuit, is applied, and power of vdd and vss is supplied. The second area AREA2 is an area to which vcc is applied, and a vcc power supply and a vssC power supply are applied. The third area AREA3 is an area to which vcc_18 is applied, and vcc_18 and vssc are applied. The fourth area AREA4 is a well isolation region for electrically isolating the first region from the second and third regions. The fifth area AREA5 is a well isolation region for electrically isolating the second region and the third region. This is because the substrate potential of the P-type MISFET of the main buffer MBF and the substrate potential of the pre-buffer PBF and the P-type MISFET of the level-up converter LUC are different, so that it is necessary to insulate the substrate between the main buffer MBF and the pre-buffer PBF. is there.

  The areas of the fourth and fifth regions can be reduced when a double well structure is used. This is because if the deep N-well DNW is not set in the fifth region, the substrate separation of vcc and vcc_18 can be performed only by the P-well PW, so that it is not necessary to separate the deep N-well DNW. This deep N well DNW may not be set when the ground level power supply vssc of the second and third regions is the same as the ground level power supply vss of the first region. However, since the deep N-well DNW is effective for noise separation, separating the power supply in the first region and the second and third regions where the power supply noise is most severe has an effect of improving noise resistance.

  Here, the case where the power supply wiring is wired in the metal first layer M1 is shown, but as shown in FIG. 6, for example, two or more layers of metal using the metal 0th layer M0 and the metal first layer M1. It is also possible to perform wiring using a wiring layer. In this case, there are effects of facilitating layout and reducing the area.

  FIG. 10 is a diagram showing a power supply configuration (power supply allocation) of an LSI using the present invention. FIG. 10 shows an example in which a vdd power supply, a vcc1 power supply, a vcc2 power supply, and a vcc_18 power supply are configured. The vdd power supply is, for example, 1.2V, vcc1 is, for example, 2.5V, vcc2 is, for example, 3.3V, and vcc_18 is, for example, 1.8V. The ground level power supply is omitted. FIG. 10A is a diagram in which vcc2 and vcc_18 are fed to the input / output circuit SDRAMIF to the SDRAM, and FIG. 10B is a diagram in which vcc1 and vcc_18 are fed to the input / output circuit SDRAMIF to the SDRAM. The input buffer IBF, pre-buffer PBF, main buffer MBF, etc. shown in FIG. 1 are provided in the input / output circuit SDRAMIF.

  First, examples of the circuit block that uses the vdd power supply include a logic unit Logic such as a CPU and an SRAM that is an on-chip storage element. A plurality of these may be integrated. Although not shown here, these circuits only need to have a breakdown voltage of the MISFET or less configured even when operated with different power supply voltages (for example, vdd2 = 0.9 V). The vcc1 includes an analog circuit ANLG and input / output circuits IFC1, IFC2 to a flash memory which is an off-chip storage element. The vcc2 power is supplied because the chip enters a standby state, and a standby circuit STBYC that controls the chip even when, for example, a circuit block to which vdd is applied is cut off from the chip or by an on-chip power switch. And on-chip power cut-off switch control circuits PSWC1, PSWC2, and the like. The power supply vcc_18 is used for an input / output circuit SDRAMIF for SDRAM which is an external storage element. A voltage higher than vcc_18 is supplied to the SDRAMIF. In FIG. 10A, the highest voltage vcc2 is used. Depending on the specifications, as shown in FIG. 10B, using vcc1 is slower than vcc2, but it still has the effect of speeding up.

  In many cases, the MISFETs constituting the analog circuit ANLG, the input / output circuits IFC1 and IFC2 to the flash memory, the standby circuit STBYC, the power cut-off switch control circuits PSWC1 and PSWC2, and the SDRAM input / output circuit SDRAMIF are gate-insulated. It is composed of a thick MISFET. The design value of the gate insulating film thickness is the same. This has the effect of reducing manufacturing costs.

  FIG. 11 is a conceptual diagram showing connection of an I / O circuit and power supply terminal of an LSI. FIG. 11 is a diagram showing a ball grid type power supply wiring that takes power from the upper surface of the LSI chip. Along with the miniaturization of the manufacturing process, a method of avoiding a voltage drop by directly bonding the power supply inside the LSI from the upper part of the chip is becoming mainstream. At that time, if the vcc_18, vssc, and vcc power supplies are arranged from the top of the chip in the vicinity of 1.8 VI / O driven at a low voltage, the power supply capability is most effective, and the layout is facilitated. is there. In FIG. 11, the ball grid is arranged so that vss and vdd are almost equal. However, depending on the LSI, there is a case where the power consumption is biased. In this case, the ball grid is arranged on the circuit block that consumes the most current. A ball grid for power supply may be arranged so that a large number of power supplies can be taken.

  FIG. 12 is another embodiment of the I / O circuit. Here, three types of I / O circuits are described. For simplicity, only the output system from the internal logic circuit CLGC to the outside of the chip is described. Each I / O circuit includes an I / O circuit IO18C operated at the lowest voltage (for example, 1.8V), an I / O circuit IO33C operated at the highest voltage (for example, 3.3V), and an intermediate voltage between these circuits ( For example, the I / O circuit IO25C is operated at 2.5V.

  The I / O circuit IO33C includes vdd and vcc as operation voltages and their ground levels vss and vssc. In addition, it has a protection element ESD1 that protects the inside of the LSI from static electricity from the outside.

  The I / O circuit IO25C includes vdd, vcc_25, vcc, and their ground levels vss and vssc as operating voltages. In addition, it has a protection element ESD1 that protects the inside of the LSI from static electricity from the outside.

  The I / O circuit IO18C includes vdd, vcc_18, and vcc as operating voltages and their ground levels vss and vssc. In addition, it has a protection element ESD1 that protects the inside of the LSI from static electricity from the outside. The I / O circuit shown in FIG. 1 corresponds to the I / O circuit IO18C.

  The MISFETs constituting these I / O circuits are a MISFET with a thin gate insulating film designed to operate with a vdd power supply and a MISFET with a thick gate insulating film designed to operate with a vcc power supply. It consists of two types.

  All of the protection elements ESD1 are composed of the same circuit, and MISFETs that can operate at vcc are used as active elements.

  By adopting such a circuit, it is possible to share a protective element and to reduce the design cost.

  FIG. 13 is a modification of FIG. 12 and is another embodiment of the I / O circuit. Here, three types of I / O circuits are described. For simplicity, only the output system from the internal logic circuit CLGC to the outside of the chip is described. Each I / O circuit includes an I / O circuit IO18C2 that operates at the lowest voltage (for example, 1.8V), an I / O circuit IO33C2 that operates at the highest voltage (for example, 3.3V), and an intermediate between these circuits. The I / O circuit IO25C2 is operated at a voltage (for example, 2.5 V).

  The I / O circuit IO33C2 includes vdd, vcc, and vcc_25 as operation voltages, and vss and vssc as ground levels thereof. Unlike the IO33C described in FIG. 12, this circuit is a MISFET that is created on the assumption that the MISFET that is configured is operated with the vcc_25 power supply. The MISFET operated by vcc_25 is characterized in that the gate insulating film thickness is thinner than the MISFET operated by vcc. Therefore, a high-speed operation is possible with a lower voltage (for example, 2.5 V) than in the case of a MISFET for vcc. However, if this MISFET is operated by applying the vcc power supply as it is, the breakdown voltage of the gate insulating film is exceeded, leading to destruction of the MISFET. In addition, it has a protective element ESD2 that protects the inside of the LSI from static electricity from the outside. Unlike ESD1, this ESD2 uses MISFET etc. which operate | move by vcc_25 as an active element. However, when the vcc voltage is applied to the MISFET as it is, the gate insulating film is destroyed. Therefore, this ESD2 circuit requires a circuit measure for suppressing the maximum applied voltage.

  The I / O circuit IO25C2 includes vdd and vcc_25 as operation voltages and vss and vssc that are ground levels thereof. This circuit is similar to the IO25C described in FIG. 12, but the gate insulating film thickness of the MISFET to which vcc_25 is applied is thinner than the MISFET used in the IO25C. Further, it has a protection element ESD3 that protects the inside of the LSI from static electricity from the outside. Unlike ESD1, ESD3 uses MISFET etc. which operate | move by vcc_25 as an active element.

  The I / O circuit IO18C includes vdd, vcc_18, and vcc_25 as operation voltages and their ground levels vss and vssc. This circuit is similar to the I / O circuit IO18C described in FIG. 12, but the gate insulating film thickness of the MISFET to which vcc_25 and vcc_18 are applied is thinner than the MISFET used in the I / O circuit IO18C. Further, it has a protection element ESD3 that protects the inside of the LSI from static electricity from the outside. Unlike ESD1, ESD3 uses MISFET etc. which operate | move by vcc_25 as an active element. The I / O circuit shown in FIG. 1 corresponds to the I / O circuit IO18C2.

  The MISFETs constituting these I / O circuits are MISFETs with a thin gate insulating film thickness designed to operate with a vdd power supply and MISFETs with a thick gate insulating film thickness designed to operate with a vcc power supply. Consists of types. Further, in the IO33C2 circuit, it is necessary to avoid the breakdown of the gate insulating film when the MISFET designed for the vcc_25 power source is used as the vcc power source.

  When this circuit is used, a MISFET optimized by applying a voltage of vcc_25 can be used as a high breakdown voltage MISFET. Therefore, a circuit to which a power supply of vcc_25 is applied can be operated at high speed.

  FIG. 14 shows an embodiment of I / O circuit IO33C2 shown in FIG. FIG. 14 shows the level-up converter LSC, the pre-buffer PBF, and the main buffer MBF. The MISFET used here is characterized in that a MISFET having a thin gate insulating film thickness used in an internal logic circuit and a MISFET optimized for a vcc_25 voltage are used for I / O. 14 will be described using symbols similar to those of MISFET shown in FIG. 4, but the maximum applied voltage of a MISFET having a thick gate insulating film thickness is assumed to be vcc_25. By using this MISFET, high-speed operation under a voltage of vcc_25 is possible as compared with a MISFET having a thicker gate insulating film thickness designed to apply a vcc power supply.

  By the way, the vcc power supply cannot be directly applied to the MISFET. This is because the gate insulating film thickness of this MISFET does not have a sufficient thickness to withstand the application of vcc. Therefore, in order to operate with the vcc power supply, the maximum applied voltage applied to the MISFET must be suppressed to the vcc_25 voltage or lower. Therefore, in the present embodiment, in order to suppress the maximum applied voltage to the MISFET for enabling the vcc operation to be vcc_25, a withstand voltage relaxation mechanism described later is provided.

  First, the connection relationship of this circuit will be described. The input of the level-up converter LUC is first input to LUC_B, where a signal having an amplitude between the vdd power supply and the vss power supply is converted into a signal having an amplitude between the vcc_25 power supply and the vss power supply. This circuit outputs complementary signals nd11 and nd11b. These output signals are input to LUC_A, where they are converted into signals having the amplitudes of the vcc power supply and the vdd power supply. The output of LUC_A is the signal nd12b. The outputs nd11 and nd12 of LUC_A and LUC_B are continuously input to the prebuffer PBF. The pre-buffer PBF is composed of PBF_A and PBF_B as shown. PBF_A amplifies the driving power of the signal that transitions between the power supply vdd and the power supply vcc, and PBF_B amplifies the driving power of the signal that transitions between the power supply vssc and the power supply vcc_25. The outputs of the pre-buffer PBF are the signal nd16 from PBF_A and the signal nd15 from PBF_B, which are input to the main buffer MBF.

  Here, MN1, MN2, MN3, MN4, MN9, MN10, MN5 and MP5 use MISFETs having a small threshold voltage of MISFETs. This is because these MISFETs are used for withstand voltage reduction, and thus the gate-source voltage is small. If there is no problem even if the operation speed is somewhat slow, these MISFETs can be replaced with MISFETs having a standard threshold voltage. In that case, the manufacturing process can be simplified and the cost can be reduced.

  Next, the operation of the circuit shown in FIG. 14 will be described.

  A case where the input signal i is at the high level (vdd) will be described.

  At this time, in LUC_B, the output of the inverter INV1 is input to the MISFETs MN1, MN7, MP1, and MP9, and the output of the inverter INV2 that receives the output signal of the inverter INV1 is input to the MISFETs MN2, MN8, MP2, and MP10. As a result, since nd11 becomes low level (vss), MP7 is turned on and MP9 is turned on, so nd11b becomes high level (vcc_25).

  When nd11 becomes low level (vss) and nd11b becomes high level (vcc_25), MP3 is turned off, MN9 is turned on, MP4 is turned on, and MN10 is turned off in LUC_A. Since MP11 is off and MN3 is on, nd12 is low level (vdd), MP12 is on and nd12b is high level (vcc). MP13 and MP14 are always on. These MISFETs MP13 and MP14 are used for the purpose of current suppression, and have the purpose of making a high-speed transition to a low level during signal level conversion. If desired performance is obtained without these MISFETs, MP13 and MP14 can be used without using them. In that case, there is an effect of reducing the area. Thus, the operation of the level conversion circuit is determined.

  The two signals whose signal amplitudes have been converted by the level-up converter LUC are buffered to a driving force sufficient to drive the final stage main buffer MBF by the pre-buffer PBF. At this time, since nd11 is at the low level, nd15 is at the low level (vssc). On the other hand, nd12 is at the high level (vcc), so nd16 is at the low level (vdd). Outputs from these pre-buffers PBF are input to the main buffer MBF. In the main buffer MBF, since nd15 is at a low level, MN16 is turned off and MP6 is turned on. Therefore, nd13 becomes the vcc_25 potential, and since the gate potential of MN5 is the vcc_25 power supply, MN5 is also turned off. On the other hand, since nd16 is at the low level (vdd), MP13 is turned on and MN6 is turned off. Therefore, nd14 becomes the vcc potential, and MP5 is also in the on state because the gate potential of MP5 is vdd. Therefore, the output o becomes the vcc level.

  A case where the input signal i is at a low level (vss) will be described.

  At this time, in LUC_B, the output of the inverter INV1 is input to the MISFETs MN1, MN7, MP1, and MP9, and the output of the inverter INV2 that receives the output signal of the inverter INV1 is input to the MISFETs MN2, MN8, MP2, and MP10. As a result, since nd11b is at the low level (vss), MP8 is on and MP10 is on, so nd11 is at the high level (vcc_25).

  When nd11b becomes low level (vss) and nd11 becomes high level (vcc_25), MP4 is turned off, MN10 is turned on, MP3 is turned on, and MN9 is turned off in LUC_A. As a result, MP12 is turned off. Since MN4 is on, nd12b is at the low level (vdd), and as a result, MP11 is on and nd12 is at the high level (vcc). At this time, MP13 and MP14 are always on. These MISFETs MP13 and MP14 are used for the purpose of current suppression, and have the purpose of making a high-speed transition to a low level during signal level conversion. If desired performance is obtained without these MISFETs, MP13 and MP14 can be used without using them. In that case, there is an effect of reducing the area.

  Thus, the operation of the level conversion circuit is determined.

  The two signals whose signal amplitudes have been converted by the level-up converter LUC are buffered to a driving force sufficient to drive the final stage main buffer MBF by the pre-buffer PBF. At this time, since nd11 is at the high level (vcc_25), nd15 is at the high level (vcc_25). One nd12 is at the low level (vdd), so nd16 is at the high level (vcc). Outputs from these pre-buffers PBF are input to the main buffer MBF. In the main buffer MBF, since nd15 is at a high level, MN16 is turned on and MP6 is turned off. Therefore, nd13 becomes the vssc potential, and MN5 is also turned on because the gate potential of MN5 is the vcc_25 power supply. On the other hand, since nd16 is at the high level (vcc), MP13 is turned off and MN6 is turned on. Therefore, nd14 becomes the vdd potential, and MP5 is also in the off state because the gate potential of MP5 is vdd. Therefore, the output o becomes the vssc level.

  FIG. 15 shows an operation waveform diagram of main nodes of the I / O circuit of FIG.

Next, the pressure resistance relaxation will be described.
MISFETs indicated by MN1 to 6 and MP1 to 6 shown in FIG. When the gate voltage of MN1 is at a low level, MP1 is turned on and the source side of MN1 becomes vdd. Look at the voltage relationship at this time.

  Regarding MN7, since the gate voltage is vss, the source voltage is vss, and the drain voltage is vdd, it is within the maximum applied voltage of the MISFET having a thin gate insulating film thickness.

  Regarding MP1, since the gate voltage is vss, the source voltage is vdd, and the drain voltage is vdd, it is within the maximum applied voltage of the MISFET having a thin gate insulating film thickness.

  Regarding MN1, since the gate voltage is vss, the source voltage is vdd, and the drain voltage is vcc_25, it is within the maximum applied voltage of the MISFET having a thick gate insulating film thickness.

  On the other hand, when the gate voltage of MN1 is at a high level (vdd), MP1 is turned off and the source side of MN1 becomes vss. Look at the voltage relationship at this time.

  Regarding MN7, since the gate voltage is vdd, the source voltage is vss, and the drain voltage is vss, it is within the maximum applied voltage of the MISFET having a thin gate insulating film thickness.

  Regarding MP1, since the gate voltage is vdd, the source voltage is vdd, and the drain voltage is vss, it is within the maximum applied voltage of the MISFET having a thin gate insulating film thickness.

  Regarding MN1, since the gate voltage is vdd, the source voltage is vss, and the drain voltage is vss, it is within the maximum applied voltage of the MISFET having a thick gate insulating film thickness.

  Here, the purpose is to suppress the maximum applied voltage of MN7 to vdd or less as described above. MN8, MN2, and MP2 have similar functions, and the maximum applied voltage of MN8 can be suppressed to vdd or less.

  Next, the pressure-resistant relaxation mechanism that constitutes LUC_A will be described.

  A case where nd11 is at the low level (vss) will be described.

  At this time, regarding MN10, since the gate voltage is vss, the source voltage is vdd, and the drain voltage is vcc_25, it is within the maximum applied voltage of the MISFET having a thick gate insulating film thickness.

  Regarding MP4, since the gate voltage is vss, the source voltage is vcc_25, and the drain voltage is vcc_25, it is within the maximum applied voltage of the MISFET having a thick gate insulating film thickness.

  Regarding MN4, since the gate voltage is vcc_25, the source voltage is vcc_25, and the drain voltage is vcc, it is within the maximum applied voltage of the MISFET having a thick gate insulating film thickness.

  A case where nd11 is at a high level (vcc_25) will be described.

  Regarding MN10, since the gate voltage is vcc_25, the source voltage is vdd, and the drain voltage is vdd, it is within the maximum applied voltage of the MISFET having a thick gate insulating film thickness.

  Regarding MP4, since the gate voltage is vcc_25, the source voltage is vcc_25, and the drain voltage is vdd, it is within the maximum applied voltage of the MISFET having a thick gate insulating film thickness.

  Regarding MN4, since the gate voltage is vcc_25, the source voltage is vdd, and the drain voltage is vdd, it is within the maximum applied voltage of the MISFET having a thick gate insulating film thickness.

  Here, the purpose is to suppress the maximum applied voltage of MN10 to (vcc-vcc_25) or less as described above. MN9, MN3, and MP3 have the same function, and the maximum applied voltage of MN8 can be suppressed to (vcc-vcc_25) or less.

  The I / O circuit that operates at a high speed with a voltage lower than the withstand voltage of the MISFET while using a high withstand voltage MISFET has been described above. However, when the operation speed may be slower than that of the embodiment shown in FIG. It is also possible to change the level-up converter.

  FIG. 16 shows another embodiment for operating with a lower power supply vcc_18 while using a MISFET operated with a vcc power supply. Here, a level-up converter is shown, and a circuit similar to the conventional circuit is used for the pre-buffer and the main buffer. In this case, since it is not necessary to wire two kinds of power supplies, the design complexity can be reduced.

  Next, this circuit (level up converter) will be described. In this level up converter, MN21, MN22, MP21, MP22 and an inverter INV21 are configured by a MISFET having a thin gate insulating film thickness, and other MN23, MN24, MN25, MN26, MP23, MP24, MP25, MP26 and an inverter are formed. INV 22 is formed of a MISFET having a thick gate insulating film thickness to which a vcc power supply can be applied.

  This circuit is a cross-coupled level conversion circuit similar to a standard level conversion circuit, but the feature of this embodiment is that the current control MP23 and MP24 have a threshold voltage smaller than MP25 and MP26. That is, it is composed of MISFETs, and MN23 and MN24 are composed of MISFETs having lower threshold voltages than MN25 and MN26. The MN25 and MN26 function as a latch for maintaining the state when the power is shut off and for a stable operation. Since this MISFET having a thick gate insulating film is designed on the assumption that it is operated at vcc (eg, 3.3 V), the saturation current of the MISFET is reduced when operated at vcc_18 (eg, 1.8 V). . The level-up converter realizes signal amplitude conversion by extracting current with the MISFETs of MN21 and MN22. For example, it performs high-speed conversion by performing control to turn off MP23 when the input signal is converted from low to high. it can. Therefore, MP23 and MP24 are effective for the purpose of limiting the current path to the vcc_18 power supply during level conversion. However, since the MISFET originally designed to operate at vcc is operated by the vcc_18 power supply, when the input i becomes high level, the driving current when the drain of the MP23 is raised to the vcc_18 power supply level is reduced and the operation is performed. It will be late. Therefore, by increasing the threshold voltages of MP23 and MP24, it is possible to increase the speed to the vcc_18 level. Thereby, even when the operating power supply voltage is low, there is an effect that the operation of the level up converter can be speeded up. Similarly, the threshold voltages of MN25 and MN26 are reduced in order to prevent an operation delay due to the MISFET having a thick gate insulating film. In this embodiment, an N-type MISFET in which a VCC_18 power supply is applied to the gate for current control is used on the source side of MN25 and MN26. The drive capability of MN25 and MN26 is limited by this MISFET, and the restraint operation of the level conversion circuit becomes possible. Increasing the gate length of the MISFET effectively increases the threshold value and increases the current suppression effect. This N-type MISFET is not essential, and it is possible to design without the N-type MISFET as long as the desired performance is satisfied even without the N-type MISFET. In that case, there is an effect that the area is reduced.

  Hereinafter, an example in which an I / O circuit that is driven at a voltage higher than that of the power source used in the interface according to the present invention is applied to SSTL will be described.

  FIG. 17 shows an embodiment of an input circuit satisfying the specification of the 1.8 V SSTL2 standard. The 1.8 V SSTL2 standard is not a so-called full-amplitude signal in which the input signal transitions between 0 V and vcc_18, but the reference voltage (VREF) is half the voltage of vcc_18 (if Vcc_18 is 1.8 V, VREF = 0.9V), and the maximum amplitude is transmitted as a signal with an amplitude of less than 1.8V. A feature of the present embodiment is that a differential amplifier SA is provided at the input, and the power source of the differential amplifier SA is driven by a vcc power source. This makes it possible to amplify a 1.8V amplitude signal, which is a low voltage, even if a transistor based on the application of the vcc power supply is used at high speed and stably, and to transmit a high quality signal to the subsequent stage. It becomes possible. The output of the differential amplifier SA is input to the input buffer IBF as a full amplitude signal, and is transmitted to the internal logic via the level conversion circuit.

  In addition, when the vdd voltage is low, for example, 1 V, vdd can be used as VREF. In this circuit, the ground power supply vss is used for all the internal logic circuits. The reason is that the noise on the power supply line generated in the output buffer is cut off on the input circuit side.

  FIG. 18 is a diagram illustrating a circuit example of the differential amplifier SA of FIG. FIG. 18 shows a differential amplifier SA using a differential amplifier. The feature of this circuit is that when the power level of the input signal is 1.8V, the power of the sense amplifier circuit receiving the input signal is moved to 3.3V instead of 1.8V. It is possible to provide a circuit that operates at high speed and stably using a transistor optimized for the above purpose. The differential amplifier SA shown in this embodiment is an example of a general differential operational amplifier. Since the input signal level of this circuit and the voltage level of VREF (vcc_18 / 2 = 0.9 V) are low, a method of sensing the voltage with a P-type MISFET is employed. The reason is that since the gate voltage is as low as about 1 V, the source-drain voltage and the source-gate voltage of the P-type MISFET are increased by 3.3 V to operate in the so-called saturation region of the transistor. It is.

  Due to the circuit characteristics of the differential amplifier SA, which is a current amplification type amplifier, it is necessary to always pass a current in order to sense the voltage level. In order to reduce power consumption, it is necessary to reduce this current during non-operation. For this purpose, the control signal CTL is set to the low level to turn off the current control P-type MISFET of the sense amplifier and cut the current flowing through the operational amplifier. At this time, since the output O1 of the sense amplifier is in a floating state, there is a possibility of a through current in a subsequent circuit. Therefore, by making this CTL signal low, the output of the NAND is fixed high, and a through current in this NAND circuit is blocked.

  FIG. 19 is another embodiment of the input circuit of FIG. This circuit is intended to improve the gain and offset characteristics of the operational amplifier by applying a bias voltage to the gate of the P-type MISFET MP30 for current control of the operational amplifier. Normally, in a general operational amplifier, a voltage generated from a bias generation circuit is applied to this P-type MISFET, but it may be difficult to provide this bias generation circuit in an I / O circuit. At that time, paying attention to the fact that the node ND30 in the operational amplifier becomes a kind of bias generation circuit, this voltage is used as a bias voltage. Also in this circuit, since it is necessary to suppress unnecessary current consumption when not in operation, it is necessary to perform current consumption reduction control with the control signal CTL. By making the control signal CTL low, the transmission gate composed of MN33 and MP33 is turned off, the gates of ND30 and MP30 are shut off, and at the same time, the P-type MISFET of MP37 is turned on. Thus, the power supply of the operational amplifier is cut off. At this time, the output of the operational amplifier becomes unstable due to the power supply of the operational amplifier being cut off. At this time, since the MN32 is turned on, it is possible to avoid a through current in a circuit in the subsequent stage. In FIG. 19, a high signal is sent to an internal circuit to stop the operational amplifier, and this CTL signal is used.

  FIG. 20 shows operation waveforms of the circuit of FIG. The input level of the SSTL 18 is not a full amplitude of 1.8 V, but a signal having an amplitude of about 0.4 to 1 V centered on VREF. Here, VREF is determined by the standard to be half the voltage of the vcc_18 power supply. First, conversion from low level to high level will be described. When the input changes from the low level to the high level at time T1, the input signal crosses VREF at time T1, so the output of the sense amplifier changes. The sense amplifier amplifies the difference between the input signals I and VREF and converts it to a signal having amplitudes of 0 V and vcc. Here, the waveform is shaped by the input buffer that has received the output of the sense amplifier at time T2. After that, the signal is converted into a signal of vdd amplitude by the level conversion circuit, and transits to the high level at time T3.

  Next, conversion from high level to low level will be described. When the input changes from the high level to the low level at time T4, the input signal crosses VREF at time T4, so that the output of the sense amplifier changes. The sense amplifier amplifies the difference between the input signals I and VREF and converts it to a signal having amplitudes of 0 V and vcc. Here, the waveform is shaped by the input buffer that has received the output of the sense amplifier at time T5. Thereafter, the signal is converted into a signal of vdd amplitude by the level conversion circuit, and changes to 0 V at time T6.

  FIG. 21 is a diagram illustrating an embodiment of a termination resistor of the input circuit. Here, the termination resistor is composed of MP40 and MN40 in the ESD circuit. These MISFETs are placed between the input I and the VTT power supply. The VTT power supply is set to a value of vcc_18 / 2 in SSTL or the like. The gate signals of these MISFETs are connected to CTL1 on the P-type MISFET side and to CTL2 on the N-type MISFET side. CTL1 and CTL2 are configured using MISFETs that can withstand the application of the vcc voltage, and these signals are driven by the vcc power supply voltage. If the MN40 is configured in this way, it can be used in a place where the on-resistance of the transistor is small, so that the area can be reduced. For example, when the termination resistance is 50Ω, when driving at 1.8V, assuming that the on-resistance of the MISFET is 2.5 KΩ per unit width (1 micrometer), 50 μm is required, but at 3.3V Assuming that the on-resistance of the MISFET is 1 KΩ per unit width when driving, it can be realized with a 20 μm MISFET. In this way, the MISFET can be reduced in size, and as a result, the area can be reduced. In addition, since the control voltage of CTL1 and CTL2 is high, a sufficiently high gate voltage can be applied particularly in the control of the N-type MISFET, so that this N-type MISFET can be operated in a sufficient saturation region, so that the control voltage is a little. There is also an effect that the influence on the variation degree of the on-resistance can be sufficiently reduced with respect to the fluctuation.

  Here, the P-type MISFET can be omitted, and it can be constituted by only the N-type MISFET.

  Although the present embodiment has mainly described SSTL, it can also be applied to a general low-amplitude I / O termination resistor.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a semiconductor device such as a system LSI for a portable device or a microprocessor.

ANLG Analog circuit CL External load capacitance CT Contact DNW Deep N well ESD1, ESD2, ESD3 Protection element IFC1, IFC2, SDRAMIF Input / output circuit IBF Input buffer INV1, INV2, INV21, INV22 Inverter LSI Semiconductor integrated circuit devices IIOC, IO18C, IO18C2, IO25C, IO25C2, IO33C, IO33C2, and IOOC I / O circuit
LDC Level down converter LGC, CLGC Logic circuit (logic part)
LUC, LSC Level-up converter MBF Main buffers MN1 to MN40, MP1 to MP40 Transistors (MISFET)
M0 Metal 0th layer M1 Metal 1st layer NL N-type diffusion layer NW N-well PBF Pre-buffer PAD_I Input pad PAD_O Output pad PL P-type diffusion layers PSWC1, PSWC2 Control circuit PW P-well P-sub P-type semiconductor substrate SA Differential Amplifier STBYC Standby circuit VB Substrate electrode VG Gate electrode VS Source electrode VD Drain electrode poly12, poly33 Polysilicon vcc vcc power supply vcc_18 vcc_18 power supply vdd vdd power supply vss vss power supply vssc power supply

Claims (2)

An inverter circuit for receiving an input signal;
A first N-type transistor receiving the input signal at a gate;
A first P-type transistor receiving the input signal at a gate and having a drain connected to a drain of the first N-type transistor;
A second N-type transistor receiving the input signal at a gate and having a source connected to a drain of the first P-type transistor;
A second P-type transistor receiving the input signal at a gate and having a drain connected to a drain of the second N-type transistor;
A third N-type transistor receiving at its gate an output signal of the inverter circuit;
A third P-type transistor receiving the output signal at a gate and having a drain connected to the third N-type transistor;
A fourth N-type transistor receiving the output signal at a gate and having a source connected to a drain of the third P-type transistor;
A fourth P-type transistor receiving the output signal at a gate and having a drain connected to a source of the fourth N-type transistor;
A fifth P-type transistor having a gate connected to the drain of the second N-type transistor and a drain connected to the source of the fourth P-type transistor;
A sixth P-type transistor having a gate connected to the drain of the fourth N-type transistor and a drain connected to the source of the second P-type transistor;
A fifth N-type transistor having a gate connected to the gate of the fifth P-type transistor and the drain of the second P-type transistor;
A sixth N-type transistor having a gate connected to the gate of the sixth P-type transistor and the drain of the fourth P-type transistor;
A seventh N-type transistor having a drain connected to the sources of the fifth and sixth N-type transistors and a source connected to the first potential;
The gate insulating films of the transistors constituting the inverter circuit, the first and third N-type transistors, and the first and third P-type transistors have a first film thickness,
The gate insulating films of the second, fourth, fifth, and sixth N-type transistors and the second, fourth, fifth, and sixth P-type transistors are thicker than the first film thickness. 2 film thickness,
P-type transistors of the second and fourth has a first threshold voltage,
The P-type transistor of the fifth and sixth has a second threshold voltage,
It said second and fourth N-type transistor has a third threshold voltage,
The first threshold voltage is lower than the second threshold voltage;
The semiconductor integrated circuit device, wherein the third threshold voltage is lower than the second threshold voltage . The semiconductor integrated circuit device according to claim 1.
The high level side potential of the input signal is a second potential,
The inverter circuit is operated by a power supply voltage having the second potential,
The semiconductor integrated circuit device, wherein sources of the fifth and sixth P-type transistors are connected to a power supply voltage having a third potential higher than the second potential.

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