CN114661649A - Bias circuit - Google Patents
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- CN114661649A CN114661649A CN202210378622.2A CN202210378622A CN114661649A CN 114661649 A CN114661649 A CN 114661649A CN 202210378622 A CN202210378622 A CN 202210378622A CN 114661649 A CN114661649 A CN 114661649A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The application discloses a bias circuit, which comprises a first voltage source, a control unit and bias units, wherein the bias units are connected with the first voltage source and the control unit, each bias unit comprises a preset number of load circuits connected in parallel, and each load circuit consists of at least one on-off circuit; the control unit is used for providing a control signal; the bias unit is used for controlling the on-off state of each on-off circuit under the action of the control signal, so that the voltage of each load circuit is controlled, and the bias voltage lower than a preset voltage value is output. The bias circuit can be compatible with the application occasions of 1.8V and 3.3V of the driving circuit, provides a proper static working point and ensures the high voltage resistance of the device.
Description
Technical Field
The present application relates to the field of electronic circuits and semiconductor designs, and more particularly, to a bias circuit.
Background
In the process of 22nm or more, there are 3.3V high voltage tolerant devices, and it is not necessary to add an additional bias circuit to the driving circuits such as Universal Serial Bus 2 (USB) and General-purpose input/output (GPIO). However, in 14nm or more advanced processes, the high-voltage tube is difficult to integrate, and in the advanced processes, only the low-voltage tube with the withstand voltage of 1.8V or lower is generally used, but the driving circuit is applied with high voltage of 3.3V, so that the bias voltage generated by the bias circuit is very important for realizing high-voltage driving of the low-voltage device. However, the bias circuit in the prior art is not compatible with the application of the driving circuit of 1.8V and 3.3V. Therefore, how to make the bias circuit compatible with the application of the driving circuit of 1.8V and 3.3V is a technical problem to be solved.
Disclosure of Invention
An object of the present invention is to provide a bias circuit, so as to solve the problem of how to make the bias circuit compatible with the application of the driving circuit of 1.8V and 3.3V.
In a first aspect, an embodiment of the present application provides a bias circuit, where the bias circuit includes a power supply, a control unit, and a bias unit, the bias unit is connected to both the power supply and the control unit, the bias unit includes a preset number of load circuits connected in parallel, and each load circuit is composed of at least one on-off circuit;
the control unit is used for providing a control signal;
the bias unit is used for controlling the on-off state of each on-off circuit under the action of the control signal, further controlling the voltage of each load circuit and outputting a bias voltage lower than a preset voltage value.
In an alternative embodiment, the bias unit includes a first load circuit, a second load circuit, a third load circuit, and a fourth load circuit connected in parallel;
the first load circuit comprises a first on-off circuit and a second on-off circuit which are connected in series, the second load circuit comprises a third on-off circuit and a fourth on-off circuit which are connected in series, the third load circuit comprises a fifth on-off circuit and a sixth on-off circuit, the fourth load circuit comprises a seventh on-off circuit, the seventh on-off circuit is connected with the second on-off circuit in parallel, and the third on-off circuit is connected with the fifth on-off circuit in parallel;
the bias unit is configured to step down an output voltage of the first voltage source to a first bias voltage and a second bias voltage, and then output the first bias voltage and the second bias voltage, where the first bias voltage is a node voltage between the first on-off circuit and the second on-off circuit, and the second bias voltage is a node voltage between the third on-off circuit and the fourth on-off circuit.
In an optional embodiment, the control signal output by the control unit includes a first control signal, a second control signal, a third control signal, a fourth control signal, and a fifth control signal;
the first on-off circuit is connected with the first control signal and is switched off or switched on according to the first control signal;
the third breaking circuit is used for connecting the first control end and breaking or conducting according to a level signal sent by the first control end;
the fifth on-off circuit comprises a first switch tube and a second switch tube, the first switch tube is connected with the second switch tube in series, the first switch tube is connected with the second control signal and is opened or closed according to the second control signal, and the second switch tube is connected with the first control end and is opened or closed according to the level signal sent by the first control end;
the seventh on-off circuit comprises a third switching tube and a fourth switching tube, the third switching tube and the fourth switching tube are connected in series, the third switching tube is used for being connected with the second control end and is opened or closed according to a level signal sent by the second control end, and the fourth switching tube is connected with the third control signal and is opened or closed according to the third control signal;
the second on-off circuit is used for being connected with the second control end and is switched off or on according to the level signal sent by the second control end;
the fourth breaking circuit is connected with the fourth control signal and is broken or conducted according to the fourth control signal;
the sixth on-off circuit is connected with the fifth control signal and is turned off or turned on according to the fifth control signal.
In an optional implementation manner, the first on-off circuit includes a fifth switching tube and a first resistor, a first end of the fifth switching tube is used for connecting the first voltage source, a control end of the fifth switching tube is used for receiving the first control signal, and a second end of the fifth switching tube is connected to the second on-off circuit through the first resistor.
In an optional implementation manner, the third disconnection circuit includes a sixth switching tube and a second resistor, a first end of the sixth switching tube is used for connecting the first voltage source, a control end of the sixth switching tube is used for connecting the first control end, and a second end of the sixth switching tube is connected to the fourth disconnection circuit through the second resistor.
In an optional implementation manner, a first end of the first switching tube is configured to be connected to the first voltage source, a control end of the first switching tube is configured to access the second control signal, a second end of the first switching tube is connected to a first end of the second switching tube, a control end of the second switching tube is configured to access the first control end, and a second end of the second switching tube is configured to be connected to the sixth on-off circuit.
In an optional implementation manner, a first end of the third switching tube is connected to the first on-off circuit, a control end of the third switching tube is used to access the second control end, a second end of the third switching tube is connected to a first end of the fourth switching tube, a control end of the fourth switching tube is used to access the third control signal, and a second end of the fourth switching tube is grounded.
In an optional implementation manner, the second on-off circuit includes a third resistor and a seventh switching tube, one end of the third resistor is connected to the first on-off circuit, the other end of the third resistor is connected to the first end of the seventh switching tube, the control end of the seventh switching tube is used for being connected to the second control end, and the second end of the seventh switching tube is grounded.
In an optional implementation manner, the fourth breaking circuit includes a fourth resistor and an eighth switching tube, one end of the fourth resistor is connected to the third breaking circuit, the other end of the fourth resistor is connected to the first end of the eighth switching tube, a control end of the eighth switching tube is used for accessing the fourth control signal, and a second end of the eighth switching tube is grounded.
In an optional implementation manner, the sixth on-off circuit includes a fifth resistor and a ninth switch tube, one end of the fifth resistor is connected to the fifth on-off circuit, the other end of the fifth resistor is connected to the first end of the ninth switch tube, the control end of the ninth switch tube is used for accessing the fifth control signal, and the second end of the ninth switch tube is grounded.
In an alternative embodiment, the control unit includes a power supply detection subunit, a first output subunit, a second output subunit, and a third output subunit; the power supply detection subunit is configured to detect a first voltage source and a second voltage source connected to the control unit, the first output subunit is configured to output the first control signal and the third control signal, the second output subunit is configured to output the second control signal and the fourth control signal, and the third output subunit is configured to output the fifth control signal;
the power supply detection subunit comprises a tenth switching tube, an eleventh switching tube, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor, the first end of the tenth switching tube is used for connecting the first voltage source, the control end of the tenth switching tube is used for connecting the second voltage source, a second end of the tenth switching tube is grounded through the sixth resistor, the seventh resistor, the eighth resistor and the ninth resistor in sequence, a first end of the eleventh switch tube is connected to one end of the tenth resistor, and the other end of the tenth resistor is used for connecting the second voltage source, the first end of the eleventh switching tube is further connected with the first output subunit, the control end of the eleventh switching tube is connected with a third node between the sixth resistor and the seventh resistor, and the second end of the eleventh switching tube is grounded;
the first output subunit comprises a first inverter, a second inverter and a third inverter, one end of the first inverter is connected to the first end of the eleventh switching tube, the other end of the first inverter is connected to one end of the second inverter, the other end of the second inverter is used for outputting the first control signal, the other end of the second inverter is further connected to one end of the third inverter, and the other end of the third inverter is used for outputting the third control signal;
the second output subunit includes a level shift subunit, a first end of the level shift subunit is connected to the other end of the first inverter, a second end of the level shift subunit is configured to output the second control signal, a third end of the level shift subunit is configured to output the fourth control signal, and a fourth end of the level shift subunit is connected to the third output subunit;
the third output subunit comprises a power protection subunit, one end of the power protection subunit is connected to the fourth end of the level conversion subunit, and the other end of the power protection subunit is used for outputting the fifth control signal.
The embodiment of the application provides a bias circuit, which comprises a first voltage source, a control unit and a bias unit, wherein the bias unit is connected with the first voltage source and the control unit, the bias unit comprises a preset number of load circuits connected in parallel, and each load circuit consists of at least one on-off circuit; the control unit is used for providing a control signal; the bias unit is used for controlling the on-off state of each on-off circuit under the action of the control signal, so that the voltage of each load circuit is controlled, and the bias voltage lower than a preset voltage value is output. The bias circuit can be compatible with the application occasions of 1.8V and 3.3V of the driving circuit, provides a proper static working point and ensures the high voltage resistance of the device.
Drawings
In order to more clearly explain the technical solutions of the present application, the drawings needed to be used in the embodiments are briefly introduced below, and it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope of protection of the present application. Like components are numbered similarly in the various figures.
Fig. 1 is a schematic block diagram of a first bias circuit provided in an embodiment of the present application;
FIG. 2 is a schematic block diagram of a second bias circuit provided in an embodiment of the present application;
fig. 3 is a circuit diagram illustrating a bias unit of a bias circuit according to an embodiment of the present disclosure;
fig. 4 shows a circuit diagram of a control unit of a bias circuit provided in an embodiment of the present application.
Description of the main element symbols:
10-a bias circuit; 100-a control unit; 110-a power supply detection subunit; 120-a first output subunit; 121-a third control signal; 122-a fourth control signal; 130-a second output subunit; 131-a first control signal; 132-a second control signal; 133-a level shifting subunit; 140-a third output subunit; 141-fifth control signal; 142-a power protection subunit; 150-a circuit protection subunit; 200-a bias unit; 201-a first load circuit; 202-nth load circuit; 203-a second load circuit; 204-a third load circuit; 205-a fourth load circuit; 210-a first on-off circuit; 220-a second on-off circuit; 230-third breaking circuit; 240-fourth break circuit; 250-a fifth on-off circuit; 260-sixth on-off circuit; 270-a seventh on-off circuit; 280-a first node; 290-a second node; 300-third node.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.
The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present application, are intended to indicate only specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present application belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments.
Example 1
Referring to fig. 1, fig. 1 shows a schematic block diagram of a first bias circuit provided in an embodiment of the present application.
As shown in fig. 1, the bias circuit 10 includes a first voltage source AVDD3318, a control unit 100, and a bias unit 200, the bias unit 200 is connected to both the first voltage source AVDD3318 and the control unit 100, the bias unit 200 includes a preset number of load circuits connected in parallel, and each load circuit is composed of at least one on-off circuit;
the control unit 100 is used for providing a control signal;
the bias unit 200 is configured to control the on-off state of each on-off circuit under the action of the control signal, so as to control the voltage of each load circuit, and output a bias voltage lower than a preset voltage value.
The number of load circuits is set according to actual requirements, and is not limited herein. In this embodiment, the predetermined number is N, that is, the bias unit 200 includes N load circuits, and the first load circuit 201 to the nth load circuit 202 are connected in parallel. The control unit 100 inputs a control signal to the bias unit 200 according to the voltage value input by the first voltage source AVDD3318, so as to control the on/off state of each on/off circuit. The voltage of each load circuit is divided by adjusting the on-off state of the on-off circuit included in the load circuit, so that the bias unit 200 composed of a preset number of load circuits outputs a bias voltage lower than a preset voltage value.
Referring to fig. 2, fig. 2 is a schematic block diagram of a second bias circuit according to an embodiment of the present disclosure.
In a specific embodiment, the bias unit 200 includes a first load circuit 201, a second load circuit 203, a third load circuit 204, and a fourth load circuit 205 connected in parallel;
the first load circuit 201 comprises a first on-off circuit 210 and a second on-off circuit 220 which are connected in series, the second load circuit 203 comprises a third on-off circuit 230 and a fourth on-off circuit 240 which are connected in series, the third load circuit 204 comprises a fifth on-off circuit 250 and a sixth on-off circuit 260, the fourth load circuit 205 comprises a seventh on-off circuit 270, the seventh on-off circuit 270 is connected in parallel with the second on-off circuit 220, and the third on-off circuit 230 is connected in parallel with the fifth on-off circuit 250;
the bias unit 200 is configured to regulate an output voltage of the first voltage source AVDD3318 to the first bias voltage and the second bias voltage, and then output the regulated output voltage, where the first bias voltage is a node voltage between the first on-off circuit 210 and the second on-off circuit 220, and the second bias voltage is a node voltage between the third on-off circuit 230 and the fourth on-off circuit 240.
In this embodiment, the first voltage source AVDD3318 may provide a voltage of 3.3V or 1.8V. Taking the example that the first voltage source AVDD3318 provides a voltage of 1.8V, the on-off state of each on-off circuit is controlled by the control signal. Specifically, the first on-off circuit 210 and the second on-off circuit 220 of the first load circuit 201 are both in an off state, the third on-off circuit 230 of the second load circuit 203 is in an on state, the fourth on-off circuit 240 is in an off state, the fifth on-off circuit 250 of the third load circuit 204 is in an on state, the sixth on-off circuit 260 is in an off state, and the seventh on-off circuit 270 of the fourth load circuit 205 is in an on state. At this time, the first bias voltage is pulled to 0, and the second bias voltage is pulled to 1.8V, so as to implement the application of the first voltage source AVDD3318 of 1.8V.
Referring to fig. 3, fig. 3 is a circuit diagram illustrating a bias unit of a bias circuit according to an embodiment of the present disclosure.
In a specific embodiment, the control signals output by the control unit 100 include a first control signal 131, a second control signal 132, a third control signal 121, a fourth control signal 122, and a fifth control signal 141; the bias unit 200 controls the on/off of each subunit according to the control signal, and includes:
the first on/off circuit 210 is connected to the first control signal 131, and is turned off or turned on according to the first control signal 131.
The third disconnection circuit 230 is connected to the first control terminal, and is disconnected or connected according to a level signal sent by the first control terminal.
The fifth on-off circuit 250 includes a first switch tube MP1 and a second switch tube MP2, the first switch tube MP1 is connected in series with the second switch tube MP2, the first switch tube MP1 is connected to the second control signal 132 and is turned on or turned off according to the second control signal 132, and the second switch tube MP2 is connected to the first control end and is turned on or turned off according to a level signal sent by the first control end.
The seventh on-off circuit 270 includes a third switching tube MN3 and a fourth switching tube MN4, the third switching tube MN3 is connected in series with the fourth switching tube MN4, the third switching tube MN3 is used for connecting the second control end and is turned on or turned off according to a level signal sent by the second control end, and the fourth switching tube MN4 is used for connecting the third control signal 121 and is turned on or turned off according to the third control signal 121.
The second on-off circuit 220 is used for connecting the second control terminal, and is turned off or turned on according to a level signal sent by the second control terminal.
The fourth breaking circuit 240 is connected to the fourth control signal 122, and is broken or turned on according to the fourth control signal 122.
The sixth on/off circuit 260 is connected to the fifth control signal 141, and is turned off or on according to the fifth control signal 141.
It should be understood that the first control terminal and the second control terminal are both devices capable of outputting signals with different levels, so as to control the on/off circuit to be opened or closed. In this embodiment, the first control terminal can be implemented by the first bias voltage VBP, and the on-off state of the on-off circuit is controlled by the first bias voltage VBP. Specifically, the first bias voltage VBP pulled down to 0 is input to the on/off circuit to make the on/off circuit in an on state, or the first bias voltage VBP pulled up to 1.8V is input to the on/off circuit to make the on/off circuit in an off state. Similarly, the second control terminal can be implemented by the second bias voltage VBN, and controls the on/off state of the on/off circuit by the second bias voltage VBN.
In an alternative embodiment, the first switching circuit 210 includes a fifth switching tube MP5 and a first resistor R1, a first end of the fifth switching tube MP5 is configured to be connected to the first voltage source AVDD3318, a control end of the fifth switching tube MP5 is configured to receive the first control signal 131, and a second end of the fifth switching tube MP5 is connected to the second switching circuit 220 through the first resistor R1.
In this embodiment, the fifth switch tube MP5 is a PMOS (positive channel Metal Oxide Semiconductor) tube.
In an optional embodiment, the third breaking circuit 230 includes a sixth switching tube MP6 and a second resistor R2, a first end of the sixth switching tube MP6 is configured to be connected to the first voltage source AVDD3318, a control end of the sixth switching tube MP6 is configured to be connected to the first control end, and a second end of the sixth switching tube MP6 is connected to the fourth breaking circuit 240 through the second resistor R2.
In this embodiment, the sixth switching tube MP6 is an NMOS (Negative channel Oxide Semiconductor field effect) tube.
In an optional embodiment, a first end of the first switch tube MP1 is configured to be connected to the first voltage source AVDD3318, a control end of the first switch tube MP1 is configured to receive the second control signal 132, a second end of the first switch tube MP1 is connected to a first end of the second switch tube MP2, a control end of the second switch tube MP2 is configured to receive the first control end, and a second end of the second switch tube MP2 is configured to be connected to the sixth on/off circuit 260.
In this embodiment, the first switch tube MP1 and the second switch tube MP2 are both PMOS tubes.
In an optional implementation manner, a first terminal of the third switching tube MN3 is connected to the first on-off circuit 210, a control terminal of the third switching tube MN3 is used to access the second control terminal, a second terminal of the third switching tube MN3 is connected to a first terminal of the fourth switching tube MN4, a control terminal of the fourth switching tube MN4 is used to access the third control signal 121, and a second terminal of the fourth switching tube MN4 is grounded.
In this embodiment, the third switching tube MN1 and the fourth switching tube MN2 are both NMOS tubes.
In an optional implementation manner, the second open-close circuit 220 includes a third resistor R3 and a seventh switch tube MN7, one end of the third resistor R3 is connected to the first open-close circuit 210, the other end of the third resistor R3 is connected to the first end of the seventh switch tube MN7, a control end of the seventh switch tube MN7 is used to access the second control end, and the second end of the seventh switch tube MN7 is grounded.
In this embodiment, the seventh switch MN7 is an NMOS transistor.
In an optional implementation manner, the fourth breaking circuit 240 includes a fourth resistor R4 and an eighth switch tube MN8, one end of the fourth resistor R4 is connected to the third breaking circuit 230, the other end of the fourth resistor R4 is connected to the first end of the eighth switch tube MN8, a control end of the eighth switch tube MN8 is used to access the fourth control signal 122, and the second end of the eighth switch tube MN8 is grounded.
In this embodiment, the eighth switch MN8 is an NMOS transistor.
In an optional implementation manner, the sixth on-off circuit 260 includes a fifth resistor R5 and a ninth switching tube MN9, one end of the fifth resistor R5 is connected to the fifth on-off circuit 250, the other end of the fifth resistor R5 is connected to the first end of the ninth switching tube MN9, a control end of the ninth switching tube MN9 is used to access the fifth control signal 141, and the second end of the ninth switching tube MN9 is grounded.
In this embodiment, the ninth switch MN9 is an NMOS transistor.
Specifically, the resistances of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are all the same.
It is understood that the operating principle of the bias unit 200 is as follows: when the first voltage source AVDD3318 is 3.3V, the first control signal 131 is 1.65V, the second control signal 132 is 3.3V, the third control signal 121 is 0V, the fourth control signal 122 is 1.8V, and the fifth control signal 141 is 0V, the first switching tube MP1, the second switching tube MP2, the fourth switching tube MN4, and the ninth switching tube MN9 are all turned on, and the third switching tube MN3, the fifth switching tube MP5, the sixth switching tube MP6, the seventh switching tube MN7, and the eighth switching tube MN8 are all turned on. That is, the first on-off circuit 210, the third on-off circuit 230, the second on-off circuit 220, and the fourth on-off circuit 240 are all turned on, the fifth on-off circuit 250, the seventh on-off circuit 270, and the sixth on-off circuit 260 are all turned off, and VBP ═ VBN ═ 0.5 ═ AVDD3318 ═ 1.65V. The bias voltage is applied to the isolation tube of the drive circuit to ensure that the output branch MOS tube has no voltage withstanding problem.
Further, when the first voltage source AVDD3318 is 3.3V, the first control signal 131 is 1.65V, the second control signal 132 is 3.3V, the third control signal 121 is 0V, the fourth control signal 122 is 0V, and the fifth control signal 141 is 1.65V, the first switching tube MP1, the second switching tube MP2, the third switching tube MN3, the fourth switching tube MN4, and the eighth switching tube MN8 are all turned on, and the fifth switching tube MP5, the sixth switching tube MP6, the seventh switching tube MN7, and the ninth switching tube MN9 are all turned on. That is, the first on/off circuit 210, the third on/off circuit 230, the second on/off circuit 220, and the sixth on/off circuit 260 are all turned on, the fifth on/off circuit 250, the seventh on/off circuit 270, and the fourth on/off circuit 240 are all turned off, and VBP ═ VBN ═ 0.5 ═ AVDD3318 ═ 1.65V. The bias voltage is applied to the isolation tube of the drive circuit to ensure that the output branch MOS tube has no voltage withstanding problem.
Further, when the first voltage source AVDD3318 is 1.8V, the first control signal 131 is 1.8V, the second control signal 132 is 0V, the third control signal 121 is 1.8V, the fourth control signal 122 is 0V, and the fifth control signal 141 is 0V, the fifth switching tube MP5, the eighth switching tube MN8, and the ninth switching tube MN9 are all turned on, and the first switching tube MP1, the second switching tube MP2, the third switching tube MN3, the fourth switching tube MN4, the sixth switching tube MP6, and the seventh switching tube MN7 are all turned on. That is, the first on-off circuit 210, the fourth on-off circuit 240, and the sixth on-off circuit 260 are all open, the third on-off circuit 230, the fifth on-off circuit 250, the seventh on-off circuit 270, and the second on-off circuit 220 are all on, VBP is 0V, and VBN is 1.8V. At this time, the first bias voltage VBP and the second bias voltage VBN can be normally applied even when applied to the isolation tube of the driving circuit, and there is no problem of withstand voltage.
Referring to fig. 4, fig. 4 is a circuit diagram illustrating a control unit of a bias circuit according to an embodiment of the present disclosure.
In an alternative embodiment, the control unit 100 includes a power detection subunit 110, a first output subunit 120, a second output subunit 130, and a third output subunit 140; the power supply detecting sub-unit 110 is configured to detect a first voltage source AVDD3318 and a second voltage source AVDD18 connected to the control unit 100, the second voltage source AVDD18 may provide a voltage of 1.8V, the first output sub-unit 120 is configured to output the first control signal 131 and the third control signal 121, the second output sub-unit 130 is configured to output the second control signal 132 and the fourth control signal 122, and the third output sub-unit 140 is configured to output the fifth control signal 141.
The power detecting sub-unit 110 includes a tenth switching tube MP10, an eleventh switching tube MN11, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10, a first end of the tenth switching tube MP10 is configured to be connected to the first voltage source AVDD3318, a control end of the tenth switching tube MP10 is configured to be connected to the second voltage source AVDD18, a second end of the tenth switching tube MP10 passes through the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, and the ninth resistor R9 in sequence and is grounded, a first end of the eleventh switching tube MN11 is connected to one end of the tenth resistor R10, another end of the tenth resistor R10 is configured to be connected to the second voltage source AVDD18, a first end of the eleventh switching tube MN11 is further connected to the first output sub-unit 120, a first end of the eleventh switching tube MN11 is connected to the sixth node of the sixth resistor R6R 7, a second terminal of the eleventh switch tube MN11 is grounded.
The first output subunit 120 includes a first inverter INV1, a second inverter INV2 and a third inverter INV3, one end of the first inverter INV1 is connected to the first end of the eleventh switching tube MN11, the other end of the first inverter INV1 is connected to one end of the second inverter INV2, the other end of the second inverter INV2 is used for outputting the first control signal 131, the other end of the second inverter INV2 is further connected to one end of the third inverter INV3, and the other end of the third inverter INV3 is used for outputting the third control signal 121.
The second output subunit 130 includes a level shift subunit 133, a first end of the level shift subunit 133 is connected to the other end of the first inverter INV1, a second end of the level shift subunit 133 is configured to output the second control signal 132, a third end of the level shift subunit 133 is configured to output the fourth control signal 122, and a fourth end of the level shift subunit 133 is connected to the third output subunit 140.
The third output subunit 140 includes a power protection subunit 142, one end of the power protection subunit 142 is connected to the fourth end of the level shift subunit 133, and the other end of the power protection subunit 142 is configured to output the fifth control signal 141.
In this embodiment, the tenth switching tube MP10 is a PMOS tube, and the eleventh switching tube MN11 is an NMOS tube.
Specifically, the voltage domain of the first control signal 131 is [0, 1.65] V, and the voltage domain of the second control signal 132 is [1.65, 3.3] V. The first control signal 131 and the second control signal 132 are both high level or both low level, and the third control signal 121 and the fourth control signal 122 are opposite level. When the same level is high, the first control signal 131 is 1.65V, and the second control signal 132 is 3.3V; when the voltage level is low, the first control signal 131 is 0V, and the second control signal 132 is 1.65V.
It is understood that, when the first voltage source AVDD3318 is 3.3V and the second voltage source AVDD18 is 1.8V, the tenth switching tube MP10 and the eleventh switching tube MN11 are both closed, the first control signal 131 output by the second output subunit 130 is 1.65V, the second control signal 132 is 3.3V, the third control signal 121 output by the first output subunit 120 is 0V, the fourth control signal 122 is 1.8V, and the fifth control signal 141 output by the third output subunit 140 is 0V.
Further, when the first voltage source AVDD3318 is 3.3V and the second voltage source AVDD18 is 0V, the tenth switching tube MP10 and the eleventh switching tube MN11 are both closed, the first control signal 131 output by the second output subunit 130 is 1.65V, the second control signal 132 is 3.3V, the third control signal 121 output by the first output subunit 120 is 0V and the fourth control signal 122 is 0V, and the fifth control signal 141 output by the third output subunit 140 is 1.65V.
Furthermore, when the first voltage source AVDD3318 and the second voltage source AVDD18 are both 1.8V, the tenth switch MP10 and the eleventh switch MN11 are both turned on, the first control signal 131 output by the second output sub-unit 130 is 1.8V, the second control signal 132 is 0V, the third control signal 121 output by the first output sub-unit 120 is 1.8V, the fourth control signal 122 is 0V, and the fifth control signal 141 output by the third output sub-unit 140 is 0V.
It should be noted that, in this embodiment, the resistances of the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9 and the tenth resistor R10 may be the same or different, and are not limited herein.
In an alternative embodiment, the control unit 100 further includes a circuit protection subunit 150, and the circuit protection subunit 150 is used for protecting the control unit 100 and includes a twelfth switching tube MP12, a thirteenth switching tube MN13, and a fourteenth switching tube MP 14.
A first end of the twelfth switch tube MP12 is configured to be connected to the second voltage source AVDD18, a control end of the twelfth switch tube MP12 is configured to be connected to a third bias voltage VBQ, a second end of the twelfth switch tube MP12 is connected to a first end of the thirteenth switch tube MN13, a control end of the thirteenth switch tube MN13 is configured to be connected to the second voltage source AVDD18, and a second end of the thirteenth switch tube MN13 is connected to a control end of the tenth switch tube MP 10; the second end of the thirteenth switching tube MN13 is further connected to the first end of the fourteenth switching tube MP14, the control end of the fourteenth switching tube MP14 is configured to be connected to the second voltage source AVDD18, the second end of the fourteenth switching tube MP14 is connected to the second node 290 between the seventh resistor R7 and the eighth resistor R8, wherein the third bias voltage VBQ is a voltage of the third node 300 between the eighth resistor R8 and the ninth resistor R9.
In this embodiment, the twelfth switching tube MP12 and the fourteenth switching tube MP14 are both PMOS tubes, and the thirteenth switching tube MN13 is an NMOS tube. The circuit protection subunit 150 is configured to protect the control unit 100 from high voltage endurance when all the control unit 100 is a 1.8V low-voltage device.
In an alternative embodiment, each switching tube of the bias circuit 10 is a low-voltage device with a withstand voltage value less than or equal to 1.8V.
Specifically, the first switch tube MP1, the second switch tube MP2, the third switch tube MN3, the fourth switch tube MN4, the fifth switch tube MP5, the sixth switch tube MP6, the seventh switch tube MN7, the eighth switch tube MN8, the ninth switch tube MN9, the tenth switch tube MP10, the eleventh switch tube MN11, the twelfth switch tube MP12, the thirteenth switch tube MN13 and the fourteenth switch tube MP14 are all low-voltage devices.
It can be understood that the bias unit controls the on-off of the switch tube in each sub-unit according to the control signal provided by the control unit, so that the first voltage source connected with the bias unit is reduced to the first bias voltage and the second bias voltage and then output. Namely, the bias circuit provided by the application not only can use a low-voltage device to realize high voltage resistance, but also can be compatible with the application occasions of a driving circuit of 1.8V and 3.3V. That is to say, no matter the bias circuit is connected with a high-voltage source of 3.3V or a low-voltage source of 1.8V, the output first bias voltage and the second bias voltage are both in the interval of [0, 1.8] V, so that a low-voltage device is protected. Meanwhile, the power-on sequence of the voltage source does not influence the generation of the first bias voltage and the second bias voltage, the output of the first bias voltage and the output of the second bias voltage are slightly influenced by the manufacturing of the process, and the practicability is high.
The embodiment of the application provides a bias circuit, which comprises a first voltage source, a control unit and a bias unit, wherein the bias unit is connected with the first voltage source and the control unit, the bias unit comprises a preset number of load circuits connected in parallel, and each load circuit consists of at least one on-off circuit; the control unit is used for providing a control signal; the bias unit is used for controlling the on-off state of each on-off circuit under the action of the control signal, so that the voltage of each load circuit is controlled, and the bias voltage lower than a preset voltage value is output. The bias circuit can be compatible with the application occasions of 1.8V and 3.3V of the driving circuit, provides a proper static working point and ensures the high voltage resistance of the device.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, each functional module or unit in each embodiment of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, and various media capable of storing program codes.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application.
Claims (11)
1. A bias circuit is characterized by comprising a first voltage source, a control unit and a bias unit, wherein the bias unit is connected with the first voltage source and the control unit, the bias unit comprises a preset number of load circuits connected in parallel, and each load circuit is composed of at least one on-off circuit;
the control unit is used for providing a control signal;
the bias unit is used for controlling the on-off state of each on-off circuit under the action of the control signal, further controlling the voltage of each load circuit and outputting a bias voltage lower than a preset voltage value.
2. The bias circuit of claim 1, wherein the bias unit comprises a first load circuit, a second load circuit, and a third load circuit connected in parallel, and a fourth load circuit;
the first load circuit comprises a first on-off circuit and a second on-off circuit which are connected in series, the second load circuit comprises a third on-off circuit and a fourth on-off circuit which are connected in series, the third load circuit comprises a fifth on-off circuit and a sixth on-off circuit, the fourth load circuit comprises a seventh on-off circuit, the seventh on-off circuit is connected with the second on-off circuit in parallel, and the third on-off circuit is connected with the fifth on-off circuit in parallel;
the bias unit is used for regulating the output voltage of the first voltage source into a first bias voltage and a second bias voltage and then outputting the first bias voltage and the second bias voltage, wherein the first bias voltage is the node voltage between the first on-off circuit and the second on-off circuit, and the second bias voltage is the node voltage between the third on-off circuit and the fourth on-off circuit.
3. The bias circuit of claim 2, wherein the control signal output by the control unit comprises a first control signal, a second control signal, a third control signal, a fourth control signal, and a fifth control signal;
the first on-off circuit is connected with the first control signal and is switched off or switched on according to the first control signal;
the third breaking circuit is used for connecting the first control end and breaking or conducting according to a level signal sent by the first control end;
the fifth on-off circuit comprises a first switch tube and a second switch tube, the first switch tube is connected with the second switch tube in series, the first switch tube is connected with the second control signal and is opened or closed according to the second control signal, and the second switch tube is connected with the first control end and is opened or closed according to the level signal sent by the first control end;
the seventh on-off circuit comprises a third switching tube and a fourth switching tube, the third switching tube and the fourth switching tube are connected in series, the third switching tube is used for being connected with a second control end and is opened or closed according to a level signal sent by the second control end, and the fourth switching tube is connected with the third control signal and is opened or closed according to the third control signal;
the second on-off circuit is used for being connected with the second control end and is switched off or on according to a level signal sent by the second control end;
the fourth breaking circuit is connected with the fourth control signal and is broken or conducted according to the fourth control signal;
the sixth on-off circuit is connected with the fifth control signal and is turned off or turned on according to the fifth control signal.
4. The bias circuit according to claim 3, wherein the first on-off circuit comprises a fifth switching tube and a first resistor, a first end of the fifth switching tube is configured to be connected to the first voltage source, a control end of the fifth switching tube is configured to receive the first control signal, and a second end of the fifth switching tube is connected to the second on-off circuit through the first resistor.
5. The bias circuit according to claim 3, wherein the third cut-off circuit comprises a sixth switching tube and a second resistor, a first end of the sixth switching tube is configured to be connected to the first voltage source, a control end of the sixth switching tube is configured to be connected to the first control end, and a second end of the sixth switching tube is connected to the fourth cut-off circuit through the second resistor.
6. The bias circuit according to claim 3, wherein a first terminal of the first switch tube is configured to be connected to the first voltage source, a control terminal of the first switch tube is configured to be connected to the second control signal, a second terminal of the first switch tube is connected to a first terminal of the second switch tube, a control terminal of the second switch tube is configured to be connected to the first control terminal, and a second terminal of the second switch tube is configured to be connected to the sixth on/off circuit.
7. The bias circuit according to claim 3, wherein a first terminal of the third switching tube is connected to the first on-off circuit, a control terminal of the third switching tube is connected to the second control terminal, a second terminal of the third switching tube is connected to a first terminal of the fourth switching tube, a control terminal of the fourth switching tube is connected to the third control signal, and a second terminal of the fourth switching tube is grounded.
8. The bias circuit according to claim 3, wherein the second open circuit comprises a third resistor and a seventh switch tube, one end of the third resistor is connected to the first open circuit, the other end of the third resistor is connected to a first end of the seventh switch tube, a control end of the seventh switch tube is connected to the second control end, and a second end of the seventh switch tube is grounded.
9. The bias circuit according to claim 3, wherein the fourth breaking circuit includes a fourth resistor and an eighth switching tube, one end of the fourth resistor is connected to the third breaking circuit, the other end of the fourth resistor is connected to the first end of the eighth switching tube, the control end of the eighth switching tube is configured to access the fourth control signal, and the second end of the eighth switching tube is grounded.
10. The bias circuit according to claim 3, wherein the sixth on-off circuit includes a fifth resistor and a ninth switching tube, one end of the fifth resistor is connected to the fifth on-off circuit, the other end of the fifth resistor is connected to the first end of the ninth switching tube, the control end of the ninth switching tube is configured to receive the fifth control signal, and the second end of the ninth switching tube is grounded.
11. The bias circuit of claim 3, wherein the control unit comprises a power supply detection subunit, a first output subunit, a second output subunit, and a third output subunit; the power supply detection subunit is configured to detect a first voltage source and a second voltage source connected to the control unit, the first output subunit is configured to output the first control signal and the third control signal, the second output subunit is configured to output the second control signal and the fourth control signal, and the third output subunit is configured to output the fifth control signal;
the power supply detection subunit comprises a tenth switching tube, an eleventh switching tube, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor, a first end of the tenth switching tube is used for connecting the first voltage source, a control end of the tenth switching tube is used for connecting the second voltage source, a second end of the tenth switching tube is grounded through the sixth resistor, the seventh resistor, the eighth resistor and the ninth resistor in sequence, a first end of the eleventh switch tube is connected to one end of the tenth resistor, and the other end of the tenth resistor is used for connecting the second voltage source, the first end of the eleventh switching tube is further connected with the first output subunit, the control end of the eleventh switching tube is connected with a third node between the sixth resistor and the seventh resistor, and the second end of the eleventh switching tube is grounded;
the first output subunit comprises a first inverter, a second inverter and a third inverter, one end of the first inverter is connected with the first end of the eleventh switching tube, the other end of the first inverter is connected with one end of the second inverter, the other end of the second inverter is used for outputting the first control signal, the other end of the second inverter is further connected with one end of the third inverter, and the other end of the third inverter is used for outputting the third control signal;
the second output subunit includes a level shift subunit, a first end of the level shift subunit is connected to the other end of the first inverter, a second end of the level shift subunit is configured to output the second control signal, a third end of the level shift subunit is configured to output the fourth control signal, and a fourth end of the level shift subunit is connected to the third output subunit;
the third output subunit includes a power protection subunit, one end of the power protection subunit is connected to the fourth end of the level shift subunit, and the other end of the power protection subunit is configured to output the fifth control signal.
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| CN202210378622.2A CN114661649A (en) | 2022-04-12 | 2022-04-12 | Bias circuit |
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| CN202210378622.2A CN114661649A (en) | 2022-04-12 | 2022-04-12 | Bias circuit |
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