CN112614528A

CN112614528A - Power-down protection circuit and power-down detection circuit thereof

Info

Publication number: CN112614528A
Application number: CN202011457526.4A
Authority: CN
Inventors: 王钊
Original assignee: Hefei Zhonggan Micro Electronic Co ltd
Current assignee: Hefei Zhonggan Micro Electronic Co ltd
Priority date: 2020-12-10
Filing date: 2020-12-10
Publication date: 2021-04-06

Abstract

The invention provides a power failure protection circuit and a power failure detection circuit thereof, wherein the power failure detection circuit comprises: a detection terminal connected to a power supply voltage of the flash memory circuit; an output terminal connected to the flash memory circuit; the power failure detection circuit is used for judging whether the flash memory circuit has power failure or not by detecting the power supply voltage of the flash memory circuit, judging that the power failure occurs by the power failure detection circuit when the power supply voltage is smaller than a first turning threshold value, outputting a first level through an output end Write and informing the flash memory circuit of forbidding Write operation; and when the power supply voltage is greater than a second turnover threshold value, the power failure detection circuit judges that power failure does not occur, outputs a second level through an output end Write and informs the flash memory circuit of allowing Write operation. Compared with the prior art, the method can detect whether the flash memory circuit is powered down and quickly forbid write operation when the flash memory circuit is powered down, thereby improving the service life of the flash memory circuit.

Description

Power-down protection circuit and power-down detection circuit thereof

[ technical field ] A method for producing a semiconductor device

The invention relates to the field of integrated circuits, in particular to a power failure protection circuit and a power failure detection circuit thereof.

[ background of the invention ]

Flash memory circuits (flash memories) are a form of electrically erasable programmable read-only memory that allows the memory to be erased or written to multiple times during operation. This technology is mainly used for general data storage and data exchange between computers and other digital products, such as memory cards and usb disks. At present, Flash memory circuits (Flash memories) are adopted in more and more systems, but the Flash memories are easy to be damaged.

Therefore, there is a need to provide a new technical solution to overcome the above problems.

[ summary of the invention ]

The invention aims to provide a power failure protection circuit and a power failure detection circuit thereof, which can detect whether a flash memory circuit has power failure or not and quickly forbid write operation when the flash memory circuit has the power failure, thereby prolonging the service life of the flash memory circuit.

According to one aspect of the present invention, there is provided a power down detection circuit comprising: a detection terminal connected to a power supply voltage of the flash memory circuit; an output terminal connected to the flash memory circuit; the power failure detection circuit is used for judging whether the flash memory circuit has power failure or not by detecting the power supply voltage of the flash memory circuit, judging that the power failure occurs by the power failure detection circuit when the power supply voltage is smaller than a first turning threshold value, outputting a first level through an output end Write and informing the flash memory circuit of forbidding Write operation; and when the power supply voltage is greater than a second turnover threshold value, the power failure detection circuit judges that power failure does not occur, outputs a second level through an output end Write and informs the flash memory circuit of allowing Write operation.

Further, the first flipping threshold is equal to a second flipping threshold; or the first turning threshold value is not equal to the second turning threshold value, when the power supply voltage is smaller than the first turning threshold value from a value larger than the first turning threshold value, the power failure detection circuit judges that power failure occurs, and the output of the output end Write is turned from the second level to the first level; when the power supply voltage is larger than a second turnover threshold value from a value smaller than the second turnover threshold value, the power failure detection circuit judges that power failure does not occur, and the output of the output end Write is turned over from a first level to a second level.

Furthermore, the power-down detection circuit further comprises a resistor R2, a resistor R3, a resistor R4, a first transistor and a second transistor, wherein one end of the resistor R2 is connected with the detection end of the power-down detection circuit, and the other end of the resistor R2 is connected with a first connection node A; the first connection end of the first transistor is connected with the first connection node A through the resistor R3, the second connection end of the first transistor is connected with the grounding end, and the control end of the first transistor is connected with the first connection end of the first transistor; one end of the resistor R4 is connected with the detection end of the power failure detection circuit, and the other end of the resistor R4 is connected with a second connection node B; the first connection end of the second transistor is connected with a second connection node B, the control end of the second transistor is connected with the first connection node A, and the second connection end of the second transistor is connected with the grounding end; and the second connecting node B is connected with the output end Write of the power failure detection circuit.

Further, the first transistor and the second transistor are NMOS transistors MN1 and MN2, and the first connection end, the second connection end, and the control end of the first transistor are respectively a drain, a source, and a gate of the NMOS transistor MN 1; the first connecting end, the second connecting end and the control end of the second transistor are respectively a drain electrode, a source electrode and a grid electrode of the NMOS transistor MN 2.

Further, the width-to-length ratio of the NMOS transistor MN1 is greater than the width-to-length ratio of the NMOS transistor MN 2; the difference delta Vgs between the gate-source voltage of the NMOS transistor MN2 and the gate-source voltage of MN1 is a positive temperature coefficient voltage; the threshold voltage Vth of the NMOS transistor MN1 is a negative temperature coefficient voltage.

Further, the first transistor and the second transistor are NPN bipolar transistors NPN1 and NPN2, and the first connection end, the second connection end and the control end of the first transistor are collector, emitter and base of an NPN bipolar transistor NPN1, respectively; the first connecting end, the second connecting end and the control end of the second transistor are respectively a drain electrode, a source electrode and a grid electrode of the NMOS transistor MN 2.

Further, the emitter area of the NPN bipolar transistor NPN1 is larger than the emitter area of the NPN bipolar transistor NPN 2; the difference delta Vbe between the base-emitter voltage of the NPN bipolar transistor NPN2 and the base-emitter voltage of the NPN1 is positive temperature coefficient voltage; the base-emitter voltage Vbe1 of the NPN bipolar transistor NPN1 is a negative temperature coefficient voltage.

Furthermore, the power-down detection circuit further comprises a resistor R1 and a switch, wherein one end of the resistor R1 is connected with the detection end of the power-down detection circuit, and the other end of the resistor R1 is connected with one end of the resistor R2; one end of the switch MP1 is connected to one end of the resistor R1, and the other end thereof is connected to the other end of the resistor R1, and when the output terminal Write of the power down detection circuit outputs the first level, the switch MP1 is turned off; when the output terminal Write of the power down detection circuit outputs the second level, the switch MP1 is turned on.

Further, the switch is a PMOS transistor MP1, and one end, the other end, and the control end of the switch are respectively a source, a drain, and a gate of the PMOS transistor MP 1.

Furthermore, the power failure detection circuit further comprises a first inverter and a second inverter, wherein the input end of the first inverter is connected with the second connection node B, and the output end of the first inverter is connected with the output end Write of the power failure detection circuit; the input end of the second inversion is connected with the output end Write of the power failure detection circuit, and the output end of the second inversion is connected with the grid of the PMOS transistor MP 1.

Further, the first inverter includes a PMOS transistor MP2 and an NMOS transistor MN3, a source of the PMOS transistor MP2 is connected to the detection end of the power down detection circuit, a gate thereof is connected to the input end of the first inverter, a drain thereof is connected to the drain of the NMOS transistor MN3, a gate of the NMOS transistor MN3 is connected to the input end of the first inverter, and a source of the NMOS transistor MN3 is connected to the ground end; the second inverter comprises a PMOS transistor MP3 and an NMOS transistor MN4, the source electrode of the PMOS transistor MP3 is connected with the detection end of the power failure detection circuit, the grid electrode of the PMOS transistor MP3 is connected with the input end of the second inverter, the drain electrode of the PMOS transistor MP3 is connected with the drain electrode of the NMOS transistor MN4, the grid electrode of the NMOS transistor MN4 is connected with the input end of the second inverter, and the source electrode of the NMOS transistor MN4 is connected with the grounding end.

According to another aspect of the present invention, there is provided a power down protection circuit including a flash memory circuit and a power down detection circuit, the power down detection circuit including: a detection terminal connected to a power supply voltage of the flash memory circuit; an output terminal connected to the flash memory circuit; the power failure detection circuit is used for judging whether the flash memory circuit has power failure or not by detecting the power supply voltage of the flash memory circuit, judging that the power failure occurs by the power failure detection circuit when the power supply voltage is smaller than a first turning threshold value, outputting a first level through an output end Write and informing the flash memory circuit of forbidding Write operation; and when the power supply voltage is greater than a second turnover threshold value, the power failure detection circuit judges that power failure does not occur, outputs a second level through an output end Write and informs the flash memory circuit of allowing Write operation.

Compared with the prior art, the method and the device judge whether the flash memory circuit is powered down or not by detecting the power supply voltage of the flash memory circuit, judge that the power down occurs if the power supply voltage of the flash memory circuit is reduced to a certain threshold value, and inform the flash memory circuit of prohibiting the write operation, thereby improving the service life of the flash memory circuit.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise. Wherein:

FIG. 1 is a functional block diagram of a power down protection circuit in one embodiment of the present invention;

FIG. 2 is a circuit schematic of the power down detection circuit shown in FIG. 1 in one embodiment;

fig. 3 is a circuit schematic diagram of the power down detection circuit shown in fig. 1 in another embodiment.

[ detailed description ] embodiments

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Unless otherwise specified, the terms connected, and connected as used herein mean electrically connected, directly or indirectly.

The inventor finds through a great deal of experiments and analyses that one of the main causes of the vulnerability of the flash memory circuit is: flash memory circuits are suddenly powered down and are susceptible to damage if the flash memory circuit is being written to. Based on the power failure protection circuit and the power failure detection circuit thereof, the invention can detect whether the flash memory circuit has power failure or not, and quickly forbids write operation when the flash memory circuit has the power failure, thereby improving the service life of the flash memory circuit.

Referring to fig. 1, a functional block diagram of a power down protection circuit according to an embodiment of the invention is shown. The power down protection circuit shown in fig. 1 includes a power down detection circuit 110 and a flash memory circuit 120.

The detection terminal of the power down detection circuit 110 is connected to the power supply voltage VDD of the flash memory circuit 120, the ground terminal G thereof is grounded, and the output terminal Write thereof is connected to the flash memory circuit 120. A first flipping threshold and a second flipping threshold are set in the power failure detection circuit 110.

The power down detection circuit 110 is used to determine whether the flash memory circuit 120 is powered down by detecting the power supply voltage VDD of the flash memory circuit 120. When the power supply voltage VDD of the flash memory circuit 120 drops and is lower than a first flipping threshold (for example, the first flipping threshold may be set to be 0.85 times of the normal operating voltage of the flash memory circuit 120), the power down detection circuit 110 determines that power down occurs (or determines that power down occurs in the flash memory circuit 120), and outputs a first level (for example, the first level is a low level) through the output terminal Write, and notifies the flash memory circuit 120 of inhibiting the Write operation; when the power supply voltage VDD of the flash memory circuit 120 rises and exceeds the second switching threshold, the power down detection circuit 110 determines that power is not turned off (or determines that the flash memory circuit 120 is not turned off), and outputs a second level (for example, the second level is a high level) through the output terminal Write, informing the flash memory circuit 120 that the Write operation is allowed. That is, when the power supply voltage VDD becomes smaller than the first inversion threshold from being larger than the first inversion threshold, the power down detection circuit 110 determines that power down occurs, and the output of the output terminal Write is inverted from the second level to the first level; when the power supply voltage VDD becomes larger than the second flipping threshold from being smaller than the second flipping threshold, the power down detection circuit 110 determines that power is not turned off, and the output of the output terminal Write is flipped from the first level to the second level.

In one embodiment, the first flipping threshold is equal to the second flipping threshold. In another embodiment, there is a difference between the first and second flipping thresholds, and this difference voltage is the hysteresis voltage.

Referring to fig. 2, a circuit diagram of the power down detection circuit 110 shown in fig. 1 in one embodiment is shown. The power down detection circuit shown in fig. 2 includes: resistors R1, R2, R3 and R4, PMOS transistors MP1, MP2 and MP3, and NMOS transistors MN1, MN2, MN3 and MN 4.

The following describes specific connection relationships among the devices in the power down detection circuit shown in fig. 2.

One end of the resistor R1 is connected to the detection terminal of the power down detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), the other end thereof is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the first connection node a; the drain of the NMOS transistor MN1 is connected to the first connection node a via a resistor R3, the source thereof is connected to the ground terminal G of the power-down detection circuit 110, and the gate thereof is connected to the drain thereof; one end of the resistor R4 is connected to the detection terminal of the power-down detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), and the other end thereof is connected to the second connection node B; the drain of the NMOS transistor MN2 is connected to the second connection node B, the gate thereof is connected to the first connection node a, and the source thereof is connected to the ground terminal G of the power-down detection circuit 110.

The PMOS transistor MP2 and the NMOS transistor MN3 constitute a first inverter 210, and the input terminal of the first inverter 210 is connected to the second connection node B, and the output terminal thereof is connected to the output terminal Write of the power down detection circuit 110. The source of the PMOS transistor MP2 is connected to the detection terminal of the power down detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), the gate thereof is connected to the input terminal of the first inverter 210 (or the second connection node B), the drain thereof is connected to the drain of the NMOS transistor MN3, the gate of the NMOS transistor MN3 is connected to the input terminal of the first inverter 210 (or the second connection node B), and the source of the NMOS transistor MN3 is connected to the ground terminal G of the power down detection circuit 110.

The PMOS transistor MP3 and the NMOS transistor MN4 constitute a second inverter 220, the input terminal of the second inverter 220 is connected to the output terminal Write of the power down detection circuit 110 (or the output terminal of the first inverter 210), and the output terminal thereof is connected to the gate of the PMOS transistor MP 1. The source of the PMOS transistor MP3 is connected to the detection terminal of the power down detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), the gate thereof is connected to the input terminal of the second inverter 220 (or the output terminal Write of the power down detection circuit 110), the drain thereof is connected to the drain of the NMOS transistor MN4, the gate of the NMOS transistor MN4 is connected to the input terminal of the second inverter 220 (or the output terminal Write of the power down detection circuit 110), and the source of the NMOS transistor MN4 is connected to the ground terminal G of the power down detection circuit 110.

The source of the PMOS transistor MP1 is connected to one end of the resistor R1, and the drain thereof is connected to the other end of the resistor R1.

The operation of the power down detection circuit shown in fig. 2 is described in detail below.

The width-to-length ratio of the NMOS transistor MN1 is designed to be relatively large, the width-to-length ratio of the NMOS transistor MN2 is designed to be relatively small, and the width-to-length ratio of the NMOS transistor MN1 may be larger than the width-to-length ratio of the NMOS transistor MN 2.

The current IR3 flowing through the resistor R3 satisfies:

IR3＝(VDD-Vth)/(R1+R2+R3)

where VDD is the power voltage of the flash memory circuit 120, Vth is the threshold voltage of the NMOS transistor MN1, R1 is the resistance of the resistor R1, R2 is the resistance of the resistor R2, and R3 is the resistance of the resistor R3.

The voltage VR3 across the resistor R3 satisfies:

VR3＝(VDD-Vth).R3/(R1+R2+R3) (1)

due to the different design of the width-to-length ratios of the NMOS transistors MN2 and MN1, when the same current flows through the NMOS transistors MN2 and MN1, the difference Δ Vgs between the gate-source voltages of the NMOS transistors and MN 3526 is a certain difference, and MN2 pulls the drain voltage to the ground level when the following conditions are satisfied:

VR3+ Vgs1> Vgs2, where Vgs1 is the gate-source voltage of NMOS transistor MN1, Vgs2 is the gate-source voltage of NMOS transistor MN2,

therefore, the condition for generating the drain voltage flip of MN2 is VR3+ Vgs 1-Vgs 2

I.e. VR3 Vgs2-Vgs1 Δ Vgs (2)

Wherein, Δ Vgs is the difference between the gate-source voltage of the NMOS transistor MN2 and the gate-source voltage of MN1,

substituting equation (1) to equation (2) yields:

(VDD-Vth).R3/(R1+R2+R3)＝ΔVgs

solving to obtain:

VDD＝ΔVgs.(R1+R2+R3)/R3+Vth (3)

the value of VDD is a condition for causing the drain voltage of the NMOS transistor MN2 to flip, and when the power supply voltage VDD of the flash memory circuit 120 is greater than this value, the drain voltage of the NMOS transistor MN2 is at a low level, which causes the output signal Write to be at a high level through the first inverter 210; when the power supply voltage VDD of the flash memory circuit 120 is smaller than this value, the drain voltage of the NMOS transistor MN2 is high, resulting in the output signal Write being low through the first inverter 210. The difference Δ Vgs between the gate-source voltage of the NMOS transistor MN2 and the gate-source voltage of MN1 is a positive temperature coefficient voltage, and the threshold voltage Vth of the NMOS transistor MN1 is a negative temperature coefficient voltage, so that a suitable ratio of (R1+ R2+ R3)/R3 can be designed to realize temperature compensation, thereby realizing a relatively stable switching threshold value close to a zero temperature coefficient.

The PMOS transistor MP1 is used as a switch to form a positive feedback, which functions to generate a small hysteresis voltage to prevent the output signal Write from being unstable when the power supply voltage VDD of the flash circuit 120 is affected by noise and is close to the switching threshold. The hysteresis voltage means: when the power supply voltage VDD drops from a high voltage and is lower than a first flipping threshold, the output signal Write changes from a high level to a low level; when the power supply voltage VDD rises from a low voltage and exceeds the second switching threshold, the output signal Write changes from a low level to a high level, and there is a difference between the first switching threshold and the second switching threshold, which is a hysteresis voltage.

When the output signal Write is at a high level (which may be referred to as a second level), the gate of the PMOS transistor MP1 is at a low level via the second inverter 220, the PMOS transistor MP1 is turned on, and the resistor R1 is short-circuited, as can be seen from the foregoing derivation, at this time, the toggling threshold of the power down detection circuit 110 is the first toggling threshold:

VDD＝ΔVgs.(R2+R3)/R3+Vth (4)

if the power supply voltage VDD drops from a high voltage and is lower than the first inversion threshold, the output signal Write changes from a high level to a low level, i.e., the power down detection circuit 110 determines that power down occurs and outputs a low level (which may be referred to as a first level) through the output terminal Write, informing the flash memory circuit 120 that the Write operation is disabled.

When the output signal Write is at a low level (which may be referred to as a first level), the gate of the PMOS transistor MP1 is at a high level via the second inverter 220, and the PMOS transistor MP1 is turned off, as can be seen from the foregoing derivation, the switching threshold of the power down detection circuit 110 is the second switching threshold:

VDD＝ΔVgs.(R1+R2+R3)/R3+Vth (3)

if the power supply voltage VDD rises from a low voltage and is higher than the second switching threshold, the output signal Write changes from a low level to a high level, i.e., the power down detection circuit 110 determines that power is not turned off and outputs a high level (which may be referred to as a second level) through the output terminal Write, informing the flash memory circuit 120 that the Write operation is allowed.

Referring to fig. 3, a circuit diagram of the power down detection circuit 110 shown in fig. 1 in another embodiment is shown. In comparison with fig. 2, NMOS transistors MN1 and MN2 are replaced with NPN bipolar transistors NPN1 and NPN2, respectively. The power down detection circuit shown in fig. 3 includes: resistors R1, R2, R3 and R4, PMOS transistors MP1, MP2 and MP3, NMOS transistors MN3 and MN4, and NPN bipolar transistors NPN1 and NPN 2.

The following describes specific connection relationships among the devices in the power down detection circuit shown in fig. 3.

One end of the resistor R1 is connected to the detection terminal of the power down detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), the other end thereof is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the first connection node a; the collector of the NPN bipolar transistor NPN1 is connected to the first connection node a via a resistor R3, the emitter thereof is connected to the ground terminal G of the power-down detection circuit 110, and the base thereof is connected to the collector thereof; one end of the resistor R4 is connected to the detection terminal of the power-down detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), and the other end thereof is connected to the second connection node B; the NPN bipolar transistor NPN2 has a collector connected to the second connection node B, a base connected to the first connection node a, and an emitter connected to the ground G of the power down detection circuit 110.

The operation of the power down detection circuit shown in fig. 3 is described in detail below.

The emitter area of the NPN bipolar transistor NPN1 is designed to be relatively large, the emitter area of the NPN bipolar transistor NPN2 is designed to be relatively small, and the emitter area of the NPN bipolar transistor NPN1 may be said to be larger than the emitter area of the NPN bipolar transistor NPN 2.

The current IR3 flowing through the resistor R3 satisfies:

IR3＝(VDD-Vbe1)/(R1+R2+R3)

wherein VDD is the power voltage of the flash memory circuit 120, Vbe1 is the base-emitter voltage of NPN bipolar transistor NPN1, R1 is the resistance of resistor R1, R2 is the resistance of resistor R2, and R3 is the resistance of resistor R3.

The voltage VR3 across the resistor R3 satisfies:

VR3＝(VDD-Vbe1).R3/(R1+R2+R3) (5)

due to the difference of emitter area designs of the NPN bipolar transistors NPN1 and NPN2, when the two transistors pass through the same current, a certain base-emitter voltage difference Δ Vbe exists, and the NPN2 pulls the collector voltage to the ground level when the following conditions are met:

VR3+ Vbe1> Vbe2, where Vbe1 is the base-emitter voltage of the NPN bipolar transistor NPN1, Vbe2 is the base-emitter voltage of the NPN bipolar transistor NPN2,

thus, the condition for generating the collector voltage flip for the NPN2 is VR3+ Vbe 1-Vbe 2

I.e. VR3 Vbe2-Vbe1 Δ Vbe (6)

Wherein Δ Vbe is the difference between the base-emitter voltage of NPN bipolar transistor NPN2 and the base-emitter voltage of NPN1,

substituting equation (5) to equation (6) yields:

(VDD-Vbe1).R3/(R1+R2+R3)＝ΔVbe

solving to obtain:

VDD＝ΔVbe.(R1+R2+R3)/R3+Vbe1 (7)

the value of VDD is a condition for causing the collector voltage of NPN bipolar transistor NPN2 to flip, and when the power voltage VDD of flash circuit 120 is greater than this value, the collector voltage of NPN bipolar transistor NPN2 is at a low level, and the output signal Write is at a high level through first inverter 210; when the power supply voltage VDD of the flash memory circuit 120 is less than this value, the collector voltage of the NPN bipolar transistor NPN2 is high, resulting in the output signal Write being low through the first inverter 210. The difference delta Vbe between the base-emitter voltage of the NPN bipolar transistor NPN2 and the base-emitter voltage of the NPN1 is positive temperature coefficient voltage, and the base-emitter voltage Vbe1 of the NPN bipolar transistor NPN1 is negative temperature coefficient voltage, so that a proper ratio (R1+ R2+ R3)/R3 can be designed to realize temperature compensation, and therefore a relatively stable overturning threshold value close to zero temperature coefficient is realized.

VDD＝ΔVbe.(R2+R3)/R3+Vbe1 (8)

VDD＝ΔVbe.(R1+R2+R3)/R3+Vbe1 (7)

It should be noted that, in another embodiment, the second inverter 220, the resistor R2 and the PMOS transistor MP1 in fig. 2 or fig. 3 may be omitted, so that the first and second flipping thresholds are equal, i.e., there is no hysteresis voltage.

It should be noted that the NMOS transistors MN1 and NPN, and the NPN bipolar transistors NPN1 and NPN2 may be collectively referred to as transistors, wherein the NMOS transistor MN1 and the NPN bipolar transistor NPN1 are referred to as a first transistor, and the NMOS transistor MN2 and the NPN bipolar transistor NPN2 are referred to as a second transistor. In the embodiment shown in fig. 2, the first transistor and the second transistor are NMOS transistors MN1 and MN2, and the first connection terminal, the second connection terminal and the control terminal of the first transistor are the drain, the source and the gate of the NMOS transistor MN1, respectively; the first connecting end, the second connecting end and the control end of the second transistor are respectively a drain electrode, a source electrode and a grid electrode of the NMOS transistor MN 2. In the embodiment shown in fig. 3, the first transistor and the second transistor are NPN bipolar transistors NPN1 and NPN2, and the first connection terminal, the second connection terminal and the control terminal of the first transistor are collector, emitter and base of an NPN bipolar transistor NPN1, respectively; the first connecting end, the second connecting end and the control end of the second transistor are respectively a drain electrode, a source electrode and a grid electrode of the NMOS transistor MN 2.

In fig. 2 and 3, the PMOS transistor MP1 is used as a switch, and one end, the other end, and the control end of the switch are the source, the drain, and the gate of the PMOS transistor MP1, respectively. In other embodiments, the PMOS transistor MP1 may be replaced with another kind of switch as long as the switch is turned off when the output terminal Write of the power down detection circuit outputs the first level; when the output end Write of the power failure detection circuit outputs the second level, the switch is conducted.

In summary, the power down detection circuit 110 in the present invention determines whether the flash memory circuit 120 has a power down by detecting the power supply voltage VDD of the flash memory circuit 120, and when the power supply voltage VDD is smaller than the first flipping threshold, the power down detection circuit 110 determines that the power down occurs, and outputs the first level through the output terminal Write to notify the flash memory circuit 120 of prohibiting the Write operation; when the power supply voltage VDD is greater than the second switching threshold, the power failure detection circuit 110 determines that power is not lost, and outputs the second level through the output terminal Write, and notifies the flash memory circuit 120 of allowing a Write operation, thereby improving the life of the flash memory circuit.

In the present invention, the terms "connected", "connecting", and the like mean electrical connections, and direct or indirect electrical connections unless otherwise specified.

It should be noted that those skilled in the art can make modifications to the embodiments of the present invention without departing from the scope of the appended claims. Accordingly, the scope of the appended claims is not to be limited to the specific embodiments described above.

Claims

1. A power down detection circuit, comprising:

a detection terminal connected to a power supply voltage of the flash memory circuit;

an output terminal connected to the flash memory circuit;

the power failure detection circuit is used for judging whether the flash memory circuit has power failure or not by detecting the power supply voltage of the flash memory circuit, judging that the power failure occurs by the power failure detection circuit when the power supply voltage is smaller than a first turning threshold value, outputting a first level through an output end Write and informing the flash memory circuit of forbidding Write operation; and when the power supply voltage is greater than a second turnover threshold value, the power failure detection circuit judges that power failure does not occur, outputs a second level through an output end Write and informs the flash memory circuit of allowing Write operation.

2. The power down detection circuit of claim 1,

the first rollover threshold is equal to a second rollover threshold; or

The first and second rollover thresholds are not equal,

when the power supply voltage is smaller than a first turning threshold value from a value larger than the first turning threshold value, the power failure detection circuit judges that power failure occurs, and the output of the output end Write is turned from a second level to a first level;

when the power supply voltage is larger than a second turnover threshold value from a value smaller than the second turnover threshold value, the power failure detection circuit judges that power failure does not occur, and the output of the output end Write is turned over from a first level to a second level.

3. The power down detection circuit of claim 1, further comprising a resistor R2, a resistor R3, a resistor R4, a first transistor, and a second transistor,

one end of the resistor R2 is connected with the detection end of the power failure detection circuit, and the other end of the resistor R2 is connected with a first connection node A; the first connection end of the first transistor is connected with the first connection node A through the resistor R3, the second connection end of the first transistor is connected with the grounding end, and the control end of the first transistor is connected with the first connection end of the first transistor; one end of the resistor R4 is connected with the detection end of the power failure detection circuit, and the other end of the resistor R4 is connected with a second connection node B; the first connection end of the second transistor is connected with a second connection node B, the control end of the second transistor is connected with the first connection node A, and the second connection end of the second transistor is connected with the grounding end; and the second connecting node B is connected with the output end Write of the power failure detection circuit.

4. The power down detection circuit of claim 3,

the first and second transistors are NMOS transistors MN1 and MN2,

the first connecting end, the second connecting end and the control end of the first transistor are respectively a drain electrode, a source electrode and a grid electrode of an NMOS transistor MN 1;

the first connecting end, the second connecting end and the control end of the second transistor are respectively a drain electrode, a source electrode and a grid electrode of the NMOS transistor MN 2.

5. The power down detection circuit of claim 3,

the width-to-length ratio of the NMOS transistor MN1 is larger than that of the NMOS transistor MN 2;

the difference delta Vgs between the gate-source voltage of the NMOS transistor MN2 and the gate-source voltage of MN1 is a positive temperature coefficient voltage;

the threshold voltage Vth of the NMOS transistor MN1 is a negative temperature coefficient voltage.

6. The power down detection circuit of claim 3,

the first and second transistors are NPN bipolar transistors NPN1 and NPN2,

the first connecting end, the second connecting end and the control end of the first transistor are respectively a collector, an emitter and a base of an NPN bipolar transistor NPN 1;

7. The power down detection circuit of claim 6,

the emitter area of the NPN bipolar transistor NPN1 is greater than the emitter area of NPN bipolar transistor NPN 2;

the difference delta Vbe between the base-emitter voltage of the NPN bipolar transistor NPN2 and the base-emitter voltage of the NPN1 is positive temperature coefficient voltage;

the base-emitter voltage Vbe1 of the NPN bipolar transistor NPN1 is a negative temperature coefficient voltage.

8. The power down detection circuit of claim 3, further comprising a resistor R1, and a switch,

one end of the resistor R1 is connected with the detection end of the power failure detection circuit, and the other end of the resistor R1 is connected with one end of the resistor R2;

one end of the switch MP1 is connected to one end of the resistor R1, and the other end thereof is connected to the other end of the resistor R1, and when the output terminal Write of the power down detection circuit outputs the first level, the switch MP1 is turned off; when the output terminal Write of the power down detection circuit outputs the second level, the switch MP1 is turned on.

9. The power down detection circuit of claim 8,

the switch is a PMOS transistor MP1,

one end, the other end and the control end of the switch are respectively a source electrode, a drain electrode and a grid electrode of the PMOS transistor MP 1.

10. The power down detection circuit of claim 9, further comprising a first inverter and a second inverter,

the input end of the first inversion is connected with the second connection node B, and the output end of the first inversion is connected with the output end Write of the power failure detection circuit;

the input end of the second inversion is connected with the output end Write of the power failure detection circuit, and the output end of the second inversion is connected with the grid of the PMOS transistor MP 1.

11. The power down detection circuit of claim 10,

the first inverter comprises a PMOS transistor MP2 and an NMOS transistor MN3, the source electrode of the PMOS transistor MP2 is connected with the detection end of the power failure detection circuit, the grid electrode of the PMOS transistor MP2 is connected with the input end of the first inverter, the drain electrode of the PMOS transistor MP2 is connected with the drain electrode of the NMOS transistor MN3, the grid electrode of the NMOS transistor MN3 is connected with the input end of the first inverter, and the source electrode of the NMOS transistor MN3 is connected with the ground end;

the second inverter comprises a PMOS transistor MP3 and an NMOS transistor MN4, the source electrode of the PMOS transistor MP3 is connected with the detection end of the power failure detection circuit, the grid electrode of the PMOS transistor MP3 is connected with the input end of the second inverter, the drain electrode of the PMOS transistor MP3 is connected with the drain electrode of the NMOS transistor MN4, the grid electrode of the NMOS transistor MN4 is connected with the input end of the second inverter, and the source electrode of the NMOS transistor MN4 is connected with the grounding end.

12. A power down protection circuit, comprising:

a flash memory circuit;

the power down detection circuit of any of claims 1-11.