JP5262082B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit configured to operate at a plurality of operating frequencies.

  Semiconductor integrated circuits are mounted on various electronic devices. In the case of a semiconductor integrated circuit mounted on an electronic device driven by a battery typified by a notebook computer or a mobile phone, a circuit design that requires low power consumption is required in order to extend the driving time by the battery as much as possible. Yes. As a measure for extending the driving time, a circuit design technique is employed in which the circuit is operated at different operating frequencies depending on the use of the semiconductor integrated circuit. Here, the circuit design technique for operating at different operating frequencies is a technique for designing a circuit so that one clock net operates at a plurality of frequencies.

  For example, when an application that requires high-speed operation is operated in an electronic device, the semiconductor integrated circuit is operated at a frequency of 100 MHz. When an ordinary application is operated, the semiconductor integrated circuit is operated at a frequency of 50 MHz, which is half. If the operating circuit parts are the same, the power consumption is reduced by operating at 50 MHz, which is half of that at 100 MHz. In this way, a device has been devised to extend the driving time by the battery as much as possible by changing the operating frequency according to the application of the semiconductor integrated circuit.

  A semiconductor integrated circuit in which one clock net has a plurality of operating frequencies needs to satisfy timing constraints for each operating frequency. Usually, since the timing constraint is severer at the higher operating frequency, the cell to be used is selected under the condition of the higher operating frequency. Thus, when viewed at a low operating frequency, the selected cell may appear to have excessive drive capability, i.e. performance.

  FIG. 1 is a diagram showing a clock net 1 having a plurality of operating frequencies, and FIG. 2 is a diagram showing a clock net 2 operating at a single operating frequency. For example, the clock net 1 in FIG. 1 can operate at an operating frequency of 100 MHz or 50 MHz. In FIG. 1 and FIG. 2, for convenience of explanation, the numbers shown in the cells 11 and 12 indicate the height of the driving capability in arbitrary units. The larger the number, the higher the driving capability, that is, the higher the power consumption. Shall.

  The configuration of the clock nets 1 and 2 shown in FIG. 1 and FIG. 2 is the same, but the cell 11 used in the clock net 1 in FIG. 1 and the cell 12 used in the clock net 2 in FIG. The driving ability is different. For this reason, even if the operating frequency is set to the same 50 MHz, the clock net 1 of FIG. 1 consumes more power than the clock net 2 of FIG. In order to avoid this problem, various semiconductor integrated circuits using a cell having a function capable of changing a driving capability (or performance) have been proposed.

  A cell having a function capable of changing the driving ability is roughly divided into two types. One is an exclusive type in which a plurality of transistor circuits having the same function and different driving capabilities are prepared, and one transistor circuit is selected by a control signal applied to a control terminal. The other is to prepare a plurality of transistor circuits having the same function (regardless of driving capability), one transistor circuit is always operated, and the remaining transistor circuits are as many as required by the control signal applied to the control terminal. Is a parallel type that operates by connecting them in parallel.

  FIG. 3 is a diagram conceptually showing the exclusive cell structure 15, and FIG. 4 is a diagram conceptually showing the parallel cell structure 16. In FIG. 3, 21 is a control terminal, 22 and 23 are circuits for selecting one from transistor circuits having different driving capabilities, and 24 is a transistor circuit having the same function and different driving capabilities. In FIG. 4, 31 is a control terminal, 32 and 33 are circuits for connecting transistor circuits as much as necessary to obtain a desired drive capability, and 34 is a transistor circuit having the same function and having no drive capability. Here, for convenience of explanation, it is assumed that the driving capability of the transistor circuit 34 is “1”.

An exclusive cell structure is proposed in, for example, Patent Document 1, Patent Document 2, and the like. A parallel type cell structure is proposed in, for example, Patent Document 3 and Patent Document 4.
JP 2005-318363 A JP-A-9-91056 JP 2003-318723 A JP-A-63-80622

  Since the exclusive cell structure includes a plurality of transistor circuits having the same function and different driving capabilities, the circuit scale becomes larger than that of the parallel cell structure.

  Further, in both the exclusive cell structure and the parallel cell structure, a dedicated control terminal is required.

  Further, in the case of the conventional exclusive cell structure and parallel cell structure, voltage is always applied from the power supply wiring to the transistor circuit that is not used, so even if the transistor circuit is in the off state. Because of the voltage applied from the power supply wiring, a potential difference is generated between the source and the drain, and a leak current flows. Although the leakage current in one cell is very small, the total leakage current becomes a non-negligible magnitude depending on the circuit scale of the semiconductor integrated circuit. The power consumption due to the leakage current becomes a cause of shortening the battery driving time particularly in the case of a portable device.

  Therefore, an object of the present invention is to provide a semiconductor integrated circuit that can realize low power consumption with a relatively small circuit scale and without providing a dedicated control terminal.

  The above-described problem is a semiconductor integrated circuit having an input terminal and an output terminal and operating at a plurality of operating frequencies, wherein the first logic circuit and the first logic circuit connected in parallel between the input terminal and the output terminal 2, and a first conduction control circuit connected between the second logic circuit and the output terminal, the first logic circuit always operating voltage from the first power supply system The second logic circuit is applied with an operating voltage or a ground voltage from a second power supply system according to the operating frequency, and the first conduction control circuit is supplied with a voltage from the second power supply system. The semiconductor integrated circuit is characterized in that the operation state and leakage current of some of the transistors in the second logic circuit are controlled by the voltage from the second power supply system.

  According to the present invention, it is possible to realize a semiconductor integrated circuit capable of realizing low power consumption with a relatively small circuit scale and without providing a dedicated control terminal.

  In the present invention, the transistor circuit in the semiconductor integrated circuit has a parallel cell structure or macro structure that operates in parallel as much as necessary according to the operating frequency. The power supply in the cell structure or the macro structure is divided into a plurality of power supply systems, and an operation voltage is always applied to one power supply system, and an operation voltage or a ground voltage is applied to the remaining power supply systems according to the operation frequency. However, the function of the cell structure or the macro structure is not changed even when a part of the transistor circuit becomes non-operating because the voltage becomes the ground voltage.

  Further, in order to prevent unnecessary leakage current from flowing between the transistor circuit section to which the operating voltage is constantly applied and the transistor circuit section to which the operating voltage or the ground voltage is applied according to the operating frequency, these transistor circuits. A conduction control circuit using a power supply net to which an operating voltage or a ground voltage is applied according to the operating frequency as a control signal is provided between the units. This conduction control circuit is provided only in the input part and output part in the cell structure or macro structure, or only in the output part.

  When the conduction control circuit is provided only at the output part in the cell structure or macro structure, the circuit scale can be reduced. However, since the input part is conductive, the gate oxide film of the transistor penetrates through the tunnel effect and the current flows. There is a possibility that a small amount of gate leakage current is generated due to the flow of. This gate leakage current is particularly noticeable in a fine technology.

  On the other hand, when the conduction control circuit is provided in both the input part and the output part in the cell structure or the macro structure, the circuit scale becomes larger than that in the former case, but the generation of the gate leakage current can be suppressed.

  FIG. 5 is a circuit diagram showing the main part of the first embodiment of the present invention. FIG. 5 shows a cell structure (or macro structure) 35-1 of a semiconductor integrated circuit having an inverter function and having two power supply systems. In this embodiment and each embodiment described later, for convenience of explanation, it is assumed that the semiconductor integrated circuit is a semiconductor integrated circuit having a configuration in which one clock net operates at a plurality of operating frequencies. This cell structure 35-1 has an input terminal 37, inverter circuit portions 41 and 42, a conduction control circuit 43, and an output terminal 38. In the cell structure 35-1 of FIG. 5, the inverter circuit section 41 has three P-channel transistors and three N-channel transistors connected as shown in the figure, and the inverter circuit 42 has four pieces connected as shown in the figure. The P-channel transistors and the four N-channel transistors are included, but the number, type, and connection of the transistors constituting each of the inverter circuit portions 41 and 42 are not limited to this. The inverter circuit unit 41 is connected to the power supply system VDD1, and the inverter circuit unit 42 is connected to the power supply system VDD2. The power supply system VDD1 always applies the operating voltage VDD as VDD1 to the cell structure 35-1. On the other hand, the power supply system VDD2 applies the operating voltage VDD or the ground voltage GND to the cell structure 35-1 as VDD2 in accordance with the operating frequency of the semiconductor integrated circuit.

  Between the inverter circuit unit 41 and the inverter circuit unit 42, a conduction control circuit 43 using a voltage from the power supply system VDD2 as a control signal is provided in the input unit and the output unit in the cell structure 35-1. The conduction control circuit 43 is controlled by the voltage VDD2 from the power supply system VDD2 and VDD2 * (VDD2 bar) which is an inverted voltage of the voltage VDD2. The voltage VDD2 * is obtained by inputting the voltage VDD2 to the inverter cell 44 of the power supply system VDD1. The inverter cell 44 that generates the voltage VDD2 * does not need to form part of the cell structure 35-1. This is because the control signal for the continuity control circuit 43 is actually input simultaneously to a plurality of cell structures, so that at least one inverter cell 44 for generating the voltage VDD2 * is provided in the semiconductor integrated circuit. Because it is good. That is, the inverter cell 44 may be provided inside the cell structure 35-1, or may be provided outside the cell structure 35-1.

  The power supply system VDD2 applies the operating voltage VDD when operating the semiconductor integrated circuit at a high operating frequency, and applies the ground voltage GND when operating the semiconductor integrated circuit at a low operating frequency. The high operating frequency and the low operating frequency are not limited to a specific frequency, and the high operating frequency only needs to be higher than the low operating frequency. When the semiconductor integrated circuit is operated at a high operating frequency, the power supply system VDD2 applies the operating voltage VDD, so that the inverter circuit unit 42 is in an operating state. Further, the conduction control circuit 43 becomes conductive by applying the operating voltage VDD. Thereby, all the transistors in the cell structure 35-1 are in an operating state, and an inverter cell in which seven P-channel transistors and seven N-channel transistors are connected in parallel is configured. When the semiconductor integrated circuit is operated at a low operating frequency, the power supply system VDD2 applies the ground voltage GND, so that the inverter circuit unit 42 becomes non-operating.

  By applying the ground voltage GND to the inverter circuit portion 42, no potential difference is generated between the source and drain of the transistor because there is no potential difference between the source and drain of the transistor regardless of the state of the gate of the transistor. Further, by applying the ground voltage GND from the power supply system VDD2 to the cell structure 35-1, the conduction control circuit 43 is turned off. As a result, only the transistor circuit section 41 in the cell is in an operating state, and an inverter cell in which three P-channel transistors and three N-channel transistors are connected in parallel is configured.

  FIG. 6 is a circuit diagram showing the main part of the second embodiment of the present invention. FIG. 6 shows a cell structure 35-2 of a semiconductor integrated circuit having an inverter function and having three power supply systems. In FIG. 6, the same parts as those in FIG. This cell structure 35-2 has an input terminal 37, inverter circuit portions 41, 42, 51, conduction control circuits 43, 53 and an output terminal 38.

  The inverter circuit unit 51 is connected to the power supply system VDD3. The power supply system VDD3 applies the operating voltage VDD or the ground voltage GND as VDD3 to the cell structure 35-2 according to the operating frequency of the semiconductor integrated circuit. In the cell structure 35-2 of FIG. 6, the inverter circuit unit 51 has four P-channel transistors and four N-channel transistors connected as shown in the figure, and each inverter circuit unit 41, 42, 51 is configured. The number, type, and connection of the transistors are not limited to those shown in FIG.

  Between the inverter circuit unit 41 and the inverter circuit unit 51, a conduction control circuit 53 using a voltage from the power supply system VDD3 as a control signal is provided at an input unit and an output unit in the cell structure 35-2. The conduction control circuit 53 is controlled by the voltage VDD3 from the power supply system VDD3 and VDD3 * (VDD3 bar) which is an inverted voltage of the voltage VDD3. The voltage VDD3 * is obtained, for example, by inputting the voltage VDD3 to an inverter cell (not shown) of the power supply system VDD1. As in the case of the inverter cell 44 shown in FIG. 5, the inverter cell that generates the voltage VDD3 * does not need to form part of the cell structure 35-2, and the inverter cell that generates the voltage VDD3 * is a semiconductor. It is sufficient that at least one is provided in the integrated circuit.

  Thus, even when there are three power supply systems, the basic structure of the cell structure is the same as in the case of two power supply systems in FIG. 5, and the present invention is similarly applied when there are four or more power supply systems. Needless to say, it is applicable.

  FIG. 7 is a circuit diagram showing the main part of the third embodiment of the present invention. FIG. 7 shows a cell structure 35-3 having a 2-input NAND function and having two power supply systems. The cell structure 35-3 includes input terminals 71 and 72, NAND circuit portions 61 and 62, a conduction control circuit 63, and an output terminal 73. In the cell structure 35-3 of FIG. 7, the NAND circuit section 61 has two P-channel transistors and two N-channel transistors connected as illustrated, and the NAND circuit section 62 is connected as illustrated. Although the P-channel transistor and the six N-channel transistors are provided, the number, type, and connection of the transistors constituting each NAND circuit portion 61 and 62 are not limited to those shown in FIG.

  The NAND circuit unit 61 is connected to the power supply system VDD1, and the NAND circuit unit 62 is connected to the power supply system VDD2. The power supply system VDD1 always applies the operating voltage VDD as VDD1 to the cell structure 35-3. On the other hand, the power supply system VDD2 applies the operating voltage VDD or the ground voltage GND as VDD2 to the cell structure 35-3 according to the operating frequency of the semiconductor integrated circuit.

  Between the NAND circuit unit 61 and the NAND circuit unit 62, a conduction control circuit 63 using a voltage from the power supply system VDD2 as a control signal is provided in the input unit and the output unit in the cell structure 35-3. The conduction control circuit 63 is controlled by the voltage VDD2 from the power supply system VDD2 and VDD2 * (VDD2 bar) which is an inverted voltage of the voltage VDD2. The voltage VDD2 * is obtained by inputting the voltage VDD2 to an inverter cell (not shown) of the power supply system VDD1. As in the case of the inverter cell 44 shown in FIG. 5, the inverter cell that generates the voltage VDD2 * does not need to form a part of the cell structure 35-3, and at least one inverter cell is provided in the semiconductor integrated circuit. It ’s fine.

  Thus, even in the case of the 2-input NAND circuit as shown in FIG. 7, the basic configuration of the cell structure is the same as that of the cell structure configured by the inverter circuit of FIG. 5, and the present invention is a 2-input NAND circuit. Needless to say, the present invention can be similarly applied to other combination circuits such as AND circuits, OR circuits, NOR circuits, and sequential circuits such as flip-flop circuits.

  FIG. 8 is a circuit diagram showing the main part of the fourth embodiment of the present invention. FIG. 8 shows a cell structure 35-4 having a 2-input NAND function and having two power supply systems. The cell structure 35-4 includes input terminals 91 and 92, a two-input NAND circuit and inverter (two-input AND) circuit unit 80, inverter circuit units 81 and 82, a conduction control circuit 83, and an output terminal 93. In the cell structure 35-4 of FIG. 8, the 2-input NAND circuit and the inverter circuit unit 80 have three P-channel transistors and three N-channel transistors connected as illustrated, and the inverter circuit unit 81 is illustrated. The inverter circuit section 82 has three P-channel transistors and three N-channel transistors connected as shown in the figure, each having one P-channel transistor and one N-channel transistor connected as shown. The number, type, and connection of the transistors constituting the circuit units 80, 81, and 82 are not limited to those shown in FIG.

  The 2-input NAND / inverter circuit unit 80 and the inverter circuit unit 81 are connected to the power supply system VDD1, and the inverter circuit unit 82 is connected to the power supply system VDD2. The power supply system VDD1 always applies the operating voltage VDD as VDD1 to the cell structure 35-4. On the other hand, the power supply system VDD2 applies the operating voltage VDD or the ground voltage GND as VDD2 to the cell structure 35-4 according to the operating frequency of the semiconductor integrated circuit.

  Between the inverter circuit unit 81 and the inverter circuit unit 82, a conduction control circuit 83 using the voltage from the power supply system VDD2 as a control signal is a buffer circuit configured by the inverter circuits 81 and 82 in the cell structure 35-4. It is provided in the input part and the output part. The conduction control circuit 83 is controlled by the voltage VDD2 from the power supply system VDD2 and VDD2 * (VDD2 bar) which is an inverted voltage of the voltage VDD2. The voltage VDD2 * is obtained, for example, by inputting the voltage VDD2 to an inverter cell (not shown) of the power supply system VDD1. As in the case of the inverter cell 44 shown in FIG. 5, the inverter cell that generates the voltage VDD2 * does not need to form part of the cell structure 35-4, and the inverter cell that generates the voltage VDD2 * is a semiconductor. It is sufficient that at least one is provided in the integrated circuit.

  In general, cell structures having the same function but different driving capabilities often have the same basic circuit portion and different driving capabilities only in the final stage buffer, as in the example shown in FIG. FIG. 9 is a diagram for explaining an example of a cell structure having the same function but different driving ability. In FIG. 9, for convenience of explanation, the numbers shown in each cell indicate the height of the driving capability in arbitrary units, and the larger the number, the higher the driving capability, that is, the higher the power consumption. In FIG. 9, both the upper cell structure and the lower cell structure are NAND circuits. In the case of the upper cell structure, the NAND circuits have the same configuration, but the output stage buffers have different driving capabilities. In the case of the lower cell structure, the AND circuit has the same configuration, but the drive capability of the inverter in the output stage is different. As described above, the cell structure of the present invention can be applied only to a part of the circuit in the cell structure as long as the function of the cell structure is not impaired.

  According to each of the embodiments described above, the voltage itself applied from the power source to the semiconductor integrated circuit is used as the control signal of the conduction control circuit, so there is no need to provide a dedicated control terminal. Further, when the semiconductor integrated circuit is operated at a low operating frequency, the ground voltage is applied from the power supply system of the transistor circuit that is not used, so that the generation of a leakage current between the source and the drain can be suppressed. As a result, when the semiconductor integrated circuit is operated at a low operating frequency, it is possible to realize lower power consumption than the conventional cell structure having a function capable of changing the driving capability.

  In each of the above embodiments, the conduction control circuit may be provided only in the output section in the cell structure (or macro structure). In this case, the circuit scale can be reduced, but since the input portion is conductive, there is a possibility that a small amount of gate leakage current is generated due to the current flowing through the gate oxide film of the transistor through the tunnel effect. is there. This gate leakage current is particularly noticeable in a fine technology. On the other hand, when the conduction control circuit is provided in both the input part and the output part in the cell structure (or macro structure), the circuit scale becomes larger than in the former case, but the generation of the gate leakage current can be suppressed. . Accordingly, whether or not the conduction control circuit is provided only in the output portion of the cell structure may be selected according to the application of the semiconductor integrated circuit.

In addition, this invention also includes the invention attached to the following.
(Appendix 1)
A semiconductor integrated circuit having an input terminal and an output terminal and operating at a plurality of operating frequencies,
A first logic circuit and a second logic circuit connected in parallel between the input terminal and the output terminal;
A first conduction control circuit connected between the second logic circuit and the output terminal;
The first logic circuit is always applied with an operating voltage from the first power supply system,
The second logic circuit is applied with an operating voltage or a ground voltage from a second power supply system according to the operating frequency,
The first conduction control circuit conducts according to the voltage from the second power supply system,
A semiconductor integrated circuit, wherein the operation state and leakage current of some of the transistors in the second logic circuit are controlled by a voltage from the second power supply system.
(Appendix 2)
A second conduction control circuit connected between the input terminal and the second logic circuit and conducting in accordance with a voltage from the second power supply system;
The semiconductor integrated circuit according to appendix 1, wherein the operation state and leakage current of some other transistors in the second logic circuit are controlled by a voltage from the second power supply system.
(Appendix 3)
3. The semiconductor integrated circuit according to appendix 1 or 2, wherein the number of input terminals is one, the first and second logic circuits are inverter circuits, and the number of output terminals is one.
(Appendix 4)
3. The semiconductor integrated circuit according to appendix 1 or 2, wherein there are a plurality of input terminals, the first and second logic circuits are NAND circuits, and the output terminal is one.
(Appendix 5)
A third logic circuit connected in parallel with the first and second logic circuits between the input terminal and the output terminal;
A second conduction control circuit connected between the third logic circuit and the output terminal;
The third logic circuit is applied with an operating voltage or a ground voltage from a third power supply system according to the operating frequency,
The second conduction control circuit conducts according to the voltage from the third power supply system,
The semiconductor integrated circuit according to appendix 1, wherein the operation state and leakage current of some transistors in the third logic circuit are controlled by a voltage from the third power supply system.
(Appendix 6)
A third conduction control circuit connected between the input terminal and the second logic circuit and conducting in accordance with a voltage from the second power supply system;
A fourth conduction control circuit connected between the input terminal and the third logic circuit and conducting in accordance with a voltage from the third power supply system;
The operation state and leakage current of some other transistors in the second logic circuit are controlled by the voltage from the second power supply system,
6. The semiconductor integrated circuit according to appendix 5, wherein the operation state and leakage current of some other transistors in the third logic circuit are controlled by a voltage from the third power supply system.
(Appendix 7)
A third logic circuit provided between the input terminal and the first logic circuit;
The semiconductor integrated circuit according to appendix 1, wherein the third logic circuit is always applied with an operating voltage from the first power supply system.

  While the present invention has been described with reference to the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made within the scope of the present invention.

It is a figure which shows the clock net which has a several operating frequency. It is a figure which shows the clock net which operate | moves with a single operating frequency. It is a figure which shows an exclusive cell structure notionally. It is a figure which shows notionally a parallel type cell structure. It is a circuit diagram which shows the principal part of 1st Example of this invention. It is a circuit diagram which shows the principal part of 2nd Example of this invention. It is a circuit diagram which shows the principal part of 3rd Example of this invention. It is a circuit diagram which shows the principal part of 4th Example of this invention. It is a figure explaining an example of the cell structure from which the drive capability differs with the same function.

Explanation of symbols

35-1 to 35-4 Cell structure 37, 71, 72, 91, 92 Input terminals 38, 73, 93 Output terminals 41, 42, 51, 81, 82 Inverter circuits 43, 53, 63, 83 Conduction control circuit 80 NAND And inverter circuit

Claims (5)

A semiconductor integrated circuit to have a input terminal and an output terminal,
A first logic circuit and a second logic circuit connected in parallel between the output terminal and the input terminal,
A first conduction control circuit connected between said second logic circuit and the output terminal,
A first power supply system for applying an operating voltage to a power supply terminal of the first logic circuit;
A second power supply system for applying an operating voltage or a ground voltage to the power supply terminal of the second logic circuit ;
It said first conduction control circuit is rendered conductive in response to the operating voltage from the second power supply system, becomes non-conductive in response to the ground voltage from the second power supply system,
The second power supply lines, the power supply terminal of the second logic circuit, the semiconductor integrated circuit is the operating voltage is applied in the case of operating at a first operating frequency, said semiconductor integrated circuit is the first A semiconductor integrated circuit, wherein the ground voltage is applied when operating at a second operating frequency lower than the operating frequency . It is connected between the input terminal and the second logic circuit, rendered conductive in response to the operating voltage from the second power supply system, a non-conductive in response to the ground voltage from the second power supply system wherein the Ru further comprising a second conduction control circuit, the semiconductor integrated circuit according to claim 1, wherein. Between the output terminal and the input terminal, a third logic circuit which is connected in parallel with said first and second logic circuits,
A second conduction control circuit connected between said output terminal said third logic circuit,
A third power supply system for applying an operating voltage or a ground voltage to the power supply terminal of the third logic circuit ;
It said second conduction control circuit is rendered conductive in response to the operating voltage from said third power supply system, becomes non-conductive in response to the ground voltage from the third power supply system,
Said third power supply lines, the power supply terminal of said third logic circuit, when the semiconductor integrated circuit operates at the first operating frequency by applying the operating voltage, the semiconductor integrated circuit is the first 2. The semiconductor integrated circuit according to claim 1, wherein the ground voltage is applied when the second operating frequency is lower than the first operating frequency . It is connected between the input terminal and the second logic circuit, rendered conductive in response to the operating voltage from the second power supply system, a non-conductive in response to the ground voltage from the second power supply system A third conduction control circuit;
Is connected between the input terminal third logic circuit, rendered conductive in response to the operating voltage from said third power supply system, a non-conductive in response to the ground voltage from the third power supply system wherein the Ru further comprising a fourth conduction control circuit, the semiconductor integrated circuit according to claim 3, wherein. Further comprising a third logic circuit which is provided between the input terminal and the first logic circuit,
2. The semiconductor integrated circuit according to claim 1, wherein an operating voltage from the first power supply system is applied to the third logic circuit.

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