JP2679690B2 - Clock drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock drive circuit, and more particularly to a clock drive circuit provided on a chip of a semiconductor integrated circuit for transmitting a clock signal to a signal processing circuit inside the integrated circuit.

[0002]

2. Description of the Related Art In recent years, the performance of semiconductor integrated circuits (hereinafter referred to as LSI) has been remarkably improved, and the system clock frequency has become extremely high. At the LSI design stage, the clock drive circuit is designed in consideration of the load capacity to be driven by the clock drive circuit and the operation speed. In that case, in order to realize high-speed clock operation, it is necessary to increase the drive capability of the clock drive circuit.

However, in some cases, an LSI capable of high-speed clock operation can be operated at a low frequency in order to reduce the power consumption of the entire system or to supply only a low-frequency clock signal during a test. May be needed. At that time, the frequency of the clock signal input to the LSI is switched. However, if a clock drive circuit having a small driving capability for a load is not used, a considerable through current flows through the clock drive circuit during clock operation. Further, fluctuations in the power supply potential and the ground potential due to the parasitic inductance component remain large unless the driving capability of the clock drive circuit is changed.

One of the techniques for coping with the above problem is disclosed in Japanese Patent Laid-Open No. 3-53310. That is, this is a technique in which a clock drive circuit is configured by connecting a plurality of buffers and a plurality of three-state buffers in parallel. FIG. 5 is a block diagram of an LSI including such a clock drive circuit having a parallel connection configuration.
It is described in the above publication. Referring to FIG. 5, in this LSI, the drive capability of the clock drive circuit 58 is
The control signal input terminal 57 is switched by a control signal SC input from the outside. First, at the time of low speed clock operation, the signal SC = “L” is set to deactivate the 3-state buffer 52. At this time, the logic circuits 53 and 54
The clock signal CLK is distributed only to the buffer 51 via the wiring 55. When the high-speed clock signal CLK is input from the clock signal input terminal 56, the control signal SC = "H" is set to activate the 3-state buffer 52. At this time, both the 3-state buffer 52 and the buffer 51 are driven to enhance the driving capability.

FIG. 6 shows another example of an LSI provided with a clock drive circuit having a similar parallel connection configuration.
3 is a block diagram of an LSI including LSI shown in this figure
Is provided with crystal unit connection terminals 61 and 62,
A peripheral circuit 66 is provided on the same chip in addition to the CPU 65. The CPU 65 itself outputs the low-level signal SC = “L” to the clock drive circuit 58 in order to reduce the power consumption of the entire LSI, and the 3-state buffer 5
Make 2 inactive.

[0006]

When selecting the optimum drive capability of the clock drive circuit according to the frequency of the clock signal, the conventional clock drive circuit shown in FIG. 5 needs to be externally supplied with a control signal.
In addition, like the LSI shown in FIG. 6, the CP included in the chip
Even if it is switched by U, if the clock frequency from the outside is unknown, the clock frequency is not measured by itself, and therefore the optimum driving performance of the clock drive circuit cannot be selected.

Therefore, it is an object of the present invention to provide a clock drive circuit which can automatically detect the frequency of a clock signal without the need for an external control signal and select an optimum driving capability. .

[0008]

A clock drive circuit according to the present invention is a clock drive circuit which receives an externally applied clock signal as an input and transmits the clock signal to a load circuit. Is automatically quantized in response to changes in the frequency of
It is characterized by a changing structure.

The clock drive circuit of the present invention comprises a driver having a configuration in which a plurality of three-state buffers to which an externally applied clock signal is input are connected in parallel by connecting the input points and the output points, and the clock. Means for detecting the frequency of the signal, means for detecting which of a plurality of frequency bands the frequency of the detected clock signal belongs to, and an active state in the driver according to the frequency band to which the clock signal belongs By controlling the number of three-state buffers in the above-mentioned, the means for changing the driving capacity with respect to the load of the driver.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a clock drive circuit according to a first embodiment of the present invention. Referring to FIG. 1, this clock drive circuit
A frequency counter 1 for measuring the frequency f of the clock signal CLK, a memory 4 for storing numerical data to be compared with the clock frequency f, and a comparison circuit 3 for comparing the clock frequency with the frequency value written in the memory 4. , A driver 2 for driving a load. Three signals CKB, SAM and CLK are input to the frequency counter 1. The signal CKB is a reference signal for the frequency counter, and is a signal for determining the accuracy of the frequency counter with pulses from the start to the end of counting. The signal SAM is a sampling signal of the frequency counter and is a pulse having a cycle for measuring the frequency. The signal CLK is a clock signal that enters this LSI. The frequencies A, B, and
It is assumed that four numerical data corresponding to C and D (A>B>C> D) have been written. This memory may be RAM or ROM.

The operation of the clock drive circuit will be described below with reference to FIG. Now, it is assumed that a clock signal CLK having a frequency f of, for example, D> f is input from the outside. The frequency counter 1 measures the frequency f ₀ at this time. The comparison circuit 3 compares this frequency f ₀ with
The comparison data A, B, which are written in the memory 4 in advance,
Compare C and D respectively. Here, the comparison circuit 4 has four binary signals S _O1 , S _O2 and S _{O3 in the} states shown in FIG. 2 in accordance with the magnitude relation between the clock frequency f and the stored data A, B, C and D. , S _O4 is output. In this case, since D> f ₀ , all the four signals of the comparison circuit 3 are “0”, and the four three-state buffers 5A, 5B, 5C and 5D in the driver 2 are all inactive.
As the driver 2, only the buffer 6, that is, the driver having the smallest driving capability is used. Each driver of the three-state buffers 5A to 5D may have any size.

FIG. 3 shows a waveform of the clock output 16 and a schematic waveform of fluctuations of the power supply potential and the ground potential in the LSI at this time. Referring to FIG. 3, when D> f ₀ , the rising and falling of the clock output waveform 16 have the gentlest waveform, and the fluctuations of the power supply potential and the ground potential due to the parasitic inductance are very small.

Similarly, the clock frequencies f are f ₁ (C> f ₁ ≧ D), f ₂ (B> f ₂ ≧ C), f, respectively.
_{When 3} (A> f ₃ ≧ B) and f ₄ (f ₄ ≧ A), the three-state buffers 5D, 5C, 5B and 5A are activated in order, and the driving capability of the driver 2 increases. Along with this, the clock output waveform 16 also has steep rising and falling waveforms, and the fluctuations of the power supply potential and the ground potential also increase. In other words, in the present embodiment, the clock frequency f is automatically measured, the driving capability of the driver 2 is reduced during low frequency clock operation, and the shoot-through current in the driver 2 is reduced to reduce power consumption, and at the same time, the power supply potential is reduced. The noise caused by the fluctuation of the ground potential is reduced.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram of a clock drive circuit according to the second embodiment of the present invention. Referring to FIG. 4, the present embodiment is an example in which the number of combinations of drivers 41 is increased as compared with the first embodiment shown in FIG.
The control circuit 43, which includes a comparison circuit, therefore produces more control signals to allow the selection of a larger number of driver sizes. In this case, the driver 41 is composed of two stages X _n and Y _n of the 3-state inverter buffer 42, and functions as a driver if at least one first stage X _i and at least one subsequent stage Y _i are selected. Depending on the control circuit 43,
Theoretically, 2 ^n-1 × 2 ^n-1 combinations are possible.

The 3-state inverter buffer 42 is
It is composed of a buffer 44 having an inversion function, a pn transfer gate 46 arranged before and after the buffer 44, and an inverter 45 for inverting the selection signal EX _n from the control circuit 43. When the signal EX _n = “1” from the control circuit 43, the clock signal CLK is supplied to both transfer gates 46.
Is turned on, and the buffer 44 is driven. When the clock frequency is high, the control circuit 43 outputs a control signal for increasing the driving capability of the driver 41, and when the clock frequency is low, the control circuit 43 outputs a control signal for decreasing the driving capability of the driver. , Driver 4
Change the driving capacity of 1.

[0016]

As described above, in the clock drive circuit of the present invention, a plurality of three-state buffers to which an externally applied clock signal is input are connected in parallel by connecting their input points and their output points. A driver having a configuration, a means for detecting the frequency of the clock signal, a means for detecting which of a plurality of frequency bands the detected frequency of the clock signal belongs to, and a driver according to the frequency band to which the clock signal belongs. By controlling the number of 3-state buffers in the active state, the frequency of the clock signal is automatically detected and the optimum driving capability of the clock drive circuit is selected.

Thus, according to the present invention, when the clock frequency is low, the drive capability of the clock drive circuit is lowered, the rising and falling of the clock are made gentle, the through current is reduced, and the power consumption is reduced and the power supply is reduced. Noise caused by fluctuations in the potential and the ground potential can also be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock drive circuit according to a first embodiment of this invention.

FIG. 2 is a diagram showing a relationship between a frequency of a clock signal and a state of an output signal of a comparison circuit in the block diagram shown in FIG.

3 is a diagram showing a clock output waveform, a power supply potential waveform, and a ground potential waveform in the block diagram shown in FIG.

FIG. 4 is a block diagram of a clock drive circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram of an LSI in which a clock drive circuit according to an example of the related art is mounted.

FIG. 6 is a block diagram of an LSI equipped with another example of a clock drive circuit according to a conventional technique.

[Explanation of symbols]

 1 frequency counter 2 driver 3 comparison circuit 4 memory 5A, 5B, 5C, 5D 3 state buffer 6 buffer 41 driver 42 3 state buffer 43 control circuit 44 inverter buffer 45 inverter 46 transfer gate 51 buffer 52 3 state buffer 53, 54 logic circuit 55 wiring 56 clock signal input terminal 57 control signal input terminal 58 clock drive circuit 61, 62 crystal oscillator connection terminal 63 oscillator circuit 65 CPU 66 peripheral circuit

Claims (3)

(57) [Claims] 1. A clock drive circuit, which receives an externally applied clock signal as an input and transmits the clock signal to a load circuit, wherein the driving capability for the load is automatically determined in accordance with a change in the frequency of the clock signal. A clock drive circuit having a configuration that is changed and changed. 2. A driver having a configuration in which a plurality of three-state buffers to which an externally supplied clock signal is input are connected in parallel by connecting input points and output points, and a frequency of the clock signal is detected. Means for detecting which of a plurality of frequency bands the frequency of the detected clock signal belongs to, and a three-state buffer in an active state in the driver according to the frequency band to which the clock signal belongs And a means for changing the driving ability with respect to the load of the driver by controlling the number. 3. A driver having a configuration in which a plurality of three-state buffers to which an externally applied clock signal is input are connected in parallel by connecting their input points and output points, and the frequency of the clock signal is detected. A frequency counter, a memory circuit that stores at least one predetermined frequency value, and a comparison circuit that compares the frequency of the clock signal detected by the frequency counter with the frequency value stored in the memory circuit. And generating a plurality of binary signals whose respective states are determined in accordance with the comparison result in the comparison circuit, and activating or deactivating the plurality of three-state buffers by the plurality of binary signals. And a control circuit that controls each buffer independently, and a combination of states of the plurality of binary signals changes according to a comparison result in the comparison circuit. The clock drive circuit, characterized in that the actual number of parallel connections of the three-state buffer by changing, configured as drive capability to change the load of the driver.