JP2004206050A

JP2004206050A - Liquid crystal display device

Info

Publication number: JP2004206050A
Application number: JP2003139120A
Authority: JP
Inventors: Yuji Uchiyama; 裕治内山
Original assignee: Victor Company of Japan Ltd
Current assignee: Victor Company of Japan Ltd
Priority date: 2002-10-29
Filing date: 2003-05-16
Publication date: 2004-07-22

Abstract

<P>PROBLEM TO BE SOLVED: To prevent display quality from being degraded due to crosstalk of an image signal through auxiliary capacitance of a display pixel in a liquid crystal display device using multi-phase image signals. <P>SOLUTION: Each input circuit for the multi-phase image signals to columnar signal driving circuit 51 is provided with each single phase processing part 1-i consisting of a delay circuit 11, an adding circuit 12, and a D-A converter 13 which process digital image data VIDEOd[i]:(i=1-n). Moreover, a compensation data creating part 2 consisting of an adding circuit 21 for adding all the image data VIDEOd[i] and a multiplying circuit 22 for multiplying the addition result by a certain coefficient Ac is arranged, and the multiplication result is added to the image data VIDEOd[i] by the adding circuit 12 of each single phase processing part 1-i. The coefficient Ac is set to a value at which the multiplication result of the multiplying circuit 22 is made corresponding to the voltage variation of a base board terminal of the auxiliary capacitance, to compensate for a crosstalk portion in accordance with the image signals to be written in group units. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は液晶表示装置に係り、特に多相化された画像信号によって表示が行われる投射型ディスプレイやビューファインダ、ヘッドマウントディスプレイ等に適用され、組単位で表示画素に書き込まれる画像信号のクロストークを抑制して高画質な画像を表示させるための改善に関する。
【０００２】
【従来の技術】
アクティブマトリックス型の液晶表示装置においては、基板上に表示画素がマトリクス状に形成されており、各表示画素はスイッチング用電界効果型トランジスタ（以下、単に「トランジスタ」という）と信号電圧保持用のコンデンサ（以下、「補助容量」という）と画素電極と共通電極と液晶部材で構成されているが、従来から、トランジスタの応答特性や補助容量の周波数特性が十分でないような場合の解決策として、例えば、下記の特許文献１〜４等で開示されているように、画像信号をｎ相（ｎは２以上の自然数）の多相信号に変換して入力することが行われている。
即ち、元の画像信号を多相化することによりその占有周波数帯域を１／ｎに低下せしめ、ｎ本の入力信号線を通じて液晶表示装置に供給することにより前記の問題点を解決させている。
【０００３】
先ず、液晶表示装置は図５に示すような回路構成からなり、マトリクス状に配設された多数の表示画素ＰＸと、それらの表示画素ＰＸを駆動するための列信号線駆動回路５１及び行信号線駆動回路５２を備えており、行信号線駆動回路５２が各行信号線Ｇ１…Ｇｊを通じて各行の表示画素ＰＸのトランジスタをＯＮ／ＯＦＦ制御し、列信号線駆動回路５１が各信号線Ｄ（１）１…Ｄ（Ｘ）ｎを通じて各列の表示画素ＰＸの補助容量に画像信号を書き込むようになっている。
具体的には、単結晶シリコン基板の上に複数の列信号線Ｄ（１）１…Ｄ（Ｘ）ｎと複数の行信号線Ｇ１…Ｇｊが相互に直交した態様でそれぞれ平行に形成されていると共に、各信号線Ｄ（１）１…Ｄ（Ｘ）ｎとＧ１…Ｇｊの交差部分にそれぞれ１個ずつ表示画素ＰＸが配置・形成されており、列信号線Ｄ（１）１…Ｄ（Ｘ）ｎの合計本数をｉ本とすれば、表示画素数が（ｉ×ｊ）個の表示パネルを構成していることになる。
尚、図５では、多相化画像信号に基づく画像表示動作手順を説明するために、列信号線Ｄ（１）１…Ｄ（Ｘ）ｎをＤ（Ｋ）１〜Ｄ（Ｋ）ｎ［但し、Ｋ＝１〜Ｘ］としてＸ組に分けて表現してある。
【０００４】
次に、各表示画素ＰＸは、前記のようにトランジスタ６１と補助容量６２と画素電極６３と共通電極６４と液晶部材６５とで構成されている。
即ち、列信号線Ｄ（１）１と行信号線Ｇ１の交差部分の表示画素ＰＸ（１，１）について説明すると、トランジスタ６１のドレインには列信号線Ｄ（１）１が、制御端子であるゲートには行走査線Ｇ１が、ソースには補助容量６２と画素電極６３がそれぞれ接続されていると共に、画素電極６３と共通電極６４の間に液晶部材６５が保持された構成になっている。
また、全ての表示画素ＰＸの共通電極６４にはＣＯＭ信号が印加され、補助容量６２の一方の端子にはＣＣ信号が印加されるようになっている。
【０００５】
そして、各表示画素ＰＸの断面構造は図９に示され、基板７１面に形成されたトランジスタ６１のソースに対して画素電極６３が接続されており、その接続部分から側方へ導体部７２が連続的に形成され、基板７１と導体部７２の間に誘電体層７３を形成することによって補助容量６２を構成している。
従って、前記の導体層７２が補助容量６２の一方の端子に相当し、基板７１が他方の端子に相当するが、以降、後者の端子を「基板側端子７１ａ」として説明する。
また、画素電極６３の上側には透明基板７４が液晶部材６５を介して対向配置せしめられており、透明基板７４には透明な導体膜である共通電極６４が形成されている。
尚、７５は絶縁層であり、７６，７７はそれぞれ画素電極６３側と透明基板７４側に皮膜された液晶配向膜である。
従って、液晶表示装置では透明基板７４側の共通電極６４に対してＣＯＭ信号を印加し、補助容量６２の基板側端子７１ａに対してＣＣ信号を印加することになるが、基板側端子７１ａは基板７１自体か又は基板７１に形成した導体層によって構成されるため、ＣＣ信号も基板７１又は前記導体層を通じて共通に印加されることになる。
【０００６】
次に、列信号線駆動回路５１は、図示していないシフトレジスタやサンプリングスイッチで構成されており、外部回路から入力される水平スタート信号ＨＳＴ及び水平クロック信号ＨＣＫに基づいて、転送されてくる多相化画像信号：ＶＩＤＥＯ（Ｋ）［ｉ］［ｉ＝１〜ｎ］を所定のタイミングで順次サンプリングして列信号線Ｄ（１）１〜Ｄ（１）ｎ，Ｄ（２）１〜Ｄ（２）ｎ，…，Ｄ（Ｘ）１〜Ｄ（Ｘ）ｎへ順次出力する。
即ち、列信号線駆動回路５１はｎ個の入力端子から同時に多相化画像信号を取り込み、一定のタイミングで各組の列信号線Ｄ（Ｋ）１〜Ｄ（Ｋ）ｎ：［Ｋ＝１〜Ｘ］へ順次出力させる。
【０００７】
具体的には、１水平走査期間をＨとすると、多相化画像信号をＨ／Ｘの期間毎にサンプリングし、最初のＨ／Ｘの期間におけるｎ個のサンプリング信号は列信号線Ｄ（１）１〜Ｄ（１）ｎへ並列出力し、次のＨ／Ｘの期間におけるｎ個のサンプリング信号は列信号線Ｄ（２）１〜Ｄ（２）ｎへ並列出力し、以降、同様にして１水平走査期間の最後のＨ／Ｘの期間におけるｎ個のサンプリング出力信号は列信号線Ｄ（Ｘ）１〜Ｄ（Ｘ）ｎへ並列出力することになる。
【０００８】
一方、行走査線駆動回路５２は、図示しないシフトレジスタとセレクタを含む回路として構成されており、外部から入力される垂直スタート信号ＶＳＴ、垂直クロック信号ＶＣＫに基づいて、１フレーム分の走査期間内に走査信号（選択信号）を行走査線Ｇ１…Ｇｊへ順次供給する動作を各フレーム単位で繰り返す。
そして、その走査信号が行走査線Ｇ１に供給された時は、その走査信号が第１行目の（Ｋ×ｎ）個の表示画素ＰＸに係る各トランジスタ６１のゲートに印加されて、それらのトランジスタ６１をオン状態（選択状態）とし、各トランジスタ６１のドレイン・ソース間を導通させる。
【０００９】
それにより、列信号線駆動回路５１でサンプリングされた画像信号は各組の列信号線Ｄ（１）１〜Ｄ（１）ｎ，Ｄ（２）１〜Ｄ（２）ｎ，…，Ｄ（Ｘ）１〜Ｄ（Ｘ）ｎへ順次同時に並列出力され、それぞれの組に係る列信号線Ｄ（１）１〜Ｄ（１）ｎ，Ｄ（２）１〜Ｄ（２）ｎ，…，Ｄ（Ｘ）１〜Ｄ（Ｘ）ｎが接続されている各トランジスタ６１のドレイン・ソース間を通じて各補助容量６２に同時に蓄積される。
そして、行走査線駆動回路５２は、列信号線駆動回路５１における各水平走査期間Ｈ毎に走査信号を行信号線のＧ１からＧｊまで順次出力し、その走査信号を出力した行信号線に対応する各表示画素ＰＸの補助容量６２に対して列信号線Ｄ（１）１〜Ｄ（１）ｎ，Ｄ（２）１〜Ｄ（２）ｎ，…，Ｄ（Ｘ）１〜Ｄ（Ｘ）ｎに出力されている画像信号を蓄積させてゆくことになる。
その結果、第１行目（１）から最終行（ｊ）までの全ての表示画素ＰＸの補助容量６２に１フレーム分の画像信号が蓄積され、各表示画素ＰＸでは補助容量６２に蓄積された画像信号に対応する電圧が画素電極６３へ供給される。
【００１０】
一方、図５において、ＣＯＭ信号は図９に示した透明基板７４側の共通電極６４から印加されるが、画像信号の極性と同極性の電圧とされ、一般的な液晶表示装置ではＣＯＭ信号の電圧が液晶部材６５の閾値電圧に設定されている。
そして、液晶部材６５を交流駆動させるために画像信号はフレーム毎又はフィールド毎に反転せしめられ、その信号電圧レベル（信号分電圧）と前記のＣＯＭ信号の電圧との差を実効電圧として液晶部材６５に光変調動作を生じさせる。
また、ＣＣ信号は補助容量６２に蓄積された画像信号の電圧を調整するものであり、液晶の適正な光変調動作を確保させるための電圧を各表示画素ＰＸの基板側端子７１ａに対して共通に印加されている。
【００１１】
次に、以上に説明した液晶表示装置の概略動作を、図６及び図７のタイミングチャートに基づいて更に具体的に説明する。
ここに、図６は主に行信号線駆動回路５２の動作タイミングを、図７は主に列信号線駆動回路５１の動作タイミングを示している。
【００１２】
図６において、（ａ）は列信号線駆動回路５１に入力される多相化画像信号の入力波形を示し、その画像信号はフレーム期間Ａでは非反転信号となり、フレーム期間Ｂでは反転信号になっている。
行走査線駆動回路５２には、（ｂ）と（ｃ）に示すＶＳＴ，ＶＣＫの各信号が供給される。
そして、行走査線駆動回路５２が内蔵するシフトレジスタは、入力されたＶＳＴをＶＣＫの立ち上がりエッジで１段分シフトし、これを走査信号として出力するｊ段のシフトレジスタであり、行走査線駆動回路５２の各シフト段から内蔵のセレクタにより行信号線Ｇ１，Ｇ２，…，Ｇｊに対して（ｄ）に示す走査信号を出力させるが、そのセレクタはシフトレジスタの出力を期間Ａでは行信号線Ｇ１，Ｇ２，…，Ｇｊへ出力し、期間Ｂでは出力しないようになっている。
従って、期間Ａでは、走査信号が行走査線Ｇ１，Ｇ２，…，Ｇｊへ順次出力されて各行のトランジスタ６１がオン状態となり、期間Ｂでは各行のトランジスタ６１はオフ状態となる。
また、図６の（ｅ）と（ｆ）に示すＣＯＭ信号とＣＣ信号は、それぞれ前記の所定電位の信号で共通電極６４と各補助容量６２の基板側端子７１ａに印加されている。
【００１３】
一方、列信号線駆動回路５１の動作タイミング（図７）についてみると、列信号線駆動回路５１に対しては、（ａ）に模式的に示す多相化された画像信号と、（ｃ）のＨＳＴと、（ｄ）のＨＣＫが入力されている。
ここで、ＨＳＴとＨＣＫは列信号線駆動回路５１が内蔵するシフトレジスタの動作を制御する信号である。
列信号線駆動回路５１では、（ｂ）に示す行信号線駆動回路５２のＶＳＴと同期したＨＳＴに基づいて、（ｅ）の多相化画像信号がＨＣＫに同期して列信号線Ｄ（１）１〜Ｄ（１）ｎ，Ｄ（２）１〜Ｄ（２）ｎ，…，Ｄ（Ｘ）１〜Ｄ（Ｘ）ｎに出力される。
尚、図７の（ｅ），（ｆ）は図６に示した前記のＣＯＭ信号（ｅ）とＣＣ信号（ｆ）である。
【００１４】
従って、図５に示した液晶表示装置では、列信号線駆動回路５１と行信号線駆動回路５２が相互に同期をとりながら多相化画像信号を組単位で各表示画素ＰＸに書き込む動作を繰り返し、フレーム期間Ａにおいて画像信号を各表示画素ＰＸの補助容量６２に蓄積させ、フレーム期間Ｂにおいて各表示画素ＰＸに対応する領域の液晶部材６５に光変調動作を生じさせることにより、連続的にフレーム画像を表示させる。
【００１５】
ところで、前記の液晶表示装置においては、上記のようにＣＣ信号を印加する基板側端子７１ａが基板７１自体又は基板に構成した導体層になっており、ＣＣ信号は全ての表示画素ＰＸの補助容量６２に対して共通に印加されている。
そして、そのようなＣＣ信号の共通印加方式は、前記のように画像信号を多相化して入力させる液晶表示装置に限らず、画像信号をシリアルに転送する従来の一般的な液晶表示装置においても同様であるが、いずれにしても、各表示画素ＰＸの補助容量６２に対するＣＣ信号の共通印加回路を介して各補助容量６２に蓄積された画像信号のクロストークが発生し、その結果として画像の表示品質が低下するという問題がある。
即ち、画像信号が行単位又は前記の組単位で補助容量６２に書き込まれてゆく際に前記の共通印加回路を介して電荷の移動が生じ、それによって補助容量６２と画素電極６３の電圧が変動することにより表示画像の乱れが発生する。
特に、前記の液晶表示装置では多相化画像信号が組単位で補助容量６２に同時に書き込まれてゆき、また前記の電圧変動量が比較的大きくなるために画像の表示品質に与える影響が大きくなる。
【００１６】
その問題点に対して、本願発明者は、前記の液晶表示装置が画像信号を多相化していることに着目し、図８に示すように、各組（Ｋ＝１〜Ｘ）のｎ本の列信号線Ｄ（Ｋ）１〜Ｄ（Ｋ）ｎ：［Ｋ＝１〜Ｘ］の内で、各組の同じ順番の列信号線に接続された表示画素ＰＸの補助容量６２における基板側端子（ＣＣ信号を印加する端子）が、外部から導かれたｎ本のＣＣ信号線ＣＣ１〜ＣＣｎの内で同じ順番の信号線にのみ共通接続された回路構成を提案した（特願２００２−１９９３５５号）。
この提案に係る液晶表示装置によれば、各組単位で垂直方向に整列した表示画素ＰＸ群毎に独立したＣＣ信号線ＣＣ１〜ＣＣｎからＣＣ信号を印加しており、少なくとも水平方向に隣接した表示画素ＰＸ間でのクロストークを防止でき、画像の表示品質を向上させることが可能になる。
【００１７】
【特許文献１】
特開平１１−００７２７０号公報
【特許文献２】
特開平１１−１３３９３２号公報
【特許文献３】
特開平１１−１３３９３３号公報
【特許文献４】
特開平１１−２０２８４１号公報
【００１８】
【発明が解決しようとする課題】
しかしながら、前記の提案（特願２００２−１９９３５５号）の液晶表示装置によると、表示画素ＰＸの補助容量６２を介したクロストークは抑制できるが、図８に示すように、基板上にｎ本のＣＣ信号線ＣＣ１〜ＣＣｎを別途形成すると共に、各組（Ｋ＝１〜Ｘ）の同じ順番の列信号線に接続された表示画素ＰＸに係る補助容量６２の基板側端子７１ａに対して各ＣＣ信号線ＣＣ１〜ＣＣｎを接続する回路も形成しなければならない。
具体的には、同一の列信号線に接続された表示画素ＰＸの補助容量６２の基板側端子７１ａは共通の導体層として形成することができるが、各ＣＣ信号線ＣＣ１〜ＣＣｎと共にそれら信号線ＣＣ１〜ＣＣｎと前記の導体層に対する接続回路を基板上に形成しなければならず、それらを構成するための信号線数は非常に多くなる。
従って、画像信号のクロストークの問題点を解消する点では有効であるが、ＣＣ信号の印加回路の配線領域を確保するために液晶表示装置の基板が大きくなり、半導体プロセスの複雑化によって歩留まりの低下と製造コストの増大を招くという問題がある。
【００１９】
一方、図５に示した回路構成では、画像信号のクロストークに係る問題はあるが、画面を構成する全ての表示画素ＰＸに対して基板７１自体を全面的に基板側端子７１ａとして共通にＣＣ信号を印加させることができるため、基板上の回路構成は簡素になる。
【００２０】
そこで、本発明は、多相化画像信号によって画像表示を行う液晶表示装置において、ＣＣ信号の印加回路を図５に示した一般的な構成としながら、各表示画素ＰＸの画像信号のクロストークを抑制できる方式を提供することを目的として創作された。
【００２１】
【課題を解決するための手段】
先ず、本発明が適用される液晶表示装置は、スイッチングトランジスタと補助容量と画素電極を含み、前記補助容量の一方の端子を前記スイッチングトランジスタの出力端子と前記画素電極に接続し、他方の端子を基板側に構成した構造からなる多数の表示画素をマトリクス状に配置させた第１基板と、前記第１基板に対向して配置せしめられた透明基板であって、前記第１基板における表示画素の配置領域と対応する領域に共通電極を設けた第２基板と、前記第１基板と前記第２基板の間に封止・保持された液晶部材と、列方向に整列した各表示画素のスイッチングトランジスタの入力端子に接続した各列信号線をｎ本（ｎは２以上の自然数）を一組として組分けし、ｎ相に多相化された入力画像信号を各組の列信号線に並列にサンプリング出力する動作を前記組単位で順次実行する列信号線駆動回路と、行方向に整列した各表示画素のスイッチングトランジスタのオン／オフ制御端子に接続した各行信号線に対して行選択信号を順次出力し、表示画素のスイッチングトランジスタを行単位でオン／オフさせる行走査線駆動回路とを備え、前記第１基板における各補助容量の基板側の端子と前記第２基板の共通電極にそれぞれ所定電圧を印加した状態で、前記列信号線駆動回路と前記行走査線駆動回路が同期して動作することにより画像表示を行うものである。
即ち、従来技術において説明した多相化画像信号を扱う液晶表示装置であり、図５の回路構成のように第１基板における各補助容量の基板側端子に対して共通に所定電圧を印加する方式の液晶表示装置を前提とする。
【００２２】
そして、第１の発明は、前記液晶表示装置において、ｎ相に多相化された前記画像信号の同一時点における各信号を加算する第１加算回路と、前記第１加算回路が求めた加算結果に対して一定の係数値を乗算する第１乗算回路と、前記列信号線駆動回路に対するｎ相分の画像信号の各入力回路中にそれぞれ独立に設けられ、前記第１乗算回路の乗算結果と前記第１加算回路が加算処理を実行した時点の画像信号とを加算して前記列信号線駆動回路へ出力する第２加算回路とを備え、前記第１乗算回路における乗算係数値を、前記列信号線駆動回路によってｎ相分の画像信号が組単位で前記補助容量に蓄積される際に、前記補助容量の基板側の端子に生じる電圧変動分を補償する値として設定したことを特徴とする液晶表示装置に係る。
【００２３】
この発明では、第１加算回路で多相化されたｎ相分の画像信号を同一時点で加算した結果に対して第１乗算回路で一定の係数値を乗算し、その乗算結果を第２加算回路で各相の画像信号に加算している。
ここで、第１加算回路の加算結果は、列信号線駆動回路が画像信号を組単位で並列にサンプリング出力して表示画素の補助容量に蓄積させる際に各補助容量の基板側の端子に発生する電圧変動分にほぼ比例した値を示す。
従って、第１乗算回路によってその電圧変動分を補償する値として設定された係数値を前記の加算結果に乗算し、その乗算結果を各相の画像信号の各入力回路に設けた第２加算回路で各画像信号に加算しておけば、各表示画素の補助容量に対して前記の電圧変動分を補償した画像信号が書き込まれることになり、各補助容量の基板側の端子を通じた各画像信号のクロストークによる表示画像の乱れを防止できる。
また、この発明の各回路は多相化画像信号の入力経路に挿入すればよく、必ずしも基板上に構成する必要はなく、仮に基板上に構成するとしても、各表示画素の形成領域とは別の領域に形成できるため、半導体プロセスが複雑化することはない。
【００２４】
第２の発明は、前記の前提とされる液晶表示装置において、ｎ相に多相化された前記画像信号の同一時点における各信号を加算する第１加算回路と、前記列信号線駆動回路に対するｎ相分の画像信号の各入力回路に対応する回路としてそれぞれ独立に設けられ、前記第１加算回路が求めた加算結果に対して前記各入力回路毎に個別に設定された係数値を乗算する第２乗算回路と、前記列信号線駆動回路に対するｎ相分の画像信号の各入力回路中にそれぞれ独立に設けられ、前記第２乗算回路の乗算結果と前記第１加算回路が加算処理を実行した時点の画像信号とを加算して前記列信号線駆動回路へ出力する第３加算回路とを備え、前記各第２乗算回路の乗算係数値を、前記列信号線駆動回路によってｎ相分の画像信号が組単位で前記補助容量に蓄積される際に、前記第２乗算回路に対応する前記入力回路と接続された列方向の各表示画素における前記各補助容量の基板側の端子に生じる電圧変動分を補償する値として設定したことを特徴とする液晶表示装置に係る。
【００２５】
前記の第１の発明では、第１加算回路による多相化された信号の加算結果に対して第１乗算回路が一定の係数値を乗算し、その乗算結果を第２加算回路によって一律にｎ相分の各画像信号に対して加算するようになっている。
しかし、半導体プロセスで製造される第１基板の各表示画素に係る補助容量の基板側の端子に接続される回路（図５におけるＣＣ信号の印加回路）は、行方向に関して一様に形成されるとは限らず、例えば、偶数番目の列と奇数番目の列とで回路パターンが異なる場合がある。
そのような場合には、行方向に整列した各表示画素について、各補助容量の基板側の端子に生じる電圧変動分が異なり、行方向に係る各画像信号間のクロストークによって表示画像の乱れが生じることになる。
この第２の発明によれば、第２乗算回路をｎ相分の画像信号の各入力回路に対応させた回路として独立に設けておき、各第２乗算回路によって第１加算回路が求めた加算結果に対して個別の乗算係数値を乗算し、その乗算結果を各入力回路中にそれぞれ独立に設けた第３加算回路によって各相の画像信号に加算するようになっている。
従って、各第２乗算回路の乗算係数値を個別に調整することにより、前記のように偶数番目の列と奇数番目の列とで回路パターンが異なることによって生じる各画像信号間のクロストークをきめ細かに防止でき、より高品質な画像が得られる。
【００２６】
第３の発明は、前記の前提とされる液晶表示装置において、ｎ相に多相化された前記画像信号の同一時点における各信号を加算する第１加算回路と、前記第１加算回路が求めた加算結果に対して一定の係数値を乗算する第１乗算回路と、前記第１基板における各補助容量の基板側の端子に電圧を印加させるための基板側回路とその本来の所定電圧を出力する外部の電圧供給回路との間に設けられ、前記電圧供給回路の出力電圧に対して前記第１乗算回路の乗算結果を加算して前記基板側回路へ出力する第４加算回路とを備え、前記第１乗算回路における乗算係数値を、前記列信号線駆動回路によってｎ相分の画像信号が組単位で前記補助容量に蓄積される際に、前記補助容量の基板側の端子に生じる電圧変動分を補償する値として設定したことを特徴とする液晶表示装置に係る。
【００２７】
この発明は、第１及び第２の発明が多相化された各画像信号の入力回路側で各補助容量の基板側の端子に生じる電圧変動分を補償しているのに対して、前記の基板側の端子に共通に所定電圧を印加する回路側で補償を実行するものである。この発明における第１加算回路と第１乗算回路が担う機能は第１の発明の場合と同様であるが、その乗算結果は、第１基板における各補助容量の基板側の端子に電圧を印加させるための基板側回路とその本来の電圧を出力する外部の電圧供給回路との間に設けられた第４加算回路に出力され、第４加算回路が前記電圧供給回路の出力電圧に対して前記乗算結果を加算して前記の基板側回路に出力している。
従って、前記の電圧変動分は基板側回路側で補償されることになり、第１及び第２の発明と同様に、各補助容量の基板側の端子を通じた各画像信号のクロストークによる表示画像の乱れを防止できる。
また、各回路を必ずしも基板上に構成する必要がなく、仮に基板上に構成する場合にも半導体プロセスが複雑化しないことも、第１及び第２の発明と同様である。
【００２８】
【発明の実施の形態】
以下、本発明の液晶表示装置の実施形態を図１から図４を用いて詳細に説明する。
［実施形態１］
この実施形態における液晶表示装置の基本回路部分は図５に示したものと同様であり、その回路構成と多相化画像信号による画像表示動作については従来技術の欄で説明したとおりであるため、ここではそれらの説明を省略する。
また、この実施形態では、各表示画素ＰＸに係る補助容量６２の基板側端子７１ａが図９に示したように基板７１自体で構成されており、ＣＣ信号は基板７１を通じて表示画素ＰＸに対して共通に印加されているものとする。
【００２９】
この実施形態の特徴は、列信号線駆動回路５１に対する多相化画像信号の入力回路に図１に示すような信号処理回路が適用されている点にある。
その信号処理回路は、ｎ相に多相化された各ディジタル画像データＶＩＤＥＯｄ［ｉ］に対応する各信号線に設けられた各単相処理部１−ｉと、ｎ相の全ての画像データＶＩＤＥＯｄ［ｉ］を用いて補償データを作成する補償データ作成部２とからなり、各単相処理部１−ｉは遅延回路１１と加算回路１２とＤ／Ａ変換器１３の直列回路として構成されており、また補償データ作成部２は加算回路２１と乗算回路２２の直列回路として構成されている。
但し、「ｉ」はｎ相に多相化された各回路に対応付けたインデックス番号（１〜ｎ）であり、以下、この実施形態及び下記の実施形態２，３においても同様とする。
そして、補償データ作成部２では、加算回路２１がｎ相分の各画像データＶＩＤＥＯｄ［ｉ］を全て加算し、乗算回路２２がその加算データ：Ｖｑに対して一定の係数Ａｃを乗算して各単相処理部１−ｉ側の加算回路１２へ出力するようになっている。
【００３０】
各単相処理部１−ｉ側においては、ＣＬＫに同期した遅延回路１１で画像データＶＩＤＥＯｄ［ｉ］の転送を受けて一定時間後に加算回路１２へ出力させるが、これは補償データ作成部２の加算・乗算動作に僅かに時間を要するため、補償データ作成部２から乗算結果が出力されるタイミングと画像データＶＩＤＥＯｄ［ｉ］が各単相処理部１−ｉ側の加算回路１２へ入力されるタイミングとの同期をとるためである。
従って、各単相処理部１−ｉの加算回路１２で画像データＶＩＤＥＯｄ［ｉ］に加算される補償データ作成部２の乗算結果は、同一時点で得られている画像データＶＩＤＥＯｄ［ｉ］に基づいて作成されたものであり、それが各単相処理部１−ｉ側の加算回路１２で各画像データＶＩＤＥＯｄ［ｉ］に加算されることになる。
【００３１】
ところで、補償データ作成部２における乗算回路２２の乗算係数Ａｃは、次に説明する定数として設定される。
今、ｎ相分の各画像データＶＩＤＥＯｄ［ｉ］がＤ／Ａ変換器１３のみを介してアナログ画像信号ＶＩＤＥＯ［ｉ］として列信号線駆動回路５１に入力される場合を想定すると、上記のように図５の液晶表示装置ではそれらの画像信号ＶＩＤＥＯ［ｉ］を列信号線Ｄ（Ｋ）［ｉ］を介して組単位で各表示画素ＰＸの補助容量６２に書き込む。
【００３２】
その場合、各補助容量６２の基板側端子７１ａに相当する基板７１には所定電圧のＣＣ信号が印加されているが、各補助容量６２に蓄積された電荷は僅かであるが基板７１側を介して他の組の各表示画素ＰＸ側へ流れ、それによって画像信号ＶＩＤＥＯ［ｉ］が書き込まれた各表示画素ＰＸの基板側端子７１ａの電圧が変動し、結果的に画素電極６３の電圧が変動するために適正な画素表示が得られていないことになる。
即ち、組単位で画像信号ＶＩＤＥＯ［ｉ］のクロストークが発生して画像の表示品質が損なわれることになる。
【００３３】
一方、図２に示すように、前記のクロストーク量に対応する画素電極６３の電圧変動量Ｖｑは、同時に書き込まれる画像信号ＶＩＤＥＯｄ［ｉ］の加算値にほぼ比例した傾向を示す。
そこで、この実施形態では、前記の乗算係数Ａｃを画像信号ＶＩＤＥＯｄ［ｉ］の加算値に対する基板側端子７１ａの電圧変動量の増加率（比例定数）として設定しておき、それを画像信号ＶＩＤＥＯｄ［ｉ］の加算値に乗算することにより基板側端子７１ａの電圧変動量Ｖｑを得るようにしている。
【００３４】
従って、上記のように、補償データ作成部２で得られた電圧変動量Ｖｑを各単相処理部１−ｉの加算回路１２で各画像データＶＩＤＥＯｄ［ｉ］に加算し、それをＤ／Ａ変換器１３でアナログ信号に変換すると、予め前記の電圧変動量Ｖｑを補償した画像信号ＶＩＤＥＯ［ｉ］が得られる。
そして、そのｎ相の画像信号ＶＩＤＥＯ［ｉ］がＤ／Ａ変換器１３から列信号線駆動回路５１へ出力されるため、図５の液晶表示装置においては、組単位でクロストーク量を相殺した画像信号ＶＩＤＥＯ［ｉ］による表示が可能になる。
また、この実施形態では、一般的な液晶表示装置と同様に、基板７１自体が全ての表示画素ＰＸの補助容量６２に対する共通の基板側端子７１ａとなっており、基板７１に対してＣＣ信号を印加しておくだけで足りるため、図８に示した液晶表示装置のように基板上に複雑なＣＣ信号の印加用回路を形成する必要がない。
【００３５】
尚、前記の乗算係数Ａｃはディジタル信号として乗算回路２２へ入力されるが、出力電圧を可変設定できる定電圧回路（図示せず）から得られる電圧をＡ／Ｄ変換器（図示せず）でディジタル信号に変換して入力させればよい。
乗算係数Ａｃの値は、予め各種の画像データＶＩＤＥＯｄ［ｉ］を用いて電圧変動分を実験的に求めておき、定電圧回路側で出力電圧を調整することにより得られる。
【００３６】
［実施形態２］
先ず、この実施形態における液晶表示装置の基本回路部分も、実施形態１の場合と同様に、図５に示した構成とする。
また、各表示画素ＰＸに係る補助容量６２の基板側端子７１ａが図９に示したように基板７１自体で構成されているものとする。
この実施形態の特徴は、列信号線駆動回路５１に対する多相化画像信号の入力回路に図３に示すような信号処理回路が適用されている点にある。
【００３７】
この実施形態の特徴は、列信号線駆動回路５１に対する多相化画像信号の入力回路に図３に示すような信号処理回路が適用されている点にある。
そして、図３と図１とを比較すれば明らかなように、この実施形態の信号処理回路と実施形態１の信号処理回路との相違は次のような点にある。
先ず、実施形態１では補償データ作成部２を加算回路２１と乗算回路２２とで構成しているが、この実施形態では、乗算回路１４が各単相処理部１ａ−ｉに対してそれぞれ独立に組み込まれており、実施形態１の補償データ作成部２に相当するものが加算回路２１と各単相処理部１ａ−ｉの各乗算回路１４とで構成してある。
また、各単相処理部１ａ−ｉの加算回路１２ａは、乗算回路１４の乗算結果をその各単相処理部１ａ−ｉに入力される画像信号ＶＩＤＥＯｄ［ｉ］に加算するようになっている。
【００３８】
そして、この実施形態では、各単相処理部１ａ−ｉの乗算回路１４に対してそれぞれ個別の乗算係数Ａｃ［ｉ］が設定されている。
即ち、各乗算係数Ａｃ［ｉ］は、列信号線駆動回路５１によってｎ相分の画像信号ＶＩＤＥＯ［ｉ］が組単位で各表示画素ＰＸの補助容量６２に書き込まれる際に、単相処理部１ａ−ｉに対応した表示画素ＰＸの基板側端子７１ａに生じる個別の電圧変動量の増加率（比例定数）として設定されている。
【００３９】
この実施形態では、前記の図３に示した構成に基づいて、加算回路２１がｎ相分の各画像データＶＩＤＥＯｄ［ｉ］を全て加算し、その加算データ：Ｖａｌに対して単相処理部１ａ−ｉの乗算回路１４が乗算係数Ａｃ［ｉ］を乗算して補償データ：ΔＶｑ［ｉ］＝Ａｃ［ｉ］＊Ｖａｌを作成し、加算回路１２ａがその補償データ：ΔＶｑ［ｉ］を画像信号ＶＩＤＥＯｄ［ｉ］に加算する。
その場合、実施形態１では補償データ作成部２で作成した補償データΔＶｑを一律に各画像データＶＩＤＥＯｄ［ｉ］に加算していたが、この実施形態では、各乗算係数Ａｃ［ｉ］を個別に調整設定できるため、各画像信号ＶＩＤＥＯｄ［ｉ］が書き込まれる表示画素ＰＸの特性に対応させた補償データ：ΔＶｑ［ｉ］を各画像データＶＩＤＥＯｄ［ｉ］に加算できることになる。
【００４０】
従って、半導体プロセスで製造される各表示画素ＰＸにおける補助容量６２の基板側端子７１ａへ接続される回路（図５におけるＣＣ信号の印加回路）が偶数番目の列と奇数番目の列とで回路パターンを異ならしめてあり、それらの列毎に前記の基板側端子７１ａに生じる電圧変動分が異なるような場合には、各電圧変動分に対応させて乗算係数Ａｃ［ｉ］を個別に調整することにより、行方向に隣接している表示画素ＰＸの画像信号間で生じるクロストークを防止できる。
また、ｎ相分の画像信号ＶＩＤＥＯ［ｉ］が組単位で各表示画素ＰＸの補助容量６２に書き込まれる際に、組同士の境界部分で前記の電圧変動が大きくなることも想定されるが、この実施形態の装置によれば、そのような現象にも対応することが可能である。
【００４１】
［実施形態３］
この実施形態は、前記の各実施形態がクロストークによる画素電極６３の電圧変動量Ｖｑを予め画像信号ＶＩＤＥＯ［ｉ］の入力側で補償しているのに対して、基板側端子７１ａ側で補償するものである。
そして、この実施形態においても、前記の各実施形態と同様に、液晶表示装置の基本回路部分は図５に示した構成になっており、その基本回路部分についての説明は省略する。
また、各表示画素ＰＸに係る補助容量６２の基板側端子７１ａが基板７１自体で構成されている点も前記の各実施形態の場合と同様である。
【００４２】
この実施形態の特徴は、列信号線駆動回路５１に対する多相化画像信号の入力回路とＣＣ信号の印加回路に図４に示すような信号処理回路が適用されている点にある。
その信号処理回路は、多相化されたディジタル画像データＶＩＤＥＯｄ［ｉ］に対応する各信号線に設けられた各単相処理部３−ｉと、各画像データＶＩＤＥＯｄ［ｉ］を用いて補償データを作成する補償データ作成部４とからなり、各単相処理部３−ｉは遅延回路３１とＤ／Ａ変換器３２の直列回路として構成されており、また補償データ作成部４は加算回路４１と乗算回路４２と加算回路４３とＤ／Ａ変換器４４の直列回路として構成されている。
【００４３】
そして、各単相処理部３−ｉでは、転送されてくる各画像データＶＩＤＥＯｄ［ｉ］をクロック信号ＣＬＫに同期した遅延回路３１で遅延させ、Ｄ／Ａ変換器３２でアナログ信号へ変換して列信号線駆動回路５１へ出力させる。
一方、補償データ作成部４では、加算回路４１がｎ相分の各画像データＶＩＤＥＯｄ［ｉ］を全て加算し、乗算回路４２がその加算データに対して一定の係数Ａｃを乗算し、更に、加算回路４３によって乗算回路４２が求めた前記の乗算値Ｖｑに対して本来のＣＣ信号を与えるディジタル信号ＣＣｄを加算し、その加算データをＤ／Ａ変換器４４でアナログ信号ＣＣｑに変換する。
また、その変換後のアナログ信号ＣＣｑは、図５の液晶表示装置における基板７１に印加され、各表示画素ＰＸに係る補助容量６２の基板側端子７１ａに対する共通の電圧とされる。
【００４４】
ここで、乗算回路４２の乗算係数Ａｃは実施形態１で説明した値に相当する。
即ち、加算回路４１によるｎ相分の各画像データＶＩＤＥＯｄ［ｉ］を全て加算した結果にその係数Ａｃを乗算した値が、図５の液晶表示装置において画像信号ＶＩＤＥＯ［ｉ］が組単位で各表示画素ＰＸの補助容量６２に書き込まれた際の基板側端子７１ａの電圧変動分Ｖｑに相当するように設定されている。
【００４５】
また、各単相処理部３−ｉに遅延回路３１が設けられているのは、補償データ作成部４で前記の演算処理に時間を要するためであり、Ｄ／Ａ変換器３２でアナログ信号へ変換した画像信号ＶＩＤＥＯ［ｉ］が列信号線駆動回路５１によって各表示画素ＰＸの補助容量６２に書き込まれるタイミングと、補償データ作成部４が同一時点の画像信号ＶＩＤＥＯｄ［ｉ］に基づいて作成した前記のアナログ信号ＣＣｑが出力するタイミングとが同期するようになっている。
【００４６】
従って、この実施形態によれば、組単位で画像信号ＶＩＤＥＯ［ｉ］が各表示画素ＰＸの補助容量６２に書き込まれる際に、各表示画素ＰＸに係る補助容量６２の基板側端子７１ａの電圧が本来のＣＣ信号に前記の電圧変動分Ｖｑを加算した電圧（アナログ信号ＣＣｑの電圧）に設定されており、画像信号のクロストークによる電圧変動分を補償した画像表示を実行できる。
即ち、実施形態１の場合と同様に、図５の液晶表示装置において、組単位でクロストーク量を相殺した画像信号ＶＩＤＥＯ［ｉ］による表示が可能になる。
また、基板７１上に複雑なＣＣ信号の印加用回路を形成する必要がないことも実施形態１の場合と同様である。
【００４７】
更に、乗算回路４２へ入力される乗算係数Ａｃのディジタル信号が出力電圧を可変設定できる定電圧回路とＡ／Ｄ変換器で構成できることも実施形態１の場合と同様であり、また本来のＣＣ信号を与えるディジタル信号ＣＣｄもそれと同様の回路構成で実現できることは当然である。
【００４８】
以上の各実施形態では、多相化されたディジタル画像データＶＩＤＥＯｄ［ｉ］に対する信号処理回路について説明したが、本発明はアナログ画像信号に対する信号処理回路として構成することも可能である。
その場合には、Ｄ／Ａ変換器１３，３２，４４は不要であり、他の回路を同様の機能を備えたアナログ回路に置き換えて構成すればよい。
【００４９】
【発明の効果】
本発明の液晶表示装置は、以上の構成を有していることにより、次のような効果を奏する。
請求項１の発明は、多相化された画像信号によって表示を行う液晶表示装置において、組単位で表示画素に書き込まれる画像信号が補助容量の基板側端子を通じてクロストークする不具合を、多相化画像信号の列信号線駆動回路に対する入力経路にクロストークによる電圧変動分を補償する信号処理回路を設けることにより解消し、高い画像品質を実現する。
また、同様の目的で創作された従来技術の特願２００２−１９９３５５号のように、補助容量の基板側端子に対する所定電圧を印加する回路を基板上に複雑な構成で形成する必要がなく、前記の所定電圧を基板自体又は基板に形成した導体層を共通の印加回路にできるため、液晶表示装置を製造するための半導体プロセスが簡素化できる。
請求項２の発明は、請求項１の発明が多相化画像信号に対する組単位での補償を行っているのに対して、画素単位での画像信号に対する補償を可能にし、よりきめ細かな調整によって更に高品質な画像表示を実現する。
請求項３の発明は、各表示画素における補助容量の基板側端子に所定電圧を印加する信号経路に画像信号のクロストークによる電圧変動分を補償する信号処理回路を設けたことにより、請求項１の発明と同様の効果を実現する。
【図面の簡単な説明】
【図１】本発明の液晶表示装置の実施形態１に係る信号処理回路の回路図である。
【図２】乗算回路の乗算係数の概念を説明するためのグラフである。
【図３】実施形態２に係る信号処理回路の回路図である。
【図４】実施形態３に係る信号処理回路の回路図である。
【図５】多相化画像信号により画像表示を行う従来の液晶表示装置の回路図である。
【図６】主に行信号線駆動回路の動作タイミングを示すタイミングチャートである。
【図７】主に列信号線駆動回路の動作タイミングを示すタイミングチャートである。
【図８】画像信号のクロストークを抑制することを目的とした従来技術に係る液晶表示装置（特願２００２−１９９３５５号）の回路図である。
【図９】表示画素の断面構造図である。
【符号の説明】
１−ｉ，１ａ−ｉ，３−ｉ：（但し、ｉ＝１〜ｎ）…単相処理部、２，４…補償データ作成部、１１，３１…遅延回路、１２，１２ａ，４１，４３…加算回路、１３，３２，４４…Ｄ／Ａ変換器、２１…加算回路、１４，２２，４２…乗算回路、５１…列信号線駆動回路、５２…行信号線駆動回路、６１…トランジスタ（スイッチング用電界効果型トランジスタ）、６２…補助容量（信号電圧保持用のコンデンサ）、６３…画素電極、６４…共通電極、６５…液晶部材、７１…基板、７１ａ…補助容量の基板側端子、７２…導体部、７３…誘電体層、７４…透明基板、７５…絶縁層、７６，７７…液晶配向膜、Ａｃ…乗算係数、ＣＣ…ＣＣ信号、ＣＣｄ…本来のＣＣ信号を与えるディジタル信号、ＣＣｑ…補償した後のアナログＣＣ信号、ＣＬＫ…クロック信号、ＣＯＭ…ＣＯＭ信号、Ｄ（Ｋ）１〜Ｄ（Ｋ）ｎ：（但し、Ｋ＝１〜Ｘ）…列信号線、Ｇ１〜Ｇｊ…行信号線、ＨＣＫ…水平クロック信号、ＨＳＴ…水平スタート信号、ＶＩＤＥＯ［ｉ］：（但し、ｉ＝１〜ｎ）…多相化されたアナログ画像信号、ＶＩＤＥＯｄ［ｉ］：（但し、ｉ＝１〜ｎ）…多相化されたディジタル画像データ、ＶＩＤＥＯ（Ｋ）［ｉ］：（但し、ｉ＝１〜ｎ）…多相化された画像信号の組、ＶＣＫ…垂直クロック信号、ＶＳＴ…垂直スタート信号、ΔＶｑ…電圧変動量。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal display device, and in particular, is applied to a projection type display, a viewfinder, a head mounted display, etc., in which display is performed by a multi-phased image signal, and crosstalk of an image signal written to a display pixel in a set unit. The present invention relates to an improvement for displaying a high-quality image while suppressing image quality.
[0002]
[Prior art]
In an active matrix type liquid crystal display device, display pixels are formed in a matrix on a substrate, and each display pixel includes a switching field-effect transistor (hereinafter simply referred to as a “transistor”) and a capacitor for holding a signal voltage. (Hereinafter referred to as “auxiliary capacitance”), a pixel electrode, a common electrode, and a liquid crystal member. Conventionally, as a solution in a case where the response characteristic of the transistor or the frequency characteristic of the auxiliary capacitance is not sufficient, for example, As disclosed in the following Patent Documents 1 to 4, etc., an image signal is converted into an n-phase (n is a natural number of 2 or more) multi-phase signal and input.
That is, the occupied frequency band is reduced to 1 / n by making the original image signal multi-phase, and the above problem is solved by supplying the signal to the liquid crystal display device through n input signal lines.
[0003]
First, the liquid crystal display device has a circuit configuration as shown in FIG. 5, and includes a large number of display pixels PX arranged in a matrix, a column signal line driving circuit 51 for driving the display pixels PX, and a row signal. The row signal line drive circuit 52 controls ON / OFF of the transistors of the display pixels PX of each row through each row signal line G1... Gj, and the column signal line drive circuit 51 controls each signal line D (1). ) 1... D (X) n, an image signal is written to the storage capacitor of the display pixel PX of each column.
Specifically, on a single-crystal silicon substrate, a plurality of column signal lines D (1) 1... D (X) n and a plurality of row signal lines G1. D (X) n and G1... Gj, one display pixel PX is arranged and formed at each intersection, and the column signal lines D (1) 1. Assuming that the total number of (X) n is i, a display panel having (i × j) display pixels is configured.
In FIG. 5, in order to explain the image display operation procedure based on the multi-phase image signal, the column signal lines D (1) 1... D (X) n are connected to D (K) 1 to D (K) n [ However, K = 1 to X] are expressed separately in X sets.
[0004]
Next, each display pixel PX includes the transistor 61, the auxiliary capacitor 62, the pixel electrode 63, the common electrode 64, and the liquid crystal member 65 as described above.
That is, the display pixel PX (1, 1) at the intersection of the column signal line D (1) 1 and the row signal line G1 will be described. The column signal line D (1) 1 is connected to the drain of the transistor 61 by the control terminal. A row scanning line G1 is connected to a certain gate, an auxiliary capacitor 62 and a pixel electrode 63 are connected to a source, and a liquid crystal member 65 is held between the pixel electrode 63 and the common electrode 64. .
Further, a COM signal is applied to the common electrode 64 of all the display pixels PX, and a CC signal is applied to one terminal of the auxiliary capacitance 62.
[0005]
The cross-sectional structure of each display pixel PX is shown in FIG. 9, in which the pixel electrode 63 is connected to the source of the transistor 61 formed on the surface of the substrate 71, and the conductor 72 is laterally connected from the connection portion. The auxiliary capacitor 62 is formed continuously and has a dielectric layer 73 formed between the substrate 71 and the conductor 72.
Accordingly, the conductor layer 72 corresponds to one terminal of the auxiliary capacitor 62, and the substrate 71 corresponds to the other terminal. Hereinafter, the latter terminal will be described as a “substrate-side terminal 71a”.
A transparent substrate 74 is disposed above the pixel electrode 63 with a liquid crystal member 65 interposed therebetween, and a common electrode 64 that is a transparent conductive film is formed on the transparent substrate 74.
Reference numeral 75 denotes an insulating layer, and reference numerals 76 and 77 denote liquid crystal alignment films coated on the pixel electrode 63 side and the transparent substrate 74 side, respectively.
Therefore, in the liquid crystal display device, the COM signal is applied to the common electrode 64 on the transparent substrate 74 side, and the CC signal is applied to the substrate side terminal 71a of the auxiliary capacitor 62. Since it is constituted by the conductor layer formed on the substrate 71 itself or the substrate 71, the CC signal is also commonly applied through the substrate 71 or the conductor layer.
[0006]
Next, the column signal line drive circuit 51 is configured by a shift register and a sampling switch (not shown), and receives multiple signals transferred based on a horizontal start signal HST and a horizontal clock signal HCK input from an external circuit. Phased image signals: VIDEO (K) [i] [i = 1 to n] are sequentially sampled at predetermined timing, and column signal lines D (1) 1 to D (1) n, D (2) 1 to D (2) Output sequentially to n,..., D (X) 1 to D (X) n.
That is, the column signal line drive circuit 51 simultaneously takes in the multi-phase image signals from the n input terminals, and sets the column signal lines D (K) 1 to D (K) n: [K = 1 To X].
[0007]
Specifically, assuming that one horizontal scanning period is H, the multiphased image signal is sampled every H / X period, and the n sampling signals in the first H / X period are the column signal lines D (1 ) 1 to D (1) n in parallel, and n sampling signals in the next H / X period are output in parallel to column signal lines D (2) 1 to D (2) n, and thereafter, in the same manner. Thus, the n sampling output signals in the last H / X period of one horizontal scanning period are output in parallel to the column signal lines D (X) 1 to D (X) n.
[0008]
On the other hand, the row scanning line driving circuit 52 is configured as a circuit including a shift register and a selector (not shown). The row scanning line driving circuit 52 performs a scanning operation for one frame based on a vertical start signal VST and a vertical clock signal VCK input from outside. The operation of sequentially supplying the scanning signals (selection signals) to the row scanning lines G1 to Gj is repeated for each frame.
When the scanning signal is supplied to the row scanning line G1, the scanning signal is applied to the gates of the transistors 61 related to the (K × n) display pixels PX in the first row, and the scanning signals are applied to the gates. The transistor 61 is turned on (selected state), and conduction between the drain and source of each transistor 61 is performed.
[0009]
As a result, the image signals sampled by the column signal line driving circuit 51 are converted into column signal lines D (1) 1 to D (1) n, D (2) 1 to D (2) n,. X) 1 to D (X) n are sequentially and simultaneously output in parallel, and the column signal lines D (1) 1 to D (1) n, D (2) 1 to D (2) n,. D (X) 1 to D (X) n are simultaneously accumulated in the respective auxiliary capacitors 62 through the drain and source of each transistor 61 to which D (X) n is connected.
Then, the row scanning line driving circuit 52 sequentially outputs the scanning signals from each of the row signal lines G1 to Gj in each horizontal scanning period H in the column signal line driving circuit 51, and corresponds to the row signal line that has output the scanning signal. The column signal lines D (1) 1 to D (1) n, D (2) 1 to D (2) n,..., D (X) 1 to D (X ) N is accumulated.
As a result, image signals for one frame are accumulated in the auxiliary capacitors 62 of all the display pixels PX from the first row (1) to the last row (j), and are stored in the auxiliary capacitor 62 in each display pixel PX. A voltage corresponding to the image signal is supplied to the pixel electrode 63.
[0010]
On the other hand, in FIG. 5, the COM signal is applied from the common electrode 64 on the transparent substrate 74 side shown in FIG. 9, but has a voltage of the same polarity as the polarity of the image signal. The voltage is set to the threshold voltage of the liquid crystal member 65.
Then, the image signal is inverted for each frame or each field in order to drive the liquid crystal member 65 with an alternating current. Causes a light modulation operation.
The CC signal adjusts the voltage of the image signal stored in the auxiliary capacitor 62, and a voltage for ensuring an appropriate light modulation operation of the liquid crystal is shared with the substrate-side terminal 71a of each display pixel PX. Has been applied.
[0011]
Next, the schematic operation of the liquid crystal display device described above will be described more specifically with reference to the timing charts of FIGS.
Here, FIG. 6 mainly shows the operation timing of the row signal line drive circuit 52, and FIG. 7 mainly shows the operation timing of the column signal line drive circuit 51.
[0012]
6A shows an input waveform of a multi-phase image signal input to the column signal line drive circuit 51. The image signal becomes a non-inverted signal in the frame period A and becomes an inverted signal in the frame period B. ing.
The VST and VCK signals shown in (b) and (c) are supplied to the row scanning line drive circuit 52.
The shift register incorporated in the row scanning line driving circuit 52 is a j-stage shift register that shifts the input VST by one stage at the rising edge of VCK and outputs this as a scanning signal. A scanning signal shown in (d) is output from each shift stage of the circuit 52 to the row signal lines G1, G2,..., Gj by a built-in selector. G1, G2,..., Gj, but not during period B.
Therefore, in the period A, the scanning signals are sequentially output to the row scanning lines G1, G2,..., Gj, and the transistors 61 in each row are turned on, and in the period B, the transistors 61 in each row are turned off.
The COM signal and the CC signal shown in (e) and (f) of FIG. 6 are signals of the above-described predetermined potential, respectively, and are applied to the common electrode 64 and the substrate-side terminal 71a of each auxiliary capacitor 62.
[0013]
On the other hand, regarding the operation timing of the column signal line drive circuit 51 (FIG. 7), the column signal line drive circuit 51 has a multi-phase image signal schematically shown in FIG. HST and HCK of (d) are input.
Here, HST and HCK are signals for controlling the operation of the shift register incorporated in the column signal line drive circuit 51.
In the column signal line driving circuit 51, based on the HST synchronized with the VST of the row signal line driving circuit 52 shown in (b), the multi-phase image signal of (e) is synchronized with the HCK and the column signal line D (1). ) 1 to D (1) n, D (2) 1 to D (2) n,..., D (X) 1 to D (X) n.
7E and 7F are the COM signal (e) and the CC signal (f) shown in FIG.
[0014]
Therefore, in the liquid crystal display device shown in FIG. 5, the column signal line drive circuit 51 and the row signal line drive circuit 52 repeatedly perform the operation of writing the multi-phase image signal to each display pixel PX in a set unit while synchronizing with each other. In the frame period A, the image signal is accumulated in the storage capacitor 62 of each display pixel PX, and in the frame period B, the liquid crystal member 65 in the area corresponding to each display pixel PX performs a light modulation operation, thereby continuously forming the frame. Display the image.
[0015]
By the way, in the above-mentioned liquid crystal display device, the substrate-side terminal 71a to which the CC signal is applied as described above is the substrate 71 itself or a conductor layer formed on the substrate, and the CC signal is the auxiliary capacitance of all the display pixels PX. 62 are commonly applied.
Such a common application method of the CC signal is not limited to the liquid crystal display device for inputting the image signal in multi-phase as described above, but also to a conventional general liquid crystal display device for serially transferring the image signal. In any case, in any case, crosstalk of the image signal accumulated in each auxiliary capacitor 62 occurs via the common application circuit of the CC signal to the auxiliary capacitor 62 of each display pixel PX, and as a result, the image There is a problem that display quality is deteriorated.
That is, when an image signal is written to the auxiliary capacitor 62 in a unit of a row or the above-mentioned group, a charge moves through the common application circuit, and the voltage of the auxiliary capacitor 62 and the pixel electrode 63 fluctuates. This causes disturbance of the displayed image.
In particular, in the liquid crystal display device described above, the multi-phase image signals are simultaneously written into the auxiliary capacitor 62 in units of sets, and the voltage fluctuation amount is relatively large, so that the influence on the image display quality is increased. .
[0016]
In view of this problem, the present inventor has paid attention to the fact that the above-mentioned liquid crystal display device has made the image signal polyphase, and as shown in FIG. Among the column signal lines D (K) 1 to D (K) n: [K = 1 to X], the substrate side of the auxiliary capacitor 62 of the display pixel PX connected to the same-order column signal line of each set. A circuit configuration in which a terminal (terminal to which a CC signal is applied) is commonly connected to only signal lines in the same order among n number of externally guided CC signal lines CC1 to CCn has been proposed (Japanese Patent Application No. 2002-199355). issue).
According to the liquid crystal display device according to this proposal, CC signals are applied from independent CC signal lines CC1 to CCn for each group of display pixels PX aligned in the vertical direction in each group, and at least a display adjacent in the horizontal direction is applied. Crosstalk between the pixels PX can be prevented, and the display quality of an image can be improved.
[0017]
[Patent Document 1]
JP-A-11-007270
[Patent Document 2]
JP-A-11-133932
[Patent Document 3]
JP-A-11-133933
[Patent Document 4]
JP-A-11-202841
[0018]
[Problems to be solved by the invention]
However, according to the liquid crystal display device of the above-mentioned proposal (Japanese Patent Application No. 2002-199355), crosstalk through the auxiliary capacitor 62 of the display pixel PX can be suppressed. However, as shown in FIG. The CC signal lines CC1 to CCn are separately formed, and each CC is connected to the substrate-side terminal 71a of the auxiliary capacitor 62 associated with the display pixel PX connected to the same order column signal line of each set (K = 1 to X). A circuit for connecting the signal lines CC1 to CCn must also be formed.
Specifically, the substrate-side terminal 71a of the auxiliary capacitor 62 of the display pixel PX connected to the same column signal line can be formed as a common conductor layer. Connection circuits for the CC1 to CCn and the above-mentioned conductor layer must be formed on the substrate, and the number of signal lines for configuring them is very large.
Therefore, it is effective in solving the problem of the crosstalk of the image signal, but the substrate of the liquid crystal display device becomes large in order to secure the wiring area of the circuit for applying the CC signal, and the yield is reduced due to the complexity of the semiconductor process. There is a problem that reduction and an increase in manufacturing cost are caused.
[0019]
On the other hand, in the circuit configuration shown in FIG. 5, although there is a problem related to crosstalk of image signals, the substrate 71 itself is entirely used as a substrate-side terminal 71a for all display pixels PX constituting a screen. Since a signal can be applied, the circuit configuration on the substrate is simplified.
[0020]
Accordingly, the present invention provides a liquid crystal display device that performs image display by using a multi-phase image signal, while reducing the crosstalk of the image signal of each display pixel PX by using the general configuration shown in FIG. It was created with the aim of providing a method that can be suppressed.
[0021]
[Means for Solving the Problems]
First, a liquid crystal display device to which the present invention is applied includes a switching transistor, an auxiliary capacitor, and a pixel electrode. One terminal of the auxiliary capacitor is connected to an output terminal of the switching transistor and the pixel electrode, and the other terminal is connected. A first substrate in which a number of display pixels having a structure configured on the substrate side are arranged in a matrix, and a transparent substrate arranged to face the first substrate, wherein A second substrate provided with a common electrode in a region corresponding to the arrangement region, a liquid crystal member sealed and held between the first substrate and the second substrate, and a switching transistor of each display pixel aligned in a column direction Are divided into n sets (n is a natural number of 2 or more) as one set, and the input image signal polyphased into n phases is connected in parallel to each set of column signal lines. Sun pudding A column signal line driving circuit for sequentially executing the output operation in units of the set, and sequentially outputting a row selection signal to each row signal line connected to the on / off control terminal of the switching transistor of each display pixel aligned in the row direction. A row scanning line driving circuit for turning on / off a switching transistor of a display pixel in a row unit; and applying a predetermined voltage to a substrate-side terminal of each auxiliary capacitor in the first substrate and a common electrode of the second substrate. In the applied state, the column signal line driving circuit and the row scanning line driving circuit operate in synchronization with each other to display an image.
That is, this is a liquid crystal display device that handles a multi-phase image signal described in the related art, and a method of applying a predetermined voltage in common to the substrate-side terminal of each auxiliary capacitor in the first substrate as in the circuit configuration of FIG. Is assumed.
[0022]
According to a first aspect of the present invention, in the liquid crystal display device, a first addition circuit that adds each signal at the same time point of the image signal that has been polyphased into n phases, and an addition result obtained by the first addition circuit And a first multiplication circuit for multiplying the multiplication result by a constant coefficient value in each input circuit of image signals for n phases to the column signal line driving circuit. A second addition circuit that adds the image signal at the time when the first addition circuit has performed the addition processing and outputs the added image signal to the column signal line driving circuit. When an image signal for n phases is accumulated in the auxiliary capacitance by the signal line driving circuit in a set unit, the value is set as a value for compensating for a voltage fluctuation occurring at a terminal of the auxiliary capacitance on the substrate side. The present invention relates to a liquid crystal display device.
[0023]
According to the present invention, a result obtained by adding image signals for n phases multi-phased by the first addition circuit at the same time is multiplied by a constant coefficient value by the first multiplication circuit, and the multiplication result is subjected to the second addition. The circuit adds the image signal of each phase.
Here, the addition result of the first addition circuit is generated at a terminal on the substrate side of each auxiliary capacitance when the column signal line driving circuit samples and outputs image signals in parallel in sets and accumulates them in the auxiliary capacitance of the display pixels. It shows a value that is almost proportional to the voltage fluctuation that occurs.
Accordingly, a second adder circuit is provided which multiplies the above-mentioned addition result by a coefficient value set as a value for compensating the voltage variation by the first multiplication circuit, and provides the multiplication result in each input circuit of the image signal of each phase. By adding to each image signal, an image signal in which the above-mentioned voltage variation is compensated is written to the auxiliary capacitance of each display pixel, and each image signal passes through the substrate side terminal of each auxiliary capacitance. Of the displayed image due to the crosstalk can be prevented.
Further, each circuit of the present invention may be inserted in the input path of the multi-phase image signal, and is not necessarily required to be formed on the substrate. Even if it is formed on the substrate, it is different from the formation area of each display pixel. Therefore, the semiconductor process is not complicated.
[0024]
According to a second aspect of the present invention, in the liquid crystal display device based on the above premise, a first addition circuit for adding each signal at the same time point of the image signal multi-phased into n phases and a column signal line driving circuit Circuits are provided independently as circuits corresponding to the respective input circuits for the n-phase image signals, and multiply the addition result obtained by the first addition circuit by a coefficient value set individually for each of the input circuits. A second multiplying circuit and n-phase image signal input circuits for the column signal line driving circuit are independently provided in respective input circuits, and a multiplication result of the second multiplying circuit and the first adding circuit execute addition processing. A third addition circuit for adding the image signal at the time of the addition and outputting the added signal to the column signal line driving circuit, wherein the multiplication coefficient value of each of the second multiplication circuits is calculated for n phases by the column signal line driving circuit. The image signal is stored in the storage capacity When accumulating, the value is set as a value for compensating for a voltage variation generated at a substrate-side terminal of each of the storage capacitors in each display pixel in a column direction connected to the input circuit corresponding to the second multiplication circuit. A liquid crystal display device characterized by the above.
[0025]
In the first aspect, the first multiplication circuit multiplies the addition result of the polyphased signal by the first addition circuit by a constant coefficient value, and the multiplication result is uniformly n by the second addition circuit. The addition is performed for each image signal of the phase.
However, a circuit (a CC signal application circuit in FIG. 5) connected to a substrate-side terminal of an auxiliary capacitor related to each display pixel of the first substrate manufactured by a semiconductor process is formed uniformly in the row direction. For example, the circuit pattern may be different between the even-numbered column and the odd-numbered column.
In such a case, for each display pixel aligned in the row direction, the amount of voltage fluctuation generated at the substrate-side terminal of each auxiliary capacitor is different, and display image disturbance is caused by crosstalk between image signals in the row direction. Will happen.
According to the second aspect, the second multiplying circuit is provided independently as a circuit corresponding to each input circuit of the image signal for n phases, and the addition obtained by the first adding circuit by each second multiplying circuit is provided. The result is multiplied by an individual multiplication coefficient value, and the multiplication result is added to the image signal of each phase by a third addition circuit provided independently in each input circuit.
Therefore, by individually adjusting the multiplication coefficient values of the respective second multiplication circuits, the crosstalk between the image signals caused by the different circuit patterns between the even-numbered columns and the odd-numbered columns can be finely adjusted. And a higher quality image can be obtained.
[0026]
According to a third aspect of the present invention, in the liquid crystal display device based on the above premise, a first adder circuit for adding the respective signals at the same time point of the image signal multi-phased into n phases, and the first adder circuit determine A first multiplier circuit for multiplying the added result by a constant coefficient value; a board-side circuit for applying a voltage to a board-side terminal of each auxiliary capacitor in the first board; A fourth adder circuit that is provided between an external voltage supply circuit and a multiplication result of the first multiplication circuit to an output voltage of the voltage supply circuit and outputs the result to the substrate-side circuit. The multiplication coefficient value in the first multiplying circuit is set to a voltage variation generated at a substrate-side terminal of the auxiliary capacitor when image signals for n phases are accumulated in the auxiliary capacitor in sets by the column signal line driving circuit. Is set as a value to compensate for According to the liquid crystal display device according to claim.
[0027]
According to the present invention, the first and second inventions compensate for the voltage fluctuation generated at the substrate-side terminal of each auxiliary capacitor on the input circuit side of each of the multi-phased image signals. The compensation is performed on the circuit side that applies a predetermined voltage to the terminals on the substrate side in common. The functions of the first addition circuit and the first multiplication circuit according to the present invention are the same as those of the first invention, but the result of the multiplication causes a voltage to be applied to the substrate-side terminal of each auxiliary capacitance in the first substrate. To a fourth addition circuit provided between the substrate-side circuit and an external voltage supply circuit for outputting the original voltage, and the fourth addition circuit multiplies the output voltage of the voltage supply circuit by the multiplication. The results are added and output to the board side circuit.
Therefore, the above-mentioned voltage fluctuation is compensated on the substrate side circuit side, and similarly to the first and second inventions, the display image by the crosstalk of each image signal through the substrate side terminal of each auxiliary capacitance is provided. Disturbance can be prevented.
Further, it is not necessary to form each circuit on the substrate, and even if the circuits are formed on the substrate, the semiconductor process is not complicated, similarly to the first and second inventions.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the liquid crystal display device of the present invention will be described in detail with reference to FIGS.
[Embodiment 1]
The basic circuit portion of the liquid crystal display device in this embodiment is the same as that shown in FIG. 5, and the circuit configuration and the image display operation by the multi-phase image signal are as described in the section of the prior art. Here, their description is omitted.
In this embodiment, the substrate-side terminal 71a of the auxiliary capacitor 62 related to each display pixel PX is formed by the substrate 71 itself as shown in FIG. 9, and the CC signal is transmitted to the display pixel PX through the substrate 71. It is assumed that they are commonly applied.
[0029]
The feature of this embodiment is that a signal processing circuit as shown in FIG. 1 is applied to an input circuit of a multi-phase image signal to the column signal line driving circuit 51.
The signal processing circuit includes a single-phase processing unit 1-i provided for each signal line corresponding to each digital image data VIDEOd [i] multiplied into n phases, and all n-phase image data VIDEOd. The single-phase processing unit 1-i is configured as a series circuit of a delay circuit 11, an adder circuit 12, and a D / A converter 13 that generates compensation data using [i]. In addition, the compensation data creation unit 2 is configured as a series circuit of an addition circuit 21 and a multiplication circuit 22.
Here, “i” is an index number (1 to n) associated with each circuit multi-phased into n phases, and the same applies to this embodiment and the following embodiments 2 and 3.
Then, in the compensation data creating unit 2, the addition circuit 21 adds all the image data VIDEOd [i] for the n phases, and the multiplication circuit 22 multiplies the addition data: Vq by a constant coefficient Ac. The signal is output to the addition circuit 12 on the single-phase processing unit 1-i side.
[0030]
In each of the single-phase processing units 1-i, the image data VIDEOd [i] is transferred by the delay circuit 11 synchronized with the CLK and output to the addition circuit 12 after a certain period of time. Since the addition / multiplication operation requires a little time, the timing at which the multiplication result is output from the compensation data generation unit 2 and the image data VIDEOd [i] are input to the addition circuit 12 on each single-phase processing unit 1-i side. This is for synchronization with the timing.
Therefore, the multiplication result of the compensation data creation unit 2 added to the image data VIDEOd [i] by the addition circuit 12 of each single-phase processing unit 1-i is based on the image data VIDEOd [i] obtained at the same time. This is added to each image data VIDEOd [i] by the addition circuit 12 on each single-phase processing unit 1-i side.
[0031]
Incidentally, the multiplication coefficient Ac of the multiplication circuit 22 in the compensation data creation unit 2 is set as a constant described below.
Now, assuming that each of the n-phase image data VIDEOd [i] is input to the column signal line drive circuit 51 as an analog image signal VIDEO [i] via only the D / A converter 13, as described above. In the liquid crystal display device of FIG. 5, those image signals VIDEO [i] are written into the auxiliary capacitors 62 of the respective display pixels PX in pairs via the column signal lines D (K) [i].
[0032]
In this case, although a CC signal of a predetermined voltage is applied to the substrate 71 corresponding to the substrate-side terminal 71a of each auxiliary capacitance 62, the electric charge stored in each auxiliary capacitance 62 is small but passes through the substrate 71 side. Then, the voltage flows to the other set of display pixels PX side, whereby the voltage of the substrate side terminal 71a of each display pixel PX to which the image signal VIDEO [i] is written fluctuates, and consequently the voltage of the pixel electrode 63 fluctuates. Therefore, an appropriate pixel display is not obtained.
That is, crosstalk of the image signal VIDEO [i] occurs in each set, and the display quality of the image is impaired.
[0033]
On the other hand, as shown in FIG. 2, the voltage fluctuation amount Vq of the pixel electrode 63 corresponding to the crosstalk amount tends to be substantially proportional to the added value of the image signal VIDEOd [i] written at the same time.
Therefore, in this embodiment, the multiplication coefficient Ac is set as an increase rate (proportional constant) of the voltage fluctuation amount of the substrate-side terminal 71a with respect to the added value of the image signal VIDEOd [i], and is set to the image signal VIDEOd [i]. By multiplying the added value of [i], the voltage fluctuation amount Vq of the substrate side terminal 71a is obtained.
[0034]
Therefore, as described above, the voltage fluctuation amount Vq obtained by the compensation data creation unit 2 is added to each image data VIDEOd [i] by the addition circuit 12 of each single-phase processing unit 1-i, and the result is D / A. When converted into an analog signal by the converter 13, an image signal VIDEO [i] in which the voltage fluctuation amount Vq is compensated in advance is obtained.
Then, since the n-phase image signal VIDEO [i] is output from the D / A converter 13 to the column signal line drive circuit 51, in the liquid crystal display device of FIG. Display by the image signal VIDEO [i] becomes possible.
In this embodiment, as in a general liquid crystal display device, the substrate 71 itself is a common substrate-side terminal 71a for the auxiliary capacitors 62 of all the display pixels PX. Since it is sufficient to apply the voltage, it is not necessary to form a complicated circuit for applying the CC signal on the substrate unlike the liquid crystal display device shown in FIG.
[0035]
The multiplication coefficient Ac is input to the multiplication circuit 22 as a digital signal. A voltage obtained from a constant voltage circuit (not shown) capable of variably setting an output voltage is converted by an A / D converter (not shown). What is necessary is just to convert into a digital signal and to input it.
The value of the multiplication coefficient Ac can be obtained by experimentally calculating a voltage variation using various types of image data VIDEOd [i] and adjusting the output voltage on the constant voltage circuit side.
[0036]
[Embodiment 2]
First, the basic circuit portion of the liquid crystal display device in this embodiment has the configuration shown in FIG. 5, as in the case of the first embodiment.
It is also assumed that the substrate-side terminal 71a of the auxiliary capacitor 62 related to each display pixel PX is constituted by the substrate 71 itself as shown in FIG.
The feature of this embodiment resides in that a signal processing circuit as shown in FIG. 3 is applied to the input circuit of the multi-phase image signal to the column signal line driving circuit 51.
[0037]
The feature of this embodiment resides in that a signal processing circuit as shown in FIG. 3 is applied to the input circuit of the multi-phase image signal to the column signal line driving circuit 51.
As apparent from a comparison between FIG. 3 and FIG. 1, the difference between the signal processing circuit of this embodiment and the signal processing circuit of the first embodiment is as follows.
First, in the first embodiment, the compensation data creation unit 2 is configured by the addition circuit 21 and the multiplication circuit 22. In this embodiment, however, the multiplication circuit 14 is independent of each single-phase processing unit 1a-i. The one that is incorporated and corresponds to the compensation data creation unit 2 of the first embodiment is configured by the addition circuit 21 and the multiplication circuits 14 of the single-phase processing units 1a-i.
The addition circuit 12a of each single-phase processing unit 1a-i adds the multiplication result of the multiplication circuit 14 to the image signal VIDEOd [i] input to each single-phase processing unit 1a-i. .
[0038]
In this embodiment, individual multiplication coefficients Ac [i] are set for the multiplication circuits 14 of the single-phase processing units 1a-i.
That is, when the column signal line drive circuit 51 writes the n-phase image signals VIDEO [i] to the auxiliary capacitor 62 of each display pixel PX in pairs, the single-phase processing unit Ac [i] It is set as the rate of increase (proportionality constant) of the individual voltage fluctuation generated at the substrate-side terminal 71a of the display pixel PX corresponding to 1a-i.
[0039]
In this embodiment, based on the configuration shown in FIG. 3, the adding circuit 21 adds all the n-phase image data VIDEOd [i], and applies the single-phase processing unit 1a to the added data: Val The -i multiplication circuit 14 multiplies the multiplication coefficient Ac [i] to create compensation data: ΔVq [i] = Ac [i] * Val, and the addition circuit 12a outputs the compensation data: ΔVq [i] to the image signal. Add to VIDEOd [i].
In this case, in the first embodiment, the compensation data ΔVq created by the compensation data creation unit 2 is uniformly added to each image data VIDEOd [i]. In this embodiment, each multiplication coefficient Ac [i] is individually added. Since the adjustment can be set, compensation data ΔVq [i] corresponding to the characteristics of the display pixel PX into which each image signal VIDEOd [i] is written can be added to each image data VIDEOd [i].
[0040]
Therefore, the circuit (the CC signal application circuit in FIG. 5) connected to the substrate-side terminal 71a of the auxiliary capacitor 62 in each display pixel PX manufactured in the semiconductor process has a circuit pattern of even-numbered columns and odd-numbered columns. In the case where the voltage variation generated at the substrate-side terminal 71a differs for each of the columns, the multiplication coefficient Ac [i] is individually adjusted in accordance with each voltage variation. In addition, crosstalk generated between image signals of the display pixels PX adjacent in the row direction can be prevented.
In addition, when the image signals VIDEO [i] for n phases are written in the storage capacitor 62 of each display pixel PX in a unit of a set, it is supposed that the above-mentioned voltage fluctuation becomes large at a boundary between the sets. According to the device of this embodiment, it is possible to cope with such a phenomenon.
[0041]
[Embodiment 3]
In this embodiment, the voltage variation Vq of the pixel electrode 63 due to crosstalk is compensated in advance on the input side of the image signal VIDEO [i], whereas in each of the above embodiments, compensation is made on the substrate side terminal 71a side. Is what you do.
Also in this embodiment, as in the above embodiments, the basic circuit portion of the liquid crystal display device has the configuration shown in FIG. 5, and the description of the basic circuit portion will be omitted.
Further, the point that the substrate-side terminal 71a of the auxiliary capacitor 62 related to each display pixel PX is constituted by the substrate 71 itself is the same as in the above-described embodiments.
[0042]
The feature of this embodiment resides in that a signal processing circuit as shown in FIG. 4 is applied to the input circuit of the multi-phase image signal and the application circuit of the CC signal to the column signal line driving circuit 51.
The signal processing circuit uses each single-phase processing unit 3-i provided on each signal line corresponding to the multi-phased digital image data VIDEOd [i] and compensation data using each image data VIDEOd [i]. , Each single-phase processing unit 3-i is configured as a series circuit of a delay circuit 31 and a D / A converter 32, and the compensation data generating unit 4 , A multiplication circuit 42, an addition circuit 43, and a D / A converter 44 as a serial circuit.
[0043]
Then, in each single-phase processing unit 3-i, each transferred image data VIDEOd [i] is delayed by a delay circuit 31 synchronized with a clock signal CLK, and converted into an analog signal by a D / A converter 32. The signal is output to the column signal line drive circuit 51.
On the other hand, in the compensation data creation unit 4, the addition circuit 41 adds all the image data VIDEOd [i] for n phases, the multiplication circuit 42 multiplies the addition data by a constant coefficient Ac, and further adds A digital signal CCd for providing an original CC signal is added to the multiplied value Vq obtained by the multiplying circuit 42 by the circuit 43, and the added data is converted into an analog signal CCq by the D / A converter 44.
Further, the converted analog signal CCq is applied to the substrate 71 in the liquid crystal display device of FIG. 5, and becomes a common voltage for the substrate-side terminal 71a of the auxiliary capacitor 62 related to each display pixel PX.
[0044]
Here, the multiplication coefficient Ac of the multiplication circuit 42 corresponds to the value described in the first embodiment.
That is, the value obtained by multiplying the result of adding all the image data VIDEOd [i] for the n phases by the adding circuit 41 by the coefficient Ac is the image signal VIDEO [i] in the liquid crystal display device of FIG. It is set so as to correspond to the voltage variation Vq of the substrate-side terminal 71a when data is written to the auxiliary capacitance 62 of the display pixel PX.
[0045]
The reason that the delay circuit 31 is provided in each single-phase processing unit 3-i is that it takes time for the above-described arithmetic processing in the compensation data creation unit 4, and the D / A converter 32 converts the analog signal into an analog signal. The compensation data creation unit 4 creates the converted image signal VIDEO [i] based on the timing at which the column signal line drive circuit 51 writes the converted image signal VIDEO [i] to the storage capacitor 62 of each display pixel PX and the image signal VIDEOd [i] at the same time. The timing at which the analog signal CCq is output is synchronized.
[0046]
Therefore, according to this embodiment, when the image signal VIDEO [i] is written to the auxiliary capacitance 62 of each display pixel PX in a unit of a pair, the voltage of the substrate-side terminal 71a of the auxiliary capacitance 62 related to each display pixel PX is reduced. The voltage is set to the voltage obtained by adding the above-mentioned voltage fluctuation Vq to the original CC signal (the voltage of the analog signal CCq), and an image display can be executed in which the voltage fluctuation due to the crosstalk of the image signal is compensated.
That is, as in the case of the first embodiment, in the liquid crystal display device of FIG. 5, it is possible to perform display using the image signal VIDEO [i] in which the amount of crosstalk is canceled for each set.
Further, it is similar to the first embodiment that it is not necessary to form a complicated circuit for applying a CC signal on the substrate 71.
[0047]
Further, the digital signal of the multiplication coefficient Ac input to the multiplication circuit 42 can be constituted by a constant voltage circuit capable of variably setting an output voltage and an A / D converter, similarly to the first embodiment. Can be realized with the same circuit configuration.
[0048]
In each of the embodiments described above, the signal processing circuit for the multi-phase digital image data VIDEOd [i] has been described. However, the present invention can be configured as a signal processing circuit for an analog image signal.
In that case, the D / A converters 13, 32, and 44 are not necessary, and the other circuits may be replaced with analog circuits having similar functions.
[0049]
【The invention's effect】
The liquid crystal display device of the present invention has the following effects by having the above configuration.
According to the first aspect of the present invention, in a liquid crystal display device that performs display by using a multi-phase image signal, a problem that image signals written to display pixels in pairs are cross-talked through a substrate-side terminal of an auxiliary capacitor is eliminated. This problem can be solved by providing a signal processing circuit for compensating for a voltage variation due to crosstalk in an input path of an image signal to a column signal line driving circuit, thereby realizing high image quality.
Further, it is not necessary to form a circuit for applying a predetermined voltage to the substrate-side terminal of the auxiliary capacitor with a complicated configuration on the substrate as in Japanese Patent Application No. 2002-199355 of the prior art created for the same purpose. Since the substrate or the conductor layer formed on the substrate can be used as a common application circuit, the semiconductor process for manufacturing the liquid crystal display device can be simplified.
According to the second aspect of the invention, the invention of the first aspect performs compensation on a group basis for a polyphased image signal, but enables compensation on an image signal on a pixel basis, and performs finer adjustment. Further, high-quality image display is realized.
According to a third aspect of the present invention, a signal processing circuit for compensating for a voltage variation due to crosstalk of an image signal is provided in a signal path for applying a predetermined voltage to a substrate-side terminal of an auxiliary capacitor in each display pixel. The same effect as that of the invention is realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a signal processing circuit according to a first embodiment of a liquid crystal display device of the present invention.
FIG. 2 is a graph for explaining the concept of a multiplication coefficient of a multiplication circuit.
FIG. 3 is a circuit diagram of a signal processing circuit according to a second embodiment.
FIG. 4 is a circuit diagram of a signal processing circuit according to a third embodiment.
FIG. 5 is a circuit diagram of a conventional liquid crystal display device that performs image display using a multi-phase image signal.
FIG. 6 is a timing chart mainly showing operation timings of the row signal line driving circuit.
FIG. 7 is a timing chart mainly showing operation timings of the column signal line driving circuit.
FIG. 8 is a circuit diagram of a liquid crystal display device (Japanese Patent Application No. 2002-199355) according to the related art for the purpose of suppressing crosstalk of an image signal.
FIG. 9 is a sectional structural view of a display pixel.
[Explanation of symbols]
1-i, 1a-i, 3-i: (where i = 1 to n): Single-phase processing unit, 2, 4: Compensation data creation unit, 11, 31: Delay circuit, 12, 12a, 41, 43 ... Addition circuits, 13, 32, 44 D / A converters, 21 addition circuits, 14, 22, 42, multiplication circuits, 51 column signal line drive circuits, 52 row signal line drive circuits, 61 transistors ( Switching field-effect transistor), 62... Auxiliary capacitance (capacitor for holding signal voltage), 63... Pixel electrode, 64... Common electrode, 65... Liquid crystal member, 71. ... conductor part, 73 ... dielectric layer, 74 ... transparent substrate, 75 ... insulating layer, 76, 77 ... liquid crystal alignment film, Ac ... multiplication coefficient, CC ... CC signal, CCd ... digital signal giving the original CC signal, CCq ... Analog CC signal after compensation, C K: clock signal, COM: COM signal, D (K) 1 to D (K) n: (where K = 1 to X): column signal line, G1 to Gj: row signal line, HCK: horizontal clock signal, HST: horizontal start signal, VIDEO [i]: (however, i = 1 to n): polyphase analog image signal, VIDEOd [i]: (however, i = 1 to n) ... polyphase Digital image data, VIDEO (K) [i]: (where i = 1 to n): a set of polyphased image signals, VCK: vertical clock signal, VST: vertical start signal, ΔVq: voltage fluctuation amount.

Claims

A number of display pixels including a switching transistor, an auxiliary capacitor, and a pixel electrode, having one terminal of the auxiliary capacitor connected to the output terminal of the switching transistor and the pixel electrode, and the other terminal configured on the substrate side. A first substrate disposed in a matrix, and a transparent substrate disposed opposite to the first substrate, wherein a common electrode is provided in a region corresponding to a display pixel arrangement region on the first substrate. Two substrates, a liquid crystal member sealed and held between the first substrate and the second substrate, and n column signal lines connected to input terminals of switching transistors of display pixels aligned in the column direction. (N is a natural number of 2 or more) is grouped as a set, and an operation of sampling and outputting an input image signal polyphased into n phases to the column signal lines of each set in parallel is sequentially performed in units of the set. A row selection signal is sequentially output to the signal line drive circuit and each row signal line connected to the on / off control terminal of the switching transistor of each display pixel aligned in the row direction, and the switching transistor of the display pixel is turned on in row units. A row scanning line driving circuit for turning on / off the column signal line driving circuit while applying a predetermined voltage to each of the substrate-side terminals of the respective auxiliary capacitors in the first substrate and the common electrode of the second substrate. In a liquid crystal display device that performs image display by the row scanning line drive circuit operating in synchronization,
a first addition circuit that adds each signal at the same time point of the image signal that has been polyphased into n phases;
A first multiplication circuit for multiplying the addition result obtained by the first addition circuit by a constant coefficient value;
The multiplication result of the first multiplication circuit and the image signal at the time when the first addition circuit executes the addition processing are provided independently in each input circuit of the n-phase image signal to the column signal line driving circuit. And a second addition circuit for adding the signal to the column signal line drive circuit,
The multiplication coefficient value in the first multiplying circuit is set to a voltage variation generated at a substrate-side terminal of the auxiliary capacitor when image signals for n phases are accumulated in the auxiliary capacitor in sets by the column signal line driving circuit. A liquid crystal display device, wherein the value is set as a value for compensating for the minute.

A number of display pixels including a switching transistor, an auxiliary capacitor, and a pixel electrode, having one terminal of the auxiliary capacitor connected to the output terminal of the switching transistor and the pixel electrode, and the other terminal configured on the substrate side. A first substrate disposed in a matrix, and a transparent substrate disposed opposite to the first substrate, wherein a common electrode is provided in a region corresponding to a display pixel arrangement region on the first substrate. Two substrates, a liquid crystal member sealed and held between the first substrate and the second substrate, and n column signal lines connected to input terminals of switching transistors of display pixels aligned in the column direction. (N is a natural number of 2 or more) is grouped as a set, and an operation of sampling and outputting an input image signal polyphased into n phases to the column signal lines of each set in parallel is sequentially performed in units of the set. A row selection signal is sequentially output to the signal line drive circuit and each row signal line connected to the on / off control terminal of the switching transistor of each display pixel aligned in the row direction, and the switching transistor of the display pixel is turned on in row units. A row scanning line driving circuit for turning on / off the column signal line driving circuit while applying a predetermined voltage to each of the substrate-side terminals of the respective auxiliary capacitors in the first substrate and the common electrode of the second substrate. In a liquid crystal display device that performs image display by the row scanning line drive circuit operating in synchronization,
a first addition circuit that adds each signal at the same time point of the image signal that has been polyphased into n phases;
Circuits are provided independently as circuits corresponding to the input circuits of the n-phase image signals for the column signal line drive circuit, and individually set for each of the input circuits with respect to the addition result obtained by the first addition circuit. A second multiplier circuit for multiplying the obtained coefficient value;
The multiplication result of the second multiplication circuit and the image signal at the time when the first addition circuit executes the addition processing are provided independently in each input circuit of the image signal for n phases to the column signal line driving circuit. And a third addition circuit for adding the signal to the column signal line drive circuit,
The input circuit corresponding to the second multiplying circuit, when the multiplication coefficient value of each of the second multiplying circuits is stored in the auxiliary capacitance by the column signal line driving circuit in units of sets of n-phase image signals. A liquid crystal display device which is set as a value for compensating for a voltage variation generated at a substrate-side terminal of each of the storage capacitors in each display pixel in a column direction connected to the liquid crystal display.

A number of display pixels including a switching transistor, an auxiliary capacitor, and a pixel electrode, having one terminal of the auxiliary capacitor connected to the output terminal of the switching transistor and the pixel electrode, and the other terminal configured on the substrate side. A first substrate disposed in a matrix, and a transparent substrate disposed opposite to the first substrate, wherein a common electrode is provided in a region corresponding to a display pixel arrangement region on the first substrate. Two substrates, a liquid crystal member sealed and held between the first substrate and the second substrate, and n column signal lines connected to input terminals of switching transistors of display pixels aligned in the column direction. (N is a natural number of 2 or more) is grouped as a set, and an operation of sampling and outputting an input image signal polyphased into n phases to the column signal lines of each set in parallel is sequentially performed in units of the set. A row selection signal is sequentially output to the signal line drive circuit and each row signal line connected to the on / off control terminal of the switching transistor of each display pixel aligned in the row direction, and the switching transistor of the display pixel is turned on in row units. A row scanning line driving circuit for turning on / off the column signal line driving circuit while applying a predetermined voltage to each of the substrate-side terminals of the respective auxiliary capacitors in the first substrate and the common electrode of the second substrate. In a liquid crystal display device that performs image display by the row scanning line drive circuit operating in synchronization,
a first addition circuit that adds each signal at the same time point of the image signal that has been polyphased into n phases;
A first multiplication circuit for multiplying the addition result obtained by the first addition circuit by a constant coefficient value;
An output circuit that is provided between a substrate-side circuit for applying a voltage to a substrate-side terminal of each auxiliary capacitor in the first substrate and an external voltage supply circuit that outputs an original predetermined voltage; A fourth addition circuit that adds a result of multiplication by the first multiplication circuit to a voltage and outputs the result to the substrate-side circuit;
The multiplication coefficient value in the first multiplying circuit is set to a voltage variation generated at a substrate-side terminal of the auxiliary capacitor when image signals for n phases are accumulated in the auxiliary capacitor in sets by the column signal line driving circuit. A liquid crystal display device, wherein the value is set as a value for compensating for the minute.