JPH0934412A - Liquid crystal display - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to drive by a different driving method according to a display object without providing a processing circuit for adjusting a phase of a video signal for each color externally. [Configuration] A control signal generation circuit 22 in the horizontal drive circuit 16 sequentially samples video signals for each color of G, R, and B for configuring a color image at different timings and sequentially supplies them to a signal line corresponding to each color. The high resolution mode 1 and the mode 2 in which the video signals for each color are simultaneously sampled and simultaneously supplied to the signal line corresponding to each color are selected. In mode 1, picture element switches 32G, 32R, 3
2B samples the video signals for each color in different phases and supplies them to the signal lines S _1G , S _1R and S _1B sequentially. In mode 2, the picture element switches 32G, 32R and 32B sample the video signals of the respective colors in the same phase and output signal lines S _1G , S _1R ,
Supply to S _1B at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device which can be driven by different driving methods depending on a display object.

[0002]

2. Description of the Related Art Liquid crystal display devices are used in various applications such as displays for OA (office automation) devices such as computers and word processors, and displays for AV (audio-visual) devices such as video cameras. Conventionally, when a liquid crystal display device is caused to perform color display for OA, a color is designated for each dot, so that it is necessary to improve reproducibility of each color and to coordinate the coordinates of each color. The liquid crystal display device has a circuit configuration in which input video signals for each color of R (red), G (green), and B (blue) are simultaneously sampled as a set of 3 dots.

On the other hand, when the liquid crystal display device having the above-described configuration is used to perform color display for AV or monochrome display without using color filters, the video signal for each color continuously changes, unlike the case for OA. Therefore, in order to improve linear reproducibility and apparent resolution, simultaneous sampling of video signals for each color as described above is not preferable. Therefore, conventionally, in order to improve linear reproducibility and apparent resolution, the phase of the video signal for each color is adjusted, that is, the phase is changed in order to correct the continuity of R, G, B and dot misalignment. The processing circuit was provided outside.

[0004]

In the case of changing the phase of the video signal according to the display object in this way, a dedicated display device is developed according to the display object, or a common liquid crystal display device is used. Processing circuits must be added selectively. However, there is a problem that developing a dedicated display device increases cost. In addition, when a processing circuit is selectively added to the common liquid crystal display device, it is difficult to adjust the circuit operation so that the circuit operates properly with the processing circuit added. .

The present invention has been made in view of the above problems, and an object thereof is to drive by a different driving method according to a display object without providing an external processing circuit for adjusting the phase of a video signal for each color. An object of the present invention is to provide a liquid crystal display device that can be manufactured.

[0006]

A liquid crystal display device according to the present invention comprises a plurality of liquid crystal layers and a plurality of liquid crystal layers arranged in orthogonal to each other for applying a voltage according to a video signal to the liquid crystal layer in each picture element. In order to apply a voltage according to a video signal to the liquid crystal layer in each pixel corresponding to the scanning electrode selected by the scanning electrode and the plurality of signal electrodes, the vertical driving circuit that selects the scanning electrode, and the scanning electrode A horizontal driving circuit for selecting a signal electrode and supplying a video signal, wherein the video signal for each color for forming a color image is sequentially sampled at different timings and sequentially supplied to the signal electrode corresponding to each color. 1 mode and a horizontal drive circuit capable of selecting one of a second mode for simultaneously sampling video signals for each color and simultaneously supplying the signal electrodes corresponding to each color. Than it is.

[0007]

In the liquid crystal display device of the present invention, the horizontal drive circuit is
When the first mode is selected, the video signal for each color is sequentially sampled at different timings and sequentially supplied to the signal electrodes corresponding to each color, and when the second mode is selected, the video for each color is selected. The signals are simultaneously sampled and simultaneously supplied to the signal electrodes corresponding to the respective colors. Of the plurality of picture elements corresponding to the scanning electrodes selected by the vertical drive circuit, the liquid crystal layer in the picture element corresponding to the signal electrode to which the video signal for each color is supplied has a voltage corresponding to the video signal for each color. Is applied.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a liquid crystal display device according to the first embodiment of the present invention. Although not shown, the liquid crystal display device 10 according to the present embodiment includes a glass substrate provided with a transparent common electrode, a glass substrate provided with display electrodes, TFTs (thin film transistors), scanning lines and signal lines described later. A liquid crystal layer formed by enclosing a liquid crystal between these two glass substrates is provided. In the case of a liquid crystal display device for color display, R, G, and B color filters are further provided corresponding to each picture element on a glass substrate provided with a common electrode. In FIG. 1, reference numeral 11 represents a liquid crystal layer corresponding to each picture element. A common common electrode is in contact with one surface of the liquid crystal layer 11, and the counter voltage input terminal 12 is connected to the common electrode. Display electrodes are in contact with the other surface of the liquid crystal layer 11 for each picture element.
The drain of the TFT 13 provided for each picture element is connected to the display electrode. The liquid crystal display device 10 further includes a capacitor 14 provided for each pixel, one end of the capacitor 14 is connected to the drain of each TFT 13, and the other end is connected to a common electrode.

In the liquid crystal display device 10, further, in order to apply a voltage according to a video signal to the liquid crystal layer 11 in an arbitrary picture element, scanning lines G ₁ as a plurality of scanning electrodes arranged so as to be orthogonal to each other. To G _n and signal lines S _1G , S _1R , S _1B , ... S _mB as a plurality of signal electrodes. Each scanning line G _{1 to} G _n is each T in one row of picture elements.
It is connected to the gate of FT13. Each signal line S _1G ~ S
_{The mBs} are connected to the sources of the TFTs 13 in each row of picture elements. In this embodiment, one row of picture elements connected to one scanning line is a G picture element, an R picture element, or a B picture element.
It is repeatedly arranged in the order of picture elements. Therefore, the signal lines S _1G , S _1R , and S _1B are signal lines corresponding to consecutive G picture elements, R picture elements, and B picture elements. Liquid crystal display device,
A vertical drive circuit 15 connected to each scanning line G _{1 to} G _n ,
And a horizontal drive circuit 16 connected to each of the signal lines S _{1G to} S _mB .

Here, an outline of the operation of the liquid crystal display device 10 shown in FIG. 1 will be described. In the liquid crystal display device 10, the vertical drive circuit 15 sequentially applies scan pulses to the scan lines G _{1 to} G _n , and the TFTs 13 in one row of picture elements connected to the scan lines to which the scan pulse is applied. Turns on. While the scan pulse is being applied to one scan line, the horizontal drive circuit 16 sequentially applies the video signal to the signal lines S _{1G to} S _mB , and the video signal is passed through the TFT 13 in the ON state. Capacitor 1
4, the capacitor 14 is charged with electric charges according to the video signal. This charge will apply a voltage corresponding to the video signal to the liquid crystal layer 11 of each picture element connected to the scanning line until the scanning line is selected next time.

FIG. 2 is a circuit diagram showing the configuration of the horizontal drive circuit 16 shown in FIG. The horizontal driving circuit 16 is connected to a pair of signal lines S _1G , S _1R , S _1B ; S _2G , S _2R , S _2B ; It has been a shift register unit 21 _1, 21 _2, ..., and a control signal generating circuit 22. The horizontal drive circuit 16 further includes
Horizontal start signal HST and mode signal mod respectively
e, and input terminals 23 to 28 for inputting the respective video signals of the horizontal clocks HCK, G, R and B. The control signal generation circuit 22 has a horizontal start signal HS.
It has an input end for inputting T, a mode signal mode, and a horizontal clock HCK, and an output end for outputting a clock signal CLK and enable signals EN ₁ , EN ₂ , and EN ₃ , respectively. The horizontal start signal HST,
The horizontal clock HCK and the mode signal mode are generated by an external controller.

The shift register section 21 ₁ includes a shift element 3
1 and three picture element switches 32G, 32R, 32B each having one end connected to the signal lines S _1G , S _1R , S _1B of the G picture element, the R picture element, and the B picture element, and three picture element switches And gate 3
3G, 33R, 33B. Shift element 31
Are the horizontal start signal HST and the clock signal C, respectively.
Input terminal for inputting LK and output signal OU
The output terminal for outputting T and SH _out1 receives the horizontal start signal HST, shifts by 1 clock with the clock signal CLK, and sends it as the output signal OUT to the shift register section 21 ₂ of the next stage. The clock signal CLK is shifted by a half cycle and output as the output signal SH _out1 . Output signal SH _out1 is AND gate 3
It is adapted to be input to one of the input terminals of 3G, 33R and 33B. AND gate 33G, 33R, 33B
To the other input terminal of the control signal generating circuit 22.
Enable signals EN ₁ , EN ₂ , EN ₃ output from
Is entered. Picture element switch 32G,
The other ends of 32R and 32B are connected to input terminals 26, 27 and 28 for inputting G, B and R video signals, respectively. AND gate 33G, 33R, 33B
Output terminals of the pixel switches 32G, 32R,
It is connected to the control terminal of 32B.

The shift register sections 21 ₂ , ... Also have the same structure as the shift register section 21 _2. However, in these shift register sections 21 ₂ , ..., The shift element 31 does not use the horizontal start signal HST but shifts in the preceding stage. The difference is that the output signal OUT of the shift element 31 in the register section is input.

Next, the operation of the horizontal drive circuit 16 shown in FIG. 2 will be described with reference to FIGS. 3 and 4. The control signal generation circuit 22 sequentially samples video signals for each color of G, R, and B for forming a color image at different timings according to the mode signal mode input from the input terminal 24 and outputs signals corresponding to the respective colors. A high resolution mode 1 for sequentially supplying the lines and a mode 2 for simultaneously sampling the video signals of the respective colors and simultaneously supplying the signal lines corresponding to the respective colors are selected. Mode 1 is suitable for monochrome display or AV color display, and mode 2 is suitable for OA color display, for example.

FIG. 3 is a timing chart showing the operation of the horizontal drive circuit 16 when the mode 1 is selected. The control signal generation circuit 22 receives the input horizontal start signal HST (see FIG. 3).
(A)) is used as a reset signal RES for phase adjustment of the internal control signal, and the horizontal clock HCK (see FIG. 3) is used.
Using (b)) as a basic clock, the clock signal CLK and the enable signal E shown in FIGS.
Create a _{N 1, EN 2, EN 3} , and outputs. Here, the clock signal CLK is a signal having a cycle three times that of the horizontal clock HCK. In addition, enable signals EN ₁ , EN ₂ , E
N ₃ is a signal having a high level period of 2 clocks of the horizontal clock HCK and a low level period of 4 clocks of the horizontal clock HCK, and a signal whose phase is shifted by 2 clocks of the horizontal clock HCK. In the shift register unit 21 ₁ , the shift element 31 has the horizontal start signal HS.
T with a letter as an output signal OUT by one clock shift clock signal CLK to the next stage of the shift register unit 21 _2, the clock signal CLK the horizontal start signal HST
Output signal SH _out1 shifted by half a cycle of (Fig. 3 (g))
Is output. The output signal SH _out1 is input to one input end of each of the AND gates 33G, 33R and 33B, and the enable signals EN ₁ , EN ₂ and EN ₃ are input to the other input end of each of the AND gates 33G, 33R and 33B. The output signals G _out1 , R _out1 , and B _out1 of 33B are as shown in FIGS. 3 (h) to (j), and the signal G _out1 , R _out1 , and B _out1 causes the picture element switches 32G, 32R, and 32B to change. Controlled. During the period when the signals G _out1 , R _out1 , and B _out1 are high level,
Each picture element switch 32G, 32R, 32B is turned on,
A video signal for each color is sampled and passed through each of the picture element switches 32G, 32R, 32B and signal lines S _1G , S _1R , S.
Sequentially supplied to _1B . The same operation is performed by the clock signal CL
Shift register unit 21 ₂ at a timing delayed by one clock minute K, ... but are sequentially performed.

As described above, in the mode 1, continuous G,
In each of the B and R picture elements, the video signal for each color is sampled in a phase-shifted manner, so that each picture element outputs information at a different position in the original image. Although the number is 31, the resolution of the liquid crystal display device 10 itself is tripled. It is obvious that the resolution is tripled in the case of monochrome display, but also in the case of color display, each of the G, B, and R picture elements outputs information of different positions in the original image. The linear reproducibility is improved, and the apparent resolution is tripled.

FIG. 4 is a timing chart showing the operation of the horizontal drive circuit 16 when the mode 2 is selected. in this case,
The external controller uses the horizontal clock HCK (see FIG.
As (b)), it is assumed that a clock having a cycle three times as long as that in the mode 1 is output. Control signal generation circuit 22
Is the horizontal start signal HST as in mode 1
(FIG. 4 (a)) is used as a reset signal RES for phase adjustment of the internal control signal to generate a clock signal CLK (FIG. 4 (b)) that is the same as the horizontal clock HCK, and enable signals EN ₁ and EN ₂ are generated. , EN ₃ is always high level. The external controller may output the same horizontal clock HCK as when selecting mode 1, and the control signal creating circuit 22 may create the clock signal CLK in the same manner as when selecting mode 1. The shift register unit 21 ₁ performs the same operation as when mode 1 is selected, and the output signal SH _out1 of the shift element 31 becomes as shown in FIG. 4 (c). When mode 2 is selected, enable signals EN ₁ , EN ₂ , EN _3
Is always high level, the picture element switches 32G, 32R and 32B are controlled by the signal SH _out1 itself. Therefore, the AND gates 33G, 33R, 3
The output signals G _out1 , R _out1 , and B _out1 of 3B have the same timing as shown in FIG. 4D, the video signals for each color are sampled in the same phase, and each picture element switch 32
The signals are simultaneously supplied to the signal lines S _1G , S _1R and S _1B via G, 32R and 32B. The same operation is sequentially performed in the shift register units 21 ₂ , ... At a timing delayed by one clock by the clock signal CLK.

As described above, according to the liquid crystal display device 10 of this embodiment, the display target (AV) can be displayed without externally providing a processing circuit for adjusting the phase of the video signal for each color.
(Color display for monochromatic display, color display for office automation, etc.). Also,
The configuration of the external controller can be the same regardless of the display target. Further, the liquid crystal display device 10 itself can increase the resolution. In addition, the horizontal drive circuit 1
The liquid crystal display device 6 must have various functions and configurations depending on the specifications, purpose, cost, development period, requirements of peripheral circuits, etc. of the liquid crystal display device 10, but the liquid crystal display device 1 according to the present embodiment.
According to 0, it becomes possible to meet more demands as compared with the conventional case.

FIG. 5 is a circuit diagram showing the configuration of the horizontal drive circuit 16 in the liquid crystal display device according to the second embodiment of the present invention. The horizontal drive circuit 16 in this embodiment includes signal lines S _1G , S _1R , S _1B ; S _2G , S _2R , S _2B for a pair of G picture element, R picture element, and B picture element, which are continuous, respectively. , Shift control sections 41 ₁ , 41 ₂ , ..., Control signal generating circuit 42, and input terminals 23 to 28 similar to those of the first embodiment.
And The control signal generation circuit 42 has an input end for inputting a horizontal start signal HST, a mode signal mode, and a horizontal clock HCK, and an output end for outputting three-phase clock signals CLK ₁ , CLK ₂ , CLK ₃ , respectively. Have

The shift register section 41 ₁ has three shift elements 43G, 43R and 43B and signal lines S _1G and S _1R for the G picture element, the R picture element and the B picture element each having one set at one end. ，
Three picture element switches 32G, 32R connected to S _1B ,
32B and. The shift element 43G receives the horizontal start signal HST and the clock signal CLK _1, and receives the horizontal start signal HST at the falling edge of the clock signal CLK _1.
Is taken in, and the output signal SH _out changes at the rise of the clock signal CLK ₁ . Similarly, the shift element 43R receives the horizontal start signal HST and the clock signal CLK ₂ , receives the horizontal start signal HST at the falling edge of the clock signal CLK ₂ , and outputs the clock signal C.
The output signal SH _out changes at the rising edge of LK ₂ , the shift element 43B receives the horizontal start signal HST and the clock signal CLK ₃ , the horizontal start signal HST is taken in at the falling edge of the clock signal CLK ₃ , and the clock signal CL
The output signal SH _out changes at the rise of K ₃ . The output signals SH _out of the shift elements 43G, 43R, 43B are respectively output to the shift register section 41 _{2 of the} next stage.
To be sent to Picture element switch 32G, 3
The other ends of 2R and 32B are connected to input terminals 26, 27 and 28 for inputting G, B and R video signals, respectively. The output terminals of the shift elements 43G, 43R, 43B are respectively connected to the picture element switches 32G, 32R, 32.
It is connected to the B control terminal.

The shift register unit 41 _2, ... is also the same structure as the shift register unit 41 _2, the shift register unit 41 _2, ... in the shift element 43G, 43R, 4
3B is a shift element 43G, 43R, 43B in the previous shift register section instead of the horizontal start signal HST.
The difference is that the output signal SH _{out of} is input.

Next, the operation of the horizontal drive circuit 16 shown in FIG. 5 will be described with reference to FIGS. 6 and 7.

FIG. 6 shows horizontal drive when mode 1 is selected.
FIG. 6 is a timing chart showing the operation of the circuit 16. Control signal
The generating circuit 42 receives the input horizontal start signal HST (see FIG. 6).
(A)) is reset for phase adjustment of the internal control signal
It is used as the signal RES and the horizontal clock HCK (see FIG.
6B to 6E with (b)) as a basic clock.
Three-phase clock signal CLK shown₁, CLK_Two, CLK_Three
Create and output. Here, the clock signal CLK₁,
CLK_Two, CLK_ThreeAre the horizontal clocks HCK
It is a signal with a period three times longer, and 2 times the horizontal clock HCK.
It is a signal whose phase is shifted by clocks. Shift register
Part 41₁Of the shift elements 43G, 43R, 43B of
Signal SH_outAre the picture element switches 32G and 32, respectively.
Signal G for controlling R and 32B_out1, R_out1, B_out1(Figure
6 (f) to (h)). Signal G _out1, R_out1, B
_out1Is the high level period, each pixel switch 32G, 32
R and 32B are turned on and the video signal for each color is sampled.
It is ringed and each picture element switch 32G, 32R, 32B
Via signal line S_1G, S_1R, S_1BAre sequentially supplied. similar
Operation is clock signal CLK₁, CLK_Two, CLK_Threeso
The shift register block is delayed by one clock
41_Two,… But it is done sequentially. As an example, in FIG.
Shift register unit 41_TwoOutput signal of the shift element 43G of
G_out2Is shown.

As described above, in the mode 1, continuous G,
In each of the B and R picture elements, the video signal for each color is sampled in a phase-shifted manner, so that the resolution of the liquid crystal display device 10 itself is tripled, as in the first embodiment.

FIG. 7 is a timing chart showing the operation of the horizontal drive circuit 16 when the mode 2 is selected. in this case,
The external controller uses the horizontal clock HCK (see FIG.
As (b)), it is assumed that a clock having a cycle three times as long as that in the mode 1 is output. Control signal generation circuit 42
Is the horizontal start signal HST as in mode 1
(FIG. 7A) is used as a reset signal RES for phase adjustment of the internal control signal, and the same clock signals CLK ₁ , CLK ₂ , and CLK ₃ as the horizontal clock HCK (FIG. 7A) are used.
(C)) is created. In the shift register unit 41 ₁ , since the shift elements 43G, 43R, 43B operate in synchronization, the output signal S of each shift element 43G, 43R, 43B.
All of H _out are the same signal in phase with each other, and signals G _out1 and R for controlling the respective picture element switches 32G, 32R and 32B.
_out1 and B _out1 have the same signal (FIG. 7 (d)). Therefore, the video signals for each color are sampled in the same phase and are simultaneously supplied to the signal lines S _1G , S _1R and S _1B via the picture element switches 32G, 32R and 32B. The same operation is performed by the shift register unit 41 at a timing delayed by one clock for each of the clock signals CLK ₁ , CLK ₂ , and CLK _3.
2 , ... are also performed sequentially.

According to this embodiment, the sampling time of the video signal for each color is longer than that in the first embodiment, so that a smooth display image can be obtained in the case of AV color display. Other configurations, operations and effects of this embodiment are similar to those of the first embodiment.

The present invention is not limited to the above-mentioned embodiments. For example, when the AV color display screen is output to a part of the OA color display screen, the mode is changed depending on the part of one screen. The mode 1 and the mode 2 may be changed.

[0029]

As described above, according to the liquid crystal display device of the present invention, in the horizontal drive circuit, video signals for each color for forming a color image are sequentially sampled at different timings, and signals corresponding to the respective colors are sampled. Since it is possible to select the first mode for sequentially supplying the electrodes and the second mode for simultaneously sampling the video signals for each color and simultaneously supplying the signal electrodes corresponding to each color, the phase of the video signal for each color is selected. It is possible to drive with a different driving method according to the display object without providing a processing circuit for adjusting the external, and the configuration of the external controller can be the same regardless of the display object. There is an effect that the resolution can be increased by the display device itself.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a horizontal drive circuit in FIG.

3 is a timing chart showing an operation of the horizontal drive circuit shown in FIG. 2 when mode 1 is selected.

FIG. 4 is a timing diagram showing an operation of the horizontal drive circuit shown in FIG. 2 when mode 2 is selected.

FIG. 5 is a circuit diagram showing a configuration of a horizontal drive circuit in a liquid crystal display device according to a second embodiment of the present invention.

6 is a timing chart showing an operation of the horizontal drive circuit shown in FIG. 5 when mode 1 is selected.

7 is a timing chart showing an operation of the horizontal drive circuit shown in FIG. 5 when mode 2 is selected.

[Explanation of symbols]

10 liquid crystal display device 11 liquid crystal layer 13 TFT 14 capacitor 15 vertical drive circuit 16 horizontal drive circuit 21 ₁ , 21 ₂ , ... Shift register unit 22 control signal generation circuit 31 shift element 32G, 32R, 32B pixel switch 33G, 33R, 33B And gate

Claims (1)

[Claims] 1. A liquid crystal layer, a plurality of scanning electrodes and a plurality of signal electrodes arranged so as to be orthogonal to each other for applying a voltage according to a video signal to the liquid crystal layer in each picture element, and a scanning electrode. In order to apply a voltage according to a video signal to the liquid crystal layer in each pixel corresponding to the selected vertical drive circuit and the scan electrode selected by this vertical drive circuit, the signal electrode is selected to supply the video signal. A horizontal drive circuit, in which a video signal for each color for forming a color image is sequentially sampled at different timings and sequentially supplied to a signal electrode corresponding to each color, and a video signal for each color is simultaneously sampled. And a horizontal driving circuit capable of selecting one of the second modes for simultaneously supplying to the signal electrodes corresponding to each color.