JP2004200420A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an electrode on a semiconductor substrate from being damaged in a manufacturing process, related to a semiconductor device, along with its manufacturing method where a plurality of metal films are laminated on the semiconductor substrate in which the electrode and an insulating film where an opening part is formed at a position facing the electrode are formed. <P>SOLUTION: The semiconductor device comprises: a semiconductor substrate 10 where an electrode 12 is formed; a passivation film 13 that is formed on the semiconductor substrate 10 and in which a passivation opening 14 is formed at the position facing the electrode 10; and a plurality of laminated metal films 15 and 16. At least one metal film 16 between the plurality of metal films 15 and 16 acts as a mask to remove (etch) the metal film 15 which is closer to the semiconductor substrate 10 than the metal film 16. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, a semiconductor device in which a plurality of metal films are stacked on a semiconductor substrate on which an electrode and an insulating film having an opening formed at a position facing the electrode are formed. And a manufacturing method thereof.
[0002]
It is expected that higher density / higher speed / miniaturization of semiconductor devices will be accelerated / promoted in the future. Semiconductor devices have been increased in speed, integration, and performance. Various mounting techniques are available for mounting the bare chip semiconductor device (semiconductor chip) on an interposer or a mounting substrate (hereinafter referred to as a mounting substrate or the like). A method has been developed. Specifically, examples of the mounting technique include a wire bonding method, a TAB (tape automated bonding) method, and a flip chip method.
[0003]
The wire bonding method is a method in which a semiconductor chip is disposed face up on a mounting substrate, and an electrode of the semiconductor device and a pad on the mounting substrate or the like are connected by an aluminum wire or a gold wire. The TAB method is a method in which a copper wiring is formed on a heat-resistant insulating film such as polyimide to form a TAB tape, and the electrodes of the semiconductor device and the copper leads of the TAB tape are connected via bumps. In the flip chip method, metal bumps are formed on the electrodes on the semiconductor device by vacuum deposition / sputtering / molten metal dip / plating, etc., and the bumps and pads on the surface of the mounting substrate are aligned. It is a method of joining.
[0004]
In each of these methods, the method for mounting (connecting) a semiconductor device to a mounting substrate or the like is changed from a wire bonding method for face-up mounting to a TAB method using bumps for face-down mounting or a flip-chip mounting method. Yes. This is because the TAB method or flip chip mounting can achieve higher density and smaller size than the wire bonding method.
[0005]
[Prior art]
As described above, the method for mounting (connecting) a bare chip semiconductor device to a mounting substrate or the like is changed from the wire bonding method of face-up mounting to the TAB method or flip chip mounting method using mounting bumps of face-down. ing. This is because the TAB method or flip chip mounting can achieve higher density and smaller size than the wire bonding method. Therefore, when using the TAB method or the flip chip mounting method, it is necessary to form bumps in the semiconductor device.
[0006]
Hereinafter, a conventional example of a method for manufacturing a semiconductor device including a step of forming bumps on the semiconductor device will be described. In the following description, an example will be described in which bumps are used as solder balls and the solder balls are manufactured by electrolytic plating. Here, the reason for using solder is that a highly reliable connection can be achieved. The reason why electrolytic plating is used as a bump forming method is that according to electrolytic plating, solder balls can be formed at a uniform height, low cost, and high yield.
[0007]
1 and 2 are views for explaining a method of manufacturing a semiconductor device as a first conventional example. 1 and 2 show only the solder ball manufacturing method in the semiconductor device manufacturing method.
[0008]
FIG. 1A shows a state in which a passivation film 103 is formed on a semiconductor substrate 101 having an electrode 102 made of aluminum. A passivation opening 104 is formed at a position facing the electrode 102 of the passivation film 103, so that the electrode 102 is exposed to the outside through the passivation opening 104. Note that the electrode 102 located on the left side in the drawing is an electrode for external connection, and a solder ball 112 is formed later (see FIG. 2G). On the other hand, the electrode 102 located on the right side in the figure is a test electrode, and the probe 115 is connected during the test (see FIG. 2G).
[0009]
The probe 115 is connected to the electrode 102 when an electrical test of the semiconductor substrate 101 is performed. Although the probe 115 can be brought into direct contact with the solder ball 112, this method damages the solder ball 112. For this reason, in recent years, many methods have been adopted in which the electrode 102 for contacting the probe 115 is formed separately from the electrode 102 on which the solder ball 112 is formed, and the solder ball 112 is prevented from being damaged during the test. .
[0010]
As shown in FIG. 1B, a first metal film 105 and a second metal film 106 are stacked over the entire upper surface of the semiconductor substrate 101 by sputtering. Subsequently, a photoresist 107 is applied onto the second metal film 106 by a spinner, and then an exposure / development / curing process is performed to form a photoresist on the left electrode 102 where the solder balls 112 are formed. An opening 108 is formed (see FIG. 1C).
[0011]
Subsequently, the first metal film 105 and the second metal film 106 are used as a power supply film for electrolytic plating, and Ni plating film 109 is formed by performing electrolytic Ni plating, and further, electric field solder is formed thereon. A plating 110 is formed. FIG. 1D shows a state in which the Ni plating film 109 and the electric field solder plating 110 are formed. At this time, since the electrode 102 located on the right side is covered with the photoresist 107, the Ni plating film 109 and the electric field solder plating 110 are not formed.
[0012]
Subsequently, as shown in FIG. 1E, the photoresist 107 is removed, and the first metal film 105 and the second metal film 106 are wet-etched using the electric field solder plating 110 as a mask. Thereby, as shown in FIG. 2F, unnecessary portions of the first metal film 105 and the second metal film 106 are removed.
[0013]
Methods for removing the first and second metal films 105 and 106 include dry etching and wet etching. Since dry etching has problems such as an expensive apparatus and a complicated etching process, wet etching is usually used. In addition, since the first and second metal films 105 and 106 are etched using the electric field solder plating 110 as a mask, the manufacturing process is simplified and the material used is compared with a configuration using a resist other than the electric field solder plating 110 as a mask. Can be reduced.
[0014]
When the unnecessary portions of the first and second metal films 105 and 106 are removed as described above, a flux (not shown) is then applied to the upper surface of the semiconductor substrate 101, and this is heated in a nitrogen atmosphere. Solder oxide removal and bump shaping are performed. Thereby, as shown in FIG. 2G, a solder ball 112 is formed on the left electrode 102 of the semiconductor substrate 101.
[0015]
Note that the metal laminated film formed of the first metal film 105, the second metal film 106, and the Ni plating film 109 formed below the solder ball 112 is necessary for bonding and bonding the solder ball 112 and the electrode 102. It is a so-called barrier metal or UBM (Under Bump Metal).
This barrier metal has high conductivity, good adhesion to the electrode 102, good adhesion to the solder ball 112, and no diffusion occurs between the electrode 102 and the solder ball 112. In addition, characteristics such as not obstructing the shaping of the solder ball 112 are required.
[0016]
As described above, a method of forming a barrier metal by etching the first and second metal films 105 and 106 formed under the field solder plating 110 as a mask is disclosed in Patent Document 1, for example. This is a known technique.
[0017]
On the other hand, FIGS. 3 and 4 show a semiconductor device manufacturing method which is a second conventional example. 3 and 4 also show only the solder ball manufacturing method in the semiconductor device manufacturing method. 3 and 4, the same reference numerals are given to the components corresponding to those shown in FIGS. 1 and 2, and the description thereof will be omitted.
[0018]
FIG. 3A shows a state in which a passivation film 103 is formed on a semiconductor substrate 101 having an electrode 102 made of aluminum. A passivation opening 104 having a diameter W1 is formed at a position facing the electrode 102 of the passivation film 103. Unlike the first conventional example, in this conventional example, solder balls 112 are formed on any of the electrodes 102 shown in the figure (see FIG. 4G).
[0019]
As shown in FIG. 3B, the first and second metal films 105 and 106 are stacked on the semiconductor substrate 101, and a photoresist 107 is formed on the second metal film 106 by a spinner. Applied. The photoresist 107 is subjected to an exposure / development / curing process, and a photoresist opening 108 for forming the solder ball 112 is formed (see FIG. 3C). Conventionally, since the diameter W2 of the photoresist opening 108 is determined by the size of the solder ball 112 to be formed, it is set to be smaller than the diameter of the passivation opening 104 formed in the passivation film 103 (W1> W2). ).
[0020]
Subsequently, as shown in FIG. 3D, the Ni plating film 109 and the electric field solder plating 110 are formed by using the first and second metal films 105 and 106 as a power supply film for electrolytic plating. As shown in FIG. 3E, the photoresist 107 is removed.
[0021]
Subsequently, the first metal film 105 and the second metal film 106 are wet-etched using the electric field solder plating 110 as a mask. Accordingly, as shown in FIG. 4F, unnecessary portions of the first metal film 105 and the second metal film 106 are removed.
[0022]
Next, a flux (not shown) is applied to the upper surface of the semiconductor substrate 101, and this is heated in a nitrogen atmosphere to remove solder oxide and perform bump shaping, as shown in FIG. 4 (G). A solder ball 112 is formed on each electrode 102.
[0023]
[Patent Document 1]
Japanese Patent No. 2748530 (second page, FIG. 1)
[0024]
[Problems to be solved by the invention]
Here, attention is paid to the step of wet etching the first metal film 105 and the second metal film 106 using the electric field solder plating 110 shown in FIGS. 2F and 4F as a mask.
[0025]
As in the first conventional example, at the formation position of the electrode 102 where the solder ball 112 is not formed, the first and second metal films 105 and 106 shown in FIG. The etching solution for dissolving the second metal films 105 and 106 also acts on the aluminum electrode 102. For this reason, at the end of the wet etching process, the electrode 102 may be greatly damaged, or all of the electrode 102 may be removed as shown in FIG. 2F (the removed electrode 102A is indicated by a one-dot chain line). Show).
[0026]
When the electrode 102 is damaged in this manner, the connection with the probe 115 may not be performed properly. In addition, when the electrode 102 is completely removed, the portion of the semiconductor substrate 101 facing the passivation opening 104 is directly exposed without being protected by the passivation film 103. For this reason,
There is a possibility that a circuit formed on the semiconductor substrate 101 may be damaged.
[0027]
On the other hand, even when the solder ball 112 is formed on any electrode 102 on the semiconductor substrate 101, the first and second metal films 105 and 106 are wet-etched as shown in FIG. As a result, the portion of the electrode 102 that is not covered by the electric field solder plating 110 is greatly damaged or removed by the etching solution.
[0028]
This is because the diameter W1 of the passivation opening 104 (shown in FIG. 3A) is conventionally larger (W1> W2) than the diameter W2 of the photoresist opening 108 (see FIG. 3C). When the first and second metal films 105 and 106 are removed by wet etching, the etching solution advances from the passivation opening 104 to the electrode 102 due to the difference in diameter (area difference) between the openings 104 and 108, whereby the electrode The part which is not covered with the electric field solder plating 110 of 102 will be damaged or removed.
[0029]
As a means for solving the above-described problems, a resist or a mask is formed on the electrode 102 at the time shown in FIG. It is conceivable to prevent the second metal films 105 and 106 from being etched. Similarly, at the time shown in FIG. 3E, a resist or a mask is formed at a position (see FIG. 4G) corresponding to the difference in diameter between the openings 104 and 108 described above, thereby performing a wet etching process. However, it is conceivable to prevent the first and second metal films 105 and 106 on the electrode 102 from being etched.
[0030]
However, this method requires a difficult process of forming a resist or a mask at a predetermined position as a pre-process for performing the wet etching process (because bumps exist, resist coating and exposure processing are difficult), and the manufacturing process The manufacturing cost increases due to the complexity and the use of more materials.
[0031]
The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of preventing an electrode on a semiconductor substrate from being damaged during the manufacturing process and a manufacturing method thereof.
[0032]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention is characterized by the following measures.
[0033]
The invention described in claim 1
A semiconductor substrate on which electrodes are formed;
An insulating film formed on the semiconductor substrate and having an opening formed at a position facing the electrode;
A plurality of stacked metal films;
In a semiconductor device having
Among the plurality of metal films, a metal film closer to the semiconductor substrate than the one metal film is patterned using at least one metal film as a mask.
[0034]
According to the above invention, since one metal film functioning as a power supply film for electroplating can be left as it is in the manufacturing process, the manufacturing process is compared with a method of forming a mask with a member different from a plurality of metal films. Can be simplified.
[0035]
The invention according to claim 2
The semiconductor device according to claim 1,
The plurality of metal films are formed on the openings so as to be connected to the electrodes.
[0036]
According to the said invention, a some metal film can be used as a terminal for the external connection of an electrode. Further, when a solder ball or the like is used as the external connection terminal, a plurality of metal films are interposed between the external connection terminal such as the solder ball and the electrode, and thus can function as a barrier metal.
[0037]
The invention according to claim 3
The semiconductor device according to claim 1 or 2,
The area of the one metal film is larger than the area of the opening formed in the insulating film.
[0038]
According to the above invention, since the area of the one metal film is larger than the area of the opening formed at the position facing the electrode, the opening is formed by the one metal film and the metal film formed below the metal film. It will be covered. Therefore, since the electrode is not directly exposed from the opening, the electrode can be reliably protected.
[0039]
The invention according to claim 4
The semiconductor device according to claim 1 or 2,
Among the plurality of metal films, one or more metal films are formed on the insulating film.
[0040]
According to the above invention, a plurality of metal films can be formed at arbitrary positions on the insulating film. Since the insulating film is widely formed on the semiconductor substrate, the formation position of the metal film can be selected with flexibility and can be used for various applications.
[0041]
Specifically, the metal film according to claim 4 can be used as an alignment mark. The metal film according to the fourth aspect can be used as a power supply or a ground wiring. The metal film according to the fourth aspect can be used as a drawer pad. In addition, the metal film according to claim 4 can be used as a rewiring. Moreover, the metal film of the said Claim 4 can be used as a heat radiating member.
[0042]
The invention according to claim 5
A semiconductor substrate on which electrodes are formed;
An insulating film formed on the semiconductor substrate and having an opening formed at a position facing the electrode;
A plurality of on-electrode metal films stacked on the opening to be connected to the electrodes;
A metal film on an insulating film formed on the insulating film;
A semiconductor device comprising:
The plurality of metal films on the electrode has a configuration in which a metal film closer to the semiconductor substrate than the one metal film is patterned using at least one of the plurality of metal films as a mask,
In addition, the metal film on the insulating film is formed simultaneously with any one of the metal films constituting the metal film on the electrode.
[0043]
According to the above invention, since the metal film on the electrode is formed using at least one metal film of the plurality of metal films as a mask, the manufacturing process is simplified compared to the method of forming the mask with a member different from the plurality of metal films. Can be achieved.
[0044]
In addition, since the metal film on the insulating film is formed simultaneously with any one of the metal films constituting the metal film on the electrode, a method of forming the metal film on the insulating film separately from the metal film on the electrode Compared to the above, the manufacturing process can be simplified.
[0045]
Further, the invention described in claim 6
The semiconductor device according to claim 5.
The area of the metal film on the electrode is larger than the area of the opening formed in the insulating film.
[0046]
According to the above invention, since the area of the metal film on the electrode is larger than the area of the opening formed in the insulating film, the opening is covered with the metal film on the electrode and the metal film formed below the metal film. It will be. Therefore, since the electrode is not directly exposed from the opening, the electrode can be reliably protected.
[0047]
In the semiconductor device according to claim 5 or 6, the metal film on the insulating film can be used as an alignment mark, a power supply or ground wiring, a lead pad, a rewiring, and a heat dissipation member.
[0048]
The invention according to claim 7
In a semiconductor device manufacturing method including a metal film forming step of forming a plurality of metal films on a semiconductor substrate on which an electrode and an insulating film having an opening formed at a position facing the electrode are formed,
The metal film forming step includes
A laminating step of laminating a plurality of metal films containing different materials;
And a removal step of removing the other metal film using at least one of the plurality of metal films formed as a mask as a mask.
[0049]
According to the above invention, since the removal process is performed using at least one metal film of the plurality of metal films as a mask, the manufacturing process is simplified compared to the method of forming the mask with a member different from the plurality of metal films. be able to.
[0050]
The invention according to claim 8
The method of manufacturing a semiconductor device according to claim 7.
The formation position of the plurality of metal films is selected to include the formation position of the opening,
In addition, when the mask is formed by patterning the one metal film on the opening, the area of the one metal film is formed larger than the area of the opening. .
[0051]
According to the above invention, since the opening is covered with one metal film, when removing the other metal film in the removal step, the electrode is removed simultaneously with the removal of the other metal film. Can be prevented.
[0052]
The invention according to claim 9
In the manufacturing method of the semiconductor device according to claim 7 or 8,
Furthermore, it has the 2nd removal process which removes said one metal film used as a mask, It is characterized by the above-mentioned.
[0053]
According to the above invention, in the removal step of removing another metal film using one metal film as a mask, even if overetching (undercut) occurs in the other metal film, Since the metal film is removed, it is possible to prevent the one metal film in the overetching portion from peeling off and adhering to the semiconductor substrate or the metal film.
[0054]
The invention according to claim 10
In the manufacturing method of the semiconductor device according to claim 9,
The second removal step includes
It is carried out after forming an electrode member made of a material that is not removed in the second removal step on the plurality of metal films formed on the opening.
[0055]
According to the above invention, the electrode on the semiconductor substrate is an electrode made of a material that is not removed in the second removal step even if the first metal film is removed by performing the second removal step. It is protected by a member. For this reason, it can prevent reliably that the electrode formed on the semiconductor substrate is damaged during implementation of a 2nd removal process.
[0056]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0057]
5 to 8 are diagrams for explaining a semiconductor device 50A according to the first embodiment of the present invention and a manufacturing method thereof. FIG. 5 is a bottom view of the semiconductor device 50A, and FIGS. 6 to 8 are views showing a method of manufacturing the semiconductor device 50A along the manufacturing process. 6 to 8, only the method for manufacturing the solder ball 112, which is a main part of the present invention, in the manufacturing process of the semiconductor device 50A is shown and described.
[0058]
First, the configuration of the semiconductor device 50A will be described with reference to FIGS. The semiconductor device 50A is roughly composed of the semiconductor substrate 10 on which the electrode 12 is formed, the passivation film 13 (insulating film), the barrier metal 21, the probe electrode 30, and the like.
[0059]
The semiconductor substrate 10 is, for example, a silicon substrate, and a plurality of electrodes 12 made of aluminum are formed on its circuit formation surface. The circuit formation surface of the semiconductor substrate 10 is covered with a passivation film 13 which is an insulating film (silicon nitride in this embodiment), and a passivation opening 14 is formed at a position facing the electrode 12.
[0060]
A barrier metal 21 (corresponding to the metal film on the electrode described in claims) and a solder ball 22 are formed on the upper portion of the electrode 12 located on the left side in FIG. The lower part of the barrier metal 21 is joined to the electrode 12 through the passivation opening 14, and the upper part of the barrier metal 21 is joined to the solder ball 22. In addition, a probe electrode 30 is formed on the electrode 12 located on the right side in FIG.
[0061]
The barrier metal 21 has a configuration in which a first metal film 15, a second metal film 16, and a Ni plating film 19 are laminated on the electrode 12. The first metal film 15 constituting the barrier metal 21 is formed using the second metal film 16 as a mask as will be described later.
[0062]
That is, the barrier metal 21 uses the second metal film 16, which is one of the metal films 15, 16, and 19, as a mask, and a semiconductor substrate rather than the second metal film 16. The first metal film 15 close to 10 is etched. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced as compared with the method of forming a mask using a member (for example, resist) different from each of the metal films 15, 16, and 19 constituting the barrier metal 21. .
[0063]
Further, the barrier metal 21 has high conductivity, good adhesion to the electrode 12, good adhesion to the solder ball 22, and diffusion between the electrode 12 and the solder ball 22. Characteristics such as not occurring and not obstructing the shaping of the solder ball 112 are required. For this reason, titanium (Ti) is selected as the material of the first metal film 15, and nickel (Ni) is selected as the material of the second metal film 16 and the Ni plating film 19.
[0064]
On the other hand, the probe electrode 30 (corresponding to the metal film on an insulating film described in the claims) is configured such that only the first metal film 15 is formed on the electrode 12. The first metal film 15 constituting the probe electrode 30 is formed simultaneously with the first metal film 15 constituting the barrier metal 21 as will be described later. Therefore, compared to a method in which the probe electrode 30 is formed of a material different from the material used for the barrier metal 21, the manufacturing process can be simplified and the manufacturing cost can be reduced.
[0065]
In the semiconductor device 50A configured as described above, the solder ball 22 functions as an external connection terminal, and is joined to a pad formed on the mounting substrate when the semiconductor device 50A is mounted on the mounting substrate or the like. On the other hand, the probe electrode 30 is a test electrode, and the probe 32 is connected during the test.
[0066]
Thus, by separately forming the solder ball 22 used for mounting and the probe electrode 30 used for the test, it is not necessary to bring the probe 32 into contact with the solder ball 22 during the test, and the solder ball 22 is damaged. It can be prevented from sticking. In the above description, the “upper part” is the arrow X1 direction side in FIG. 8 (O), and the “lower part” is the arrow X2 direction side.
[0067]
Next, a method for manufacturing the semiconductor device 50A configured as described above will be described.
[0068]
FIG. 6A shows a state in which a passivation film 13 is formed on a semiconductor substrate 10 having an electrode 12 made of aluminum. A passivation opening 14 is formed at a position facing the electrode 12 of the passivation film 13, so that the electrode 12 is exposed to the outside through the passivation opening 14.
[0069]
In addition, the electrode 12 located on the left side in the drawing is an electrode for external connection, and a barrier metal 21 and a solder ball 22 are formed later (see FIG. 8O). On the other hand, the electrode 12 located on the right side in the figure is a test electrode, and the probe 32 is connected during the test (see FIG. 2O).
[0070]
First, the surface oxide of about 2 nm formed in the portion exposed from the passivation opening 14 of the electrode 12 is removed (patterned) from the semiconductor substrate 10 by sputtering using a silicon wafer as a target. Subsequently, as shown in FIG. 6B, a first metal film 15 and a second metal film 16 are formed on the semiconductor substrate 10.
[0071]
Specifically, the semiconductor substrate 10 is mounted on a sputtering apparatus, and first, titanium (Ti), which becomes the first metal film 15, is formed in a circuit in which the electrodes 12 of the semiconductor substrate 10 are formed with a thickness of 100 nm for 500 seconds. It is formed on the entire surface side. Subsequently, nickel (Ni) to be the second metal film 16 is formed on the entire upper surface of the first metal film 15 with a thickness of 500 nm for 120 seconds.
[0072]
When the first and second metal films 15 and 16 are formed as described above, a photoresist is subsequently applied onto the semiconductor substrate 10 by a spinner. Next, after pre-baking the photoresist, exposure processing, development processing, and baking processing are sequentially performed. As a result, as shown in FIG. 6C, a photoresist 17 patterned into a predetermined shape is formed. The photoresist 17 is formed at the upper position of each electrode 12. The diameter W4 is set to be larger than the diameter W3 of the passivation opening 14 formed in the passivation film 13 (W4> W3).
[0073]
Subsequently, using the photoresist 17 as a mask, the second metal film 16 is etched with an etchant containing HNO3. FIG. 6D shows a state in which this etching process is completed. Since this etching is performed using the photoresist 17 as a mask, and the above etchant does not corrode the first metal film 15 (Ti), the portion of the second metal film 16 corresponding to the shape of the photoresist 17 Remains undissolved.
[0074]
Since the diameter of the second metal film 16 after the etching is equal to the diameter of the photoresist 17, it is W4. Therefore, the diameter W4 of the second metal film 16 is also larger than the diameter W3 of the passivation opening 14 (W4> W3). When the etching process for the second metal film 16 is completed, the photoresist 17 is removed by a resist stripping apparatus. FIG. 6E shows a state where the photoresist 17 is removed.
[0075]
Subsequently, the semiconductor substrate 10 is mounted on a spinner, and a photoresist is applied on the semiconductor substrate 10. Next, after pre-baking the photoresist, an exposure process, a development process, and a baking process were sequentially performed. As a result, as shown in FIG. A second photoresist 25A is formed.
[0076]
When the second photoresist 25A is formed, there may be a scum 27 that is a resist residue on the second metal film 16 in which the photoresist opening 26A is opened. For this reason, the process of attaching the semiconductor substrate 10 to the ashing device and ashing and removing the scum 27 is performed. FIG. 7G shows a state where the ashing removal of the scum 27 has been completed.
[0077]
Subsequently, by using the first metal film 15 formed on the semiconductor substrate 10 as a power supply film, the second metal film 16 located in the photoresist opening 26A is used as a cathode of the plating solution, and nickel. (Ni) electroplating is performed. As a result, as shown in FIG. 9H, a Ni plating film 19 having a thickness of 2 μm is formed on the second metal film 16 in the photoresist opening 26A. The Ni plating film 19 functions as an intermediate layer that functions to improve the adhesion between the second metal film 16 and the solder balls 22 to be formed later.
[0078]
When the formation of the Ni plating film 19 is completed, the electrolytic solder plating 20 is subsequently formed by electrolytic plating by continuous processing. The plating composition of the electrolytic solder plating 20 in this example is a Pb / Sn eutectic solder, and the weight ratio is Pb: Sn = 38: 62. FIG. 7I shows a state in which the electrolytic solder plating 20 is formed on the Ni plating film 19.
[0079]
When the plating process of the electrolytic solder plating 20 is completed, the second photoresist 25A is removed. As a result, as shown in FIG. 7J, the first metal film 15 and the second metal film 16 on the electrode 12 located on the right side are exposed.
[0080]
Subsequently, an etching process for removing (patterning) unnecessary portions of the first metal film 15 is performed. When this etching process is performed, the first metal film 15 on the electrode 12 located on the left side uses the electrolytic solder plating 20 as a mask, and the first metal film 15 on the electrode 12 located on the right side becomes the second metal film. 16 becomes a mask.
[0081]
The etchant used for this etching is a mixed solution containing NH4OH. This etchant is a selective etchant that dissolves only the first metal film 15 (Ti) and does not dissolve the second metal film 16 (Ni), the Ni plating film 19, and the electrolytic solder plating 20. Therefore, by performing this etching process, as shown in FIG. 8K, the first metal film 15 is removed (patterned) except for the positions where the electrolytic solder plating 20 and the second metal film 16 are formed. The
[0082]
At this time, since the diameter W4 of the second metal film 16 is larger than the diameter W3 of the passivation opening 14 (W4> W3) as described above, the electrode 12 is formed by removing (patterning) the second photoresist 25A. There is no direct exposure to the outside. For this reason, the etchant does not reach the electrode 12 during the etching process, so that it is possible to reliably prevent and protect the electrode 12 from being damaged during the etching of the first metal film 15.
[0083]
When the first metal film 15 is etched, the first metal film 15 on the electrode 12 located on the left side is composed of the electrolytic solder plating 20, the Ni plating film 19, and the second metal film 16. Even if it functions as a mask, the side portion may be etched by the etchant and an over-etched portion 28 (undercut) may occur. The same applies to the first metal film 15 on the electrode 12 located on the right side, and even if the second metal film 16 functions as a mask, the side portion is etched by the etchant and the overetched portion 28 is generated. There is.
[0084]
In the drawing, since the thickness of the first metal film 15 and the second metal film 16 is drawn large for the sake of illustration, the depth of the overetched portion 28 seems to be small, but in reality it depends on the control of the etching time management. It's deep. Therefore, the outer peripheral edge of the second metal film 16 extends longer outward than the first metal film 15.
[0085]
Therefore, when the extended portion of the second metal film 16 (hereinafter referred to as the extended metal film) is scattered by, for example, cooling water sprayed when the semiconductor substrate 10 is diced, the electrolytic solder plating 20, the second On the metal film 16 or the passivation film 13. If the extended metal film remains attached to the electrolytic solder plating 20 or the like, the scattered metal film may have an adverse effect during mounting, and the mounting process may not be performed reliably, or an underfill resin is provided. Inconvenience that the bonding force of the underfill resin is weakened occurs.
[0086]
Therefore, in this embodiment, after the etching process of the first metal film 15 using the electrolytic solder plating 20 or the like as a mask is completed, the etching process for removing the second metal film 16 (the second process described in the claims). Corresponding to the removal step). The etchant used for this etching process is selected to remove only the second metal film 16. FIG. 8L shows a state where the second metal film 16 has been removed.
[0087]
As described above, by performing the etching process for removing the second metal film 16, the above-described extended metal film adheres to the electrolytic solder plating 20, the second metal film 16, the passivation film 13, or the like. Therefore, the mounting reliability of the semiconductor device 50A can be improved. Even when the etching process for removing the second metal film 16 is performed, the electrode 12 is protected by the first metal film 15, so that it is ensured that the electrode 12 is damaged by the etchant used for the etching process. Can be prevented.
[0088]
When the removal of the second metal film 16 is completed as described above, the flux 31 is applied to the entire upper surface of the semiconductor substrate 10 as shown in FIG. Nitrogen atmosphere heating at a temperature of 0 ° C. is performed with a reflow apparatus. As a result, removal of acid substances from the electrolytic solder plating 20 is performed, and bump shaping of the solder balls 22 is performed as shown in FIG. Subsequently, the flux 31 is cleaned with an organic compound, whereby the semiconductor device 50A shown in FIG. 8O is completed.
[0089]
Next, a modified example of the manufacturing method according to the first embodiment will be described.
FIG. 9 is a process diagram showing a modification of the first embodiment. In FIG. 9, the same components as those shown in FIGS. 6 to 8 are denoted by the same reference numerals, and the description thereof is omitted. Further, the manufacturing method shown in FIGS. 6A to 7J shown in the first embodiment is exactly the same as that of the present modification. Therefore, the following description will be made on the manufacturing method after FIG. 7J. And
[0090]
In the method of manufacturing the semiconductor device 50A according to the first embodiment described above, the etching process (second removal process) for removing the second metal film 16 was performed with the overetched portion 28 as a problem. However, when the etching process of the first metal film 15 can be accurately controlled, or when dry etching is performed, it is possible to suppress the occurrence of the overetched portion 28.
[0091]
When the overetched portion 28 does not occur, the above-described extended metal film does not occur, and therefore it is not necessary to remove the second metal film 16 after the etching of the first metal film 15. For this reason, in this modification, as shown in FIG. 9A, the probe electrode 30A is formed by the first metal film 15 and the second metal film 16 formed on the right electrode 12. Yes.
[0092]
Therefore, the probe electrode 30A composed of the first and second metal films 15 and 16 shown in FIG. 9A does not remove (butter) the second metal film 16, and FIG. As shown in FIG. 9D, a flux 31 coating process, an acid deposit removal process for the electrolytic solder plating 20, a bump shaping process for the solder ball 22, and a cleaning process for the flux 31 with an organic compound are performed. The semiconductor device 50B shown in 9 (D) is manufactured.
[0093]
Next, a second embodiment of the present invention will be described.
[0094]
10 and 11 are views showing a method of manufacturing the semiconductor device 50D according to the second embodiment. 10 and 11, the same components as those shown in FIGS. 6 to 8 are denoted by the same reference numerals, and the description thereof is omitted. Also, the manufacturing method shown in FIGS. 6A to 6E shown in the first embodiment is exactly the same as that of this embodiment, and therefore, the manufacturing method after FIG. 6E will be described in the following description. .
[0095]
FIG. 6E described above shows a state where the photoresist 17 is removed. After removing the photoresist 17, the semiconductor substrate 10 is mounted on a spinner, and a process of applying a photoresist on the semiconductor substrate 10 is performed. Next, after pre-baking the photoresist, an exposure process, a development process, and a baking process are sequentially performed. As a result, as shown in FIG. A second photoresist 25B is formed.
[0096]
At this time, in this embodiment, the depth H2 of the photoresist opening 26B is formed to be deeper than the depth H1 of the photoresist opening 26A in the first embodiment (see FIG. 7F). (H2> H1).
[0097]
When the second photoresist 25B having the photoresist opening 26B is formed as described above, a removal process by ashing of the scum 27 is subsequently performed as shown in FIG. Subsequently, by using the first metal film 15 formed on the semiconductor substrate 10 as a power supply film, the second metal film 16 located in the photoresist opening 26A is used as a cathode of the plating solution, and nickel. (Ni) electroplating is performed. Thus, as shown in FIG. 10H, the Ni plating film 19 is formed on the second metal film 16 in the photoresist opening 26A.
[0098]
When the formation of the Ni plating film 19 is completed, the gold bumps 33 are subsequently formed by electrolytic plating by continuous processing. FIG. 10I shows a state in which gold bumps 33 are formed on the Ni plating film 19.
[0099]
When the plating process for the gold bump 33 is completed, the second photoresist 25B is removed. As a result, as shown in FIG. 10J, the first metal film 15 and the second metal film 16 on the electrode 12 located on the right side are exposed.
[0100]
Subsequently, an etching process for removing (patterning) unnecessary portions of the first metal film 15 is performed. When performing this etching process, the first metal film 15 on the electrode 12 located on the left side also uses the electrolytic solder plating 20 as a mask in this embodiment, and the first metal film 15 on the electrode 12 located on the right side The gold bump 33 becomes a mask.
[0101]
The etchant used for this etching is a selective etchant that dissolves only the first metal film 15 (Ti) and does not dissolve the second metal film 16 (Ni), the Ni plating film 19, and the gold bump 33. Therefore, by performing this etching process, the first metal film 15 is removed (patterned) except for the formation positions of the gold bumps 33 and the second metal film 16 as shown in FIG. .
[0102]
At this time, since the diameter W4 of the second metal film 16 is larger than the diameter W3 of the passivation opening 14 (W4> W3), also in this embodiment, the electrode 12 is removed by the removal (patterning) of the second photoresist 25A. Is not directly exposed to the outside. For this reason, the etchant does not reach the electrode 12 during the etching process, so that it is possible to reliably prevent and protect the electrode 12 from being damaged during the etching of the first metal film 15.
[0103]
Also, in this embodiment, since the over-etched portion 28 (undercut) occurs when the first metal film 15 is etched, after the etching process for the first metal film 15 is finished, An etching process for removing the second metal film 16 is performed. Therefore, also in this embodiment, the extension metal film can be prevented from adhering to the gold bump 33, the second metal film 16, or the passivation film 13, and the mounting reliability of the semiconductor device 50C can be improved. it can.
[0104]
Further, in the first embodiment described above, after performing the etching process for removing the second metal film 16, the flux 31 is applied to form the solder balls 22, and the acid oxide removal process for the electrolytic solder plating 20. The bump shaping process of the solder ball 22 was performed, but in this embodiment, solder is not used, and the gold bump 33 is formed instead of the solder ball 22. For this reason, the above-described flux application process or the like necessary for forming the solder ball 22 is not necessary, and the semiconductor device is formed as shown in FIG. 11L when the etching process for removing the second metal film 16 is performed. 50C is completed. Therefore, according to the present embodiment, the manufacturing process of the semiconductor device 50D can be simplified as compared with the first embodiment.
[0105]
FIG. 12 shows a modification of the second embodiment. Also in the second embodiment, when the etching process of the first metal film 15 can be accurately controlled or when dry etching is performed, the second metal film 16 is removed after the etching of the first metal film 15. There is no need. For this reason, in this modification, as shown in FIG. 12, the probe electrode 30 </ b> A is formed by the first metal film 15 and the second metal film 16 formed on the right electrode 12.
[0106]
Next, a third embodiment of the present invention will be described.
[0107]
13 to 15 are views showing a method of manufacturing the semiconductor device 50E according to the third embodiment. 13 to 15, the same components as those shown in FIGS. 6 to 8 are denoted by the same reference numerals, and the description thereof is omitted.
[0108]
FIG. 13A shows a state in which a passivation film 13 is formed on a semiconductor substrate 10 having an electrode 12 made of aluminum. A passivation opening 14 is formed at a position facing the electrode 12 of the passivation film 13, so that the electrode 12 is exposed to the outside through the passivation opening 14. In this embodiment, the barrier metal 21 and the solder ball 22 are formed later on both the left and right electrodes 12 (see FIG. 15K).
[0109]
First, a surface oxide of about 2 nm formed on the semiconductor substrate 10 in a portion exposed from the passivation opening 14 of the electrode 12 is removed by sputtering using a silicon wafer as a target. Subsequently, as shown in FIG. 13B, a first metal film 15 and a second metal film 16 are formed on the semiconductor substrate 10 as in the first embodiment.
[0110]
When the first and second metal films 15 and 16 are formed as described above, a photoresist is subsequently applied onto the semiconductor substrate 10 by a spinner, and then pre-baking, exposure processing, and development are performed on the photoresist. By sequentially performing the process and the baking process, as shown in FIG. 13C, a first photoresist 17 patterned into a predetermined shape is formed. The first photoresist 17 is formed at an upper position of each electrode 12. The diameter W6 is set to be larger than the diameter W5 of the passivation opening 14 formed in the passivation film 13 (W6> W5).
[0111]
Subsequently, using the first photoresist 17 as a mask, the second metal film 16 is etched with an etchant containing HNO3. FIG. 13D shows a state in which this etching process is completed. Since this etching is performed using the first photoresist 17 as a mask, and the etchant does not corrode the first metal film 15 (Ti), the photoresist 17 of the second metal film 16 is shaped. The corresponding part remains undissolved. At this time, the diameter of the second metal film 16 after etching is equal to the diameter of the photoresist 17, so that it becomes W4, which is larger than the diameter W3 of the passivation opening 14 (W4> W3).
[0112]
When the etching process for the second metal film 16 is completed, the first photoresist 17 is removed by a resist stripping apparatus. FIG. 13E shows a state where the photoresist 17 is removed.
[0113]
Subsequently, the semiconductor substrate 10 is mounted on a spinner, and a photoresist is applied on the semiconductor substrate 10. Next, after pre-baking the photoresist, an exposure process, a development process, and a baking process are sequentially performed. As a result, as shown in FIG. A second photoresist 25C having a resist opening 26C is formed.
[0114]
Subsequently, by using the first metal film 15 formed on the semiconductor substrate 10 as a power supply film, the second metal film 16 positioned in the photoresist opening 26C is used as a cathode of the plating solution, and an electric field is applied. By performing the plating process, the Ni plating film 19 and the electrolytic solder plating 20 are formed. FIG. 14G shows a state in which the Ni plating film 19 and the electrolytic solder plating 20 are formed (the description of the removal process by ashing of the scum 27 is omitted).
[0115]
When the plating process of the electrolytic solder plating 20 is completed, the second photoresist 25C is removed as shown in FIG. Subsequently, an etching process for removing (patterning) unnecessary portions of the first metal film 15 is performed. When this etching process is performed, the first metal film 15 is etched using each electrolytic solder plating 20 as a mask.
[0116]
The etchant used for this etching is also a selective etchant that dissolves only the first metal film 15 (Ti) and does not dissolve the second metal film 16 (Ni), the Ni plating film 19, and the electrolytic solder plating 20. Therefore, by performing this etching process, as shown in FIG. 14I, the first metal film 15 is removed except for the position where each electrolytic solder plating 20 is formed.
[0117]
Also in this embodiment, since the overetched portion 28 (undercut) may occur and an extended metal film may be generated, the second metal film is formed after the etching process of the first metal film 15 is completed. An etching process for removing 16 is performed. The etchant used for this etching process is selected to remove only the second metal film 16. FIG. 14J shows a state where the second metal film 16 has been removed.
[0118]
Subsequently, a flux 31 application process for forming the solder balls 22, an oxalate removal process for the electrolytic solder plating 20, a bump shaping process for the solder balls 22, and a cleaning process for the flux 31 using an organic compound are performed. As a result, the semiconductor device 50E shown in FIG. As described above, also in the semiconductor device 50E in which the barrier metal 21 and the solder ball 22 are formed on each electrode 12, the use of the above manufacturing method ensures that the electrode 12 is damaged during the manufacturing process. Can be prevented.
[0119]
FIG. 16 is a process diagram showing a modification of the third embodiment. In FIG. 16, the same components as those shown in FIGS. 13 to 15 are denoted by the same reference numerals, and the description thereof is omitted. In addition, the manufacturing method shown in FIGS. 13A to 14H shown in the third embodiment is exactly the same as that of the present modification. Therefore, the following description will be made on the manufacturing method after FIG. And
[0120]
Also in the third embodiment, when the etching process of the first metal film 15 can be accurately controlled, or when dry etching is performed, the overetched portion 28 is generated as shown in FIG. There is no need to remove the second metal film 16 after the etching of the first metal film 15. For this reason, in the present modification, as shown in FIG. 16B, the first metal film 15 and the second metal film having substantially the same diameter without etching the second metal film 16. 16 to manufacture the semiconductor device 50F having the barrier metal 21.
[0121]
Next, fourth to ninth embodiments of the present invention will be described with reference to FIGS.
17 and 18 show a semiconductor device 50G according to the fourth embodiment. FIG. 17 is a bottom view of the semiconductor device 50G, and FIG. 18 is a cross-sectional view of the semiconductor device 50G.
[0122]
In each of the above-described embodiments, when the first metal film 15 and / or the second metal film 16 is left on the semiconductor substrate 10, the probe electrode 30 is formed on the electrode 12. However, the first metal film 15 and / or the second metal film 16 can be used in various ways other than the probe electrode 30, and the formation position is not necessarily limited to the upper part of the electrode 12. Absent. That is, the first metal film 15 and / or the second metal film 16 can be formed at any position on the passivation film 13.
[0123]
Therefore, in this embodiment, the first metal film 15 formed as shown in FIG. 8L in the first embodiment described above is not the upper position of the electrode 12, but a semiconductor substrate as shown in FIG. It is used as the alignment mark 40 by forming it at 10 corners.
[0124]
FIG. 19 shows a semiconductor device 50H according to the fifth embodiment. In this embodiment, the power supply solder balls 22A are connected by the power supply wiring 41 formed by the first metal film 15. With this configuration, the impedance of the power supply wiring 41 can be reduced, high-frequency noise can be reduced, and stable power supply can be performed.
[0125]
FIG. 20 shows a semiconductor device 50I according to the sixth embodiment. In this embodiment, the first metal film 15 constituting the barrier metal 21 on which the solder balls 22 are formed is directly drawn, thereby forming a drawing pad 42 with which the probe comes into contact. With this configuration, it is not necessary to form the probe connection electrode 12 on the semiconductor substrate 10, and the wiring design of the semiconductor substrate 10 can be facilitated.
[0126]
FIG. 21 shows a semiconductor device 50J according to the seventh embodiment. The present embodiment is characterized in that the rewiring 43 is formed by the first metal film 15. As a result, the solder ball 22 can be formed at a position different from the electrode formation position 44.
[0127]
By adopting the configuration of the present embodiment, the solder balls 22 can be arranged at an equal pitch and close to each other, and the fatigue fracture life of the solder balls 22 can be extended. In other words, it is known that the fatigue failure life is inversely proportional to the square of the distance between all bump centers and the farthest bump, and therefore the fatigue failure life can be improved by the configuration of this embodiment. Further, by providing the rewiring 43, the thermal fatigue stress can be reduced to the electrode 12 made of aluminum, and the degree of freedom of the arrangement position of the solder ball 22 can be expanded, so that the semiconductor device 50J can have a high density.
[0128]
FIG. 22 shows a semiconductor device 50K according to the eighth embodiment. This embodiment is characterized in that the first metal film 15 is used as a so-called ground solid layer. Therefore, the first metal film 15 is configured to be electrically connected to the ground solder ball 22B.
[0129]
With this configuration, the electronic circuit formed on the semiconductor substrate 10 can be prevented from being affected by disturbances such as electromagnetic waves, and the operation reliability of the semiconductor device 50K can be improved. Furthermore, the first metal film 15 can also be used as a heat radiating member. In this case, heat generated on the circuit formation surface of the semiconductor substrate 10 can be efficiently radiated, and this also allows the semiconductor device to be radiated. The operational reliability of 50K can be increased.
[0130]
FIG. 23 shows a semiconductor device 50L according to the ninth embodiment. The present embodiment is characterized in that a dummy bump 45 is formed at the center of the back surface of the semiconductor device 50K according to the eighth embodiment. By providing the dummy bump 45, the heat generated on the circuit forming surface can be radiated more efficiently. In FIGS. 22 and 23, the first metal film 15 is a solid layer, but may be a mesh.
[0131]
Regarding the above description, the following items are further disclosed.
[0132]
(Supplementary note 1) a semiconductor substrate on which an electrode is formed;
An insulating film formed on the semiconductor substrate and having an opening formed at a position facing the electrode;
A plurality of stacked metal films;
In a semiconductor device having
A semiconductor device characterized in that, among the plurality of metal films, a metal film closer to the semiconductor substrate than the one metal film is patterned using at least one metal film as a mask.
[0133]
(Appendix 2) In the semiconductor device according to Appendix 1,
The semiconductor device, wherein the plurality of metal films are formed on the opening so as to be connected to the electrode.
[0134]
(Appendix 3) In the semiconductor device according to Appendix 1 or 2,
The semiconductor device according to claim 1, wherein an area of the one metal film is larger than an area of an opening formed in the insulating film.
[0135]
(Appendix 4) In the semiconductor device according to Appendix 1 or 2,
One or a plurality of metal films among the plurality of metal films are formed on top of the insulating film.
[0136]
(Appendix 5) In the semiconductor device according to Appendix 4,
A semiconductor device using the metal film as an alignment mark.
[0137]
(Appendix 6) In the semiconductor device described in Appendix 4,
A semiconductor device using the metal film as a power source or a ground wiring.
[0138]
(Appendix 7) In the semiconductor device described in Appendix 4,
A semiconductor device using the metal film as a lead pad.
[0139]
(Appendix 8) In the semiconductor device according to Appendix 4,
A semiconductor device using the metal film as a rewiring.
[0140]
(Supplementary note 9) In the semiconductor device according to supplementary note 4,
A semiconductor device using the metal film as a heat dissipation member.
[0141]
(Additional remark 10) The semiconductor substrate in which the electrode was formed,
An insulating film formed on the semiconductor substrate and having an opening formed at a position facing the electrode;
A plurality of on-electrode metal films stacked on the opening to be connected to the electrodes;
A metal film on an insulating film formed on the insulating film;
A semiconductor device comprising:
The plurality of metal films on the electrode has a configuration in which a metal film closer to the semiconductor substrate than the one metal film is patterned using at least one of the plurality of metal films as a mask,
In addition, the metal film on the insulating film is formed simultaneously with any one of the metal films constituting the metal film on the electrode.
[0142]
(Supplementary note 11) In the semiconductor device according to supplementary note 10,
The semiconductor device according to claim 1, wherein the area of the metal film on the electrode is larger than the area of the opening formed in the insulating film.
[0143]
(Appendix 12) In the semiconductor device according to Appendix 10 or 11,
A semiconductor device using the metal film on an insulating film as an alignment mark.
[0144]
(Supplementary note 13) In the semiconductor device according to supplementary note 10 or 11,
A semiconductor device characterized in that the metal film on the insulating film is used as a power supply or a ground wiring.
[0145]
(Appendix 14) In the semiconductor device according to Appendix 10 or 11,
A semiconductor device characterized in that the metal film on the insulating film is used as a lead pad.
[0146]
(Supplementary Note 15) In the semiconductor device according to Supplementary Note 10 or 11,
A semiconductor device characterized in that the metal film on the insulating film is used as a rewiring.
[0147]
(Supplementary note 16) In the semiconductor device according to supplementary note 10 or 11,
A semiconductor device characterized in that the metal film on the insulating film is used as a heat dissipation member.
[0148]
(Additional remark 17) In the manufacturing method of the semiconductor device which has the metal film formation process which laminates and forms a several metal film with respect to the semiconductor substrate with which the electrode and the insulating film in which the opening part was formed in the position facing this electrode were formed ,
The metal film forming step includes
A laminating step of laminating a plurality of metal films containing different materials;
A removal step of removing the other metal film using at least one metal film as a mask among the plurality of metal films formed in a stack;
A method for manufacturing a semiconductor device, comprising:
[0149]
(Supplementary note 18) In the method for manufacturing a semiconductor device according to supplementary note 17,
The formation position of the plurality of metal films is selected to include the formation position of the opening,
In addition, when the mask is formed by patterning the one metal film on the opening, the area of the one metal film is formed to be larger than the area of the opening. Production method.
[0150]
(Supplementary note 19) The method for manufacturing a semiconductor device according to supplementary note 17 or 18, further comprising a second removal step of removing the one metal film used as a mask.
[0151]
(Supplementary note 20) In the method for manufacturing a semiconductor device according to supplementary note 19,
The second removal step includes
A method for manufacturing a semiconductor device, comprising: forming an electrode member made of a material that is not removed in the second removal step on the plurality of metal films formed on the opening.
[0152]
【The invention's effect】
As described above, according to the present invention, various effects described below can be realized.
[0153]
According to the first aspect of the present invention, since one metal film functioning as a power supply film for electroplating can be left as it is in the manufacturing process, the mask is formed of a member different from a plurality of metal films. In comparison, the manufacturing process can be simplified.
[0154]
According to the invention described in claim 2, when a plurality of metal films can be used as terminals for external connection of electrodes, and when external connection terminals (solder balls or the like) are provided on the plurality of metal films. Can make a plurality of metal films function as barrier metals.
[0155]
According to the invention described in claim 3, the opening is covered with one metal film and a metal film formed below the metal film, so that the electrode is not directly exposed from the opening. Can be reliably protected.
[0156]
According to the invention described in claim 4, since the plurality of metal films can be formed at arbitrary positions on the insulating film, the formation position of the metal film can be selected with a degree of freedom. .
[0157]
According to the invention described in claim 5, the manufacturing process can be simplified as compared with the method of forming the mask with a member different from the plurality of metal films. In addition, the manufacturing process can be simplified as compared with the method in which the metal film on the insulating film is formed separately from the metal film on the electrode.
[0158]
Further, according to the invention of claim 6, since the opening is covered with the metal film on the electrode and the metal film formed below this, the electrode is not directly exposed from the opening, Therefore, the electrode can be reliably protected.
[0159]
According to the invention described in claim 7, since the removal step is performed using at least one metal film of the plurality of metal films as a mask, it is manufactured in comparison with the method of forming the mask with a member different from the plurality of metal films. Simplification of the process can be achieved.
[0160]
According to the eighth aspect of the invention, since the opening is covered with one metal film, when removing the other metal film in the removal step, the electrode removes the other metal film. It can be prevented from being removed simultaneously.
[0161]
According to the ninth aspect of the present invention, even if overetching (undercut) occurs in the other metal film in the removal step of removing the other metal film using the one metal film as a mask, Since the one metal film is removed by this removing step, it is possible to prevent the one metal film in the overetched portion from peeling off and adhering to the semiconductor substrate or the metal film.
[0162]
According to the tenth aspect of the invention, since the electrode on the semiconductor substrate is protected by the electrode member made of a material that is not removed in the second removal step, the semiconductor substrate is subjected to the second removal step. It can prevent reliably that the electrode formed on it is damaged.
[Brief description of the drawings]
FIG. 1 is a process diagram for explaining a semiconductor device manufacturing method according to a first conventional example (part 1);
FIG. 2 is a step diagram for explaining the semiconductor device manufacturing method of the first conventional example (part 2);
FIG. 3 is a process diagram for explaining a semiconductor device manufacturing method which is a second conventional example (part 1);
FIG. 4 is a process diagram for explaining a semiconductor device manufacturing method which is a second conventional example (part 2);
FIG. 5 is a bottom view of the semiconductor device according to the first embodiment of the present invention.
FIG. 6 is a process diagram for explaining the method of manufacturing a semiconductor device according to the first embodiment of the present invention (No. 1).
FIG. 7 is a step diagram for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention (No. 2);
FIG. 8 is a process diagram for explaining the method of manufacturing a semiconductor device according to the first embodiment of the present invention (No. 3).
FIG. 9 is a process diagram for describing a modification of the semiconductor device manufacturing method according to the first embodiment of the present invention;
FIG. 10 is a process diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention (No. 1).
FIG. 11 is a process diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention (No. 2).
FIG. 12 is a process diagram for describing a modification of the semiconductor device manufacturing method according to the second embodiment of the present invention;
FIG. 13 is a process diagram for explaining a method of manufacturing a semiconductor device according to a third embodiment of the present invention (No. 1);
FIG. 14 is a step diagram for explaining the method of manufacturing a semiconductor device according to the third embodiment of the present invention (No. 2).
FIG. 15 is a process diagram for explaining a method of manufacturing a semiconductor device according to a third embodiment of the present invention (No. 3);
FIG. 16 is a process diagram for describing a modification of the semiconductor device manufacturing method according to the third embodiment of the present invention;
FIG. 17 is a bottom view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 18 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 19 is a bottom view of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 20 is a bottom view of a semiconductor device according to a sixth embodiment of the present invention.
FIG. 21 is a bottom view of a semiconductor device according to a seventh embodiment of the present invention.
FIG. 22 is a bottom view of a semiconductor device according to an eighth embodiment of the present invention.
FIG. 23 is a bottom view of a semiconductor device according to a ninth embodiment of the present invention.
[Explanation of symbols]
10 Semiconductor substrate
12 electrodes
12A electrode
13 Passivation film
14 Passivation opening
15 First metal film
16 Second metal film
17 photoresist
19 Ni plating film
20 Electrolytic solder plating
21 barrier metal
22 Solder balls
22A Solder ball for power supply
22B Ground solder balls
25A-25C second photoresist
26A-26C Photoresist opening
27 Scum
28 Over-etched section
30 Electrode for probe
30A Probe electrode
32 probes
33 gold bump
40 Alignment mark
41 Power supply wiring
42 Drawer pad
43 Rewiring
44 Electrode formation position
45 dummy bump
50A-50K semiconductor device

Claims (10)

A semiconductor substrate on which electrodes are formed;
An insulating film formed on the semiconductor substrate and having an opening formed at a position facing the electrode;
A plurality of stacked metal films;
In a semiconductor device having
A semiconductor device characterized in that, among the plurality of metal films, a metal film closer to the semiconductor substrate than the one metal film is patterned using at least one metal film as a mask. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of metal films are formed on the opening so as to be connected to the electrode. The semiconductor device according to claim 2,
The semiconductor device according to claim 1, wherein an area of the one metal film is larger than an area of an opening formed in the insulating film. The semiconductor device according to claim 1 or 2,
One or a plurality of metal films among the plurality of metal films are formed on top of the insulating film. A semiconductor substrate on which electrodes are formed;
An insulating film formed on the semiconductor substrate and having an opening formed at a position facing the electrode;
A plurality of on-electrode metal films stacked on the opening to be connected to the electrodes;
A metal film on an insulating film formed on the insulating film;
A semiconductor device comprising:
The plurality of metal films on the electrode has a configuration in which a metal film closer to the semiconductor substrate than the one metal film is patterned using at least one of the plurality of metal films as a mask,
In addition, the metal film on the insulating film is formed simultaneously with any one of the metal films constituting the metal film on the electrode. The semiconductor device according to claim 5.
The semiconductor device according to claim 1, wherein the area of the metal film on the electrode is larger than the area of the opening formed in the insulating film. In a semiconductor device manufacturing method including a metal film forming step of forming a plurality of metal films on a semiconductor substrate on which an electrode and an insulating film having an opening formed at a position facing the electrode are formed,
The metal film forming step includes
A laminating step of laminating a plurality of metal films containing different materials;
A removal step of removing the other metal film using at least one metal film as a mask among the plurality of metal films formed in a stack;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 7.
The formation position of the plurality of metal films is selected to include the formation position of the opening,
In addition, when the mask is formed by patterning the one metal film on the opening, the area of the one metal film is formed to be larger than the area of the opening. Production method. In the manufacturing method of the semiconductor device according to claim 7 or 8,
Furthermore, the manufacturing method of the semiconductor device characterized by having the 2nd removal process of removing said one metal film used as a mask. In the manufacturing method of the semiconductor device according to claim 9,
The second removal step includes
A method for manufacturing a semiconductor device, comprising: forming an electrode member made of a material that is not removed in the second removal step on the plurality of metal films formed on the opening.

Images