JP2004187285A5 - - Google Patents
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- JP2004187285A5 JP2004187285A5 JP2003386060A JP2003386060A JP2004187285A5 JP 2004187285 A5 JP2004187285 A5 JP 2004187285A5 JP 2003386060 A JP2003386060 A JP 2003386060A JP 2003386060 A JP2003386060 A JP 2003386060A JP 2004187285 A5 JP2004187285 A5 JP 2004187285A5
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Claims (14)
前記補正手段は容量素子、第１のスイッチ及び第２のスイッチを有し、
前記容量素子の第１の電極は入力端子に電気的に接続されており、
前記容量素子の第２の電極は、前記論理回路が有するトランジスタのゲートに電気的に接続されており、
前記第１のスイッチは前記トランジスタのゲートとドレインの電気的な接続を制御しており、
前記第２のスイッチは、前記トランジスタのドレインに与えられる電位を制御していることを特徴とする半導体装置。 A semiconductor device having correction means and a logic circuit,
The correction means includes a capacitive element, a first switch, and a second switch,
A first electrode of the capacitive element is electrically connected to an input terminal;
A second electrode of the capacitor is electrically connected to a gate of a transistor included in the logic circuit;
The first switch controls the electrical connection between the gate and drain of the transistor;
The semiconductor device, wherein the second switch controls a potential applied to a drain of the transistor.
前記補正手段は容量素子と、第１乃至第４のスイッチとを有し、
前記第３のスイッチによって、入力信号の電位の、前記容量素子の第１の電極への供給が制御されており、
前記第４のスイッチによって、第１の電源電位の、前記容量素子の第１の電極への供給が制御されており、
前記容量素子の第２の電極は、前記論理回路が有するトランジスタのゲートに電気的に接続されており、
前記第１のスイッチは前記トランジスタのゲートとドレインの電気的な接続を制御しており、
前記第２のスイッチは、前記トランジスタのドレインに与えられる電位を制御していることを特徴とする半導体装置。 A semiconductor device having correction means and a logic circuit,
The correction means includes a capacitive element and first to fourth switches,
The third switch controls the supply of the potential of the input signal to the first electrode of the capacitor,
Supply of the first power supply potential to the first electrode of the capacitor is controlled by the fourth switch;
A second electrode of the capacitor is electrically connected to a gate of a transistor included in the logic circuit;
The first switch controls the electrical connection between the gate and drain of the transistor;
The semiconductor device, wherein the second switch controls a potential applied to a drain of the transistor.
前記補正手段は容量素子及びスイッチを有し、
前記容量素子の第１の電極は入力端子に電気的に接続されており、
前記容量素子の第２の電極は、前記論理回路が有する第１のトランジスタのゲートに電気的に接続されており、
前記スイッチは前記第１のトランジスタのゲートとドレインの電気的な接続を制御しており、
前記論理回路が有する第２のトランジスタは、前記第１のトランジスタのドレインに与えられる電位を制御していることを特徴とする半導体装置。 A semiconductor device having correction means and a logic circuit,
The correction means includes a capacitive element and a switch,
The first electrode of the capacitive element is electrically connected to an input terminal;
A second electrode of the capacitor is electrically connected to a gate of a first transistor included in the logic circuit;
The switch controls the electrical connection between the gate and drain of the first transistor;
The semiconductor device, wherein the second transistor included in the logic circuit controls a potential applied to a drain of the first transistor.
前記補正手段は容量素子と、第１乃至第３のスイッチとを有し、
前記第２のスイッチによって、入力信号の電位の、前記容量素子の第１の電極への供給が制御されており、
前記第３のスイッチによって、第１の電源電位の、前記容量素子の第１の電極への供給が制御されており、
前記容量素子の第２の電極は、前記論理回路が有する第１のトランジスタのゲートに電気的に接続されており、
前記第１のスイッチは前記第１のトランジスタのゲートとドレインの電気的な接続を制御しており、
前記論理回路が有する第２のトランジスタは、前記第１のトランジスタのドレインに与えられる電位を制御していることを特徴とする半導体装置。 A semiconductor device having correction means and a logic circuit,
The correction means includes a capacitive element and first to third switches,
The second switch controls the supply of the potential of the input signal to the first electrode of the capacitive element,
Supply of the first power supply potential to the first electrode of the capacitor is controlled by the third switch;
A second electrode of the capacitor is electrically connected to a gate of a first transistor included in the logic circuit;
The first switch controls the electrical connection between the gate and drain of the first transistor;
The semiconductor device, wherein the second transistor included in the logic circuit controls a potential applied to a drain of the first transistor.
前記スイッチをオフして前記容量素子に蓄積された電荷を放電し、
前記トランジスタのゲートとドレインを電気的に切り離し、
前記第１の電極に入力信号の高電位側または低電位側の電位を供給することを特徴とする半導体装置の駆動方法。 Supplying either potential on the high potential side or the low potential side of the input signal to the first electrode of the capacitor, the gate and the drain gate is electrically connected to the second electrode of the capacitor element A first power supply potential is supplied to a source of the electrically connected transistor, and a second power supply potential is supplied to the drain of the transistor by turning on the switch;
Turning off the switch to discharge the charge accumulated in the capacitive element;
Electrically disconnect the city gate and the drain of the transistor,
A driving method of a semiconductor device, wherein a potential on a high potential side or a low potential side of an input signal is supplied to the first electrode.
前記トランジスタの極性がｐチャネル型のとき、
前記入力信号の高電位側の電位を前記第１の電極に供給することで前記容量素子に電荷を蓄積し、
前記第２の電源電位よりも前記入力信号の高電位側の電位の方が高く、
前記入力信号の高電位側の電位よりも前記第１の電源電位の方が高いことを特徴とする半導体装置の駆動方法。 In claim 7 ,
When the polarity of the transistor is a p-channel type,
By supplying a potential on the high potential side of the input signal to the first electrode, charges are accumulated in the capacitor element,
The potential on the high potential side of the input signal is higher than the second power supply potential,
The method for driving a semiconductor device, wherein the first power supply potential is higher than a potential on a high potential side of the input signal.
前記トランジスタの極性がｎチャネル型のとき、
前記入力信号の低電位側の電位を前記第１の電極に供給することで前記容量素子に電荷を蓄積し、
前記第１の電源電位よりも前記入力信号の低電位側の電位の方が高く、
前記入力信号の低電位側の電位よりも前記第２の電源電位の方が高いことを特徴とする半導体装置の駆動方法。 In claim 7 ,
When the polarity of the transistor is an n-channel type,
By supplying a potential on the low potential side of the input signal to the first electrode, charges are accumulated in the capacitor element,
The lower potential of the input signal is higher than the first power supply potential,
The method for driving a semiconductor device, wherein the second power supply potential is higher than a potential on a low potential side of the input signal.
前記トランジスタのゲートとドレインを電気的に切り離すことで、前記容量素子に前記トランジスタの閾値電圧を保持させることを特徴とする半導体装置の駆動方法。A method for driving a semiconductor device, characterized in that the threshold voltage of the transistor is held in the capacitor by electrically separating a gate and a drain of the transistor.
前記第２のスイッチをオフして前記容量素子に蓄積された電荷を放電し、
前記トランジスタのゲートとドレインを電気的に切り離し、
前記第１のスイッチをオフし、
前記第１の容量素子の第１の電極に入力信号の電位を供給することを特徴とする半導体装置の駆動方法。 The first electrode of the capacitor by turning on the first switch to supply the first power supply potential, the gate and drain electrical gate is electrically connected to the second electrode of the capacitor element A second power supply potential is supplied to the source of the connected transistor, and a third power supply potential is supplied to the drain of the transistor by turning on the second switch;
Turning off the second switch to discharge the charge accumulated in the capacitive element;
Electrically disconnect the city gate and the drain of the previous Symbol transistor,
Turning off the first switch;
A driving method of a semiconductor device, wherein a potential of an input signal is supplied to a first electrode of the first capacitor element.
前記トランジスタの極性はｐチャネル型であり、
前記第３の電源電位よりも前記第１の電源電位の方が高く、
前記第１の電源電位よりも前記入力信号の高電位側の電位の方が高く、
前記入力信号の高電位側の電位よりも前記第２の電源電位の方が高いことを特徴とする半導体装置の駆動方法。 In claim 11 ,
The transistor has a p-channel polarity,
The first power supply potential is higher than the third power supply potential;
The potential on the high potential side of the input signal is higher than the first power supply potential,
The method for driving a semiconductor device, wherein the second power supply potential is higher than a potential on a high potential side of the input signal.
前記トランジスタの極性はｎチャネル型であり、
前記第２の電源電位よりも前記入力信号の低電位側の電位の方が高く、
前記入力信号の低電位側の電位よりも前記第１の電源電位の方が高く、
前記第１の電源電位よりも前記第３の電源電位の方が高いことを特徴とする半導体装置の駆動方法。 In claim 11 ,
The polarity of the transistor is an n-channel type,
The lower potential of the input signal is higher than the second power supply potential,
The first power supply potential is higher than the potential on the low potential side of the input signal,
The method for driving a semiconductor device, wherein the third power supply potential is higher than the first power supply potential.
前記トランジスタのゲートとドレインを電気的に切り離すことで、前記容量素子に前記トランジスタの閾値電圧を保持させることを特徴とする半導体装置の駆動方法。A method for driving a semiconductor device, characterized in that the threshold voltage of the transistor is held in the capacitor by electrically separating a gate and a drain of the transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003386060A JP4357936B2 (en) | 2002-11-20 | 2003-11-17 | Semiconductor device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002335918 | 2002-11-20 | ||
| JP2003386060A JP4357936B2 (en) | 2002-11-20 | 2003-11-17 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006329043A Division JP4624340B2 (en) | 2002-11-20 | 2006-12-06 | Semiconductor display device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2004187285A JP2004187285A (en) | 2004-07-02 |
| JP2004187285A5 true JP2004187285A5 (en) | 2007-01-11 |
| JP4357936B2 JP4357936B2 (en) | 2009-11-04 |
Family
ID=32774620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003386060A Expired - Fee Related JP4357936B2 (en) | 2002-11-20 | 2003-11-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4357936B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7327168B2 (en) | 2002-11-20 | 2008-02-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and driving method thereof |
| JP4826213B2 (en) * | 2005-03-02 | 2011-11-30 | ソニー株式会社 | Level shift circuit, shift register and display device |
| JP4830504B2 (en) * | 2006-01-18 | 2011-12-07 | ソニー株式会社 | Level conversion circuit and display device |
| JP2011150270A (en) * | 2009-12-25 | 2011-08-04 | Sony Corp | Drive circuit and display device |
-
2003
- 2003-11-17 JP JP2003386060A patent/JP4357936B2/en not_active Expired - Fee Related
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