JP5025128B2 - Thin film transistor circuit - Google Patents

Description

  The present invention relates to a thin film transistor circuit capable of reducing a temperature rise of a thin film transistor.

  Conventionally, for example, a double boosting power supply circuit 1 shown in FIG.

  In the double boosting power supply circuit 1, the charging period and the discharging period come alternately.

  In the charging period, the thin film transistors Q1 and Q2 are turned on, and the thin film transistors Q3 and Q4 are turned off. Thereby, the capacitive element C2 is charged, and the voltage between the electrodes becomes equal to the voltage VCC.

  In the discharge period, the thin film transistors Q3 and Q4 are turned on, and the thin film transistors Q1 and Q2 are turned off. As a result, the voltage VCC is applied to the negative pole of the capacitive element C2, and discharge from the capacitive element C2 to the capacitive element C1 is performed. Accordingly, the potential of the positive pole of the capacitive element C1 with respect to the circuit node G increases.

  By such alternating charging and discharging periods, the potential of the positive electrode of the capacitive element C1 eventually becomes a positive potential that is twice as large as the voltage VCC.

  Conventionally, for example, a double negative voltage power supply circuit 2 shown in FIG. 5 is configured by a thin film transistor circuit.

  In the double negative voltage power supply circuit 2, the charging period and the discharging period come alternately.

  In the charging period, the thin film transistors Q11 and Q12 are turned on, and the thin film transistors Q13 and Q14 are turned off. Thereby, the capacitive element C12 is charged, and the voltage between the electrodes becomes equal to the voltage VCC.

  In the discharge period, the thin film transistors Q13 and Q14 are turned on, and the thin film transistors Q11 and Q12 are turned off. As a result, the positive pole of the capacitive element C12 is connected to the circuit node G, and further, the capacitive element C12 is discharged to the capacitive element C11. Accordingly, the potential of the negative pole of the capacitive element C11 with respect to the circuit node G drops. Negative potential.

By such alternating charging and discharging periods, the negative electrode potential of the capacitive element C11 eventually becomes a negative potential having a magnitude equal to the voltage VCC.
JP 2005-151634 A

  In the double boosting power supply circuit 1, as shown in FIG. 13, a drain current (off-state current) also flows through the thin film transistor Q2 that is off during the discharge period. Further, in the double negative voltage power supply circuit 2, as shown in FIG. 14, the drain current (off current) also flows through the thin film transistor Q <b> 14 that is turned off during the charging period.

  In these N type thin film transistors, as shown in the characteristic diagram of FIG. This is because the temperature of the thin film transistor is low. However, the off-current increases when energized for a long time. This is because the temperature rise of the thin film transistor increases. Therefore, when power is supplied for a long time, the power consumption in the power supply circuit increases.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a thin film transistor circuit capable of reducing the temperature rise of the thin film transistor.

  In order to solve the above-described problems, a thin film transistor circuit of the present invention includes a first thin film transistor that is turned on and off, a second thin film transistor that is turned off during a period in which the first thin film transistor is turned on, and turned on in a period in which the first thin film transistor is turned off. Are alternately arranged on an insulator.

  According to the present invention, since the first thin film transistor and the second thin film transistor are alternately arranged, the thin film transistor that is turned on, that is, the heat source can be dispersed in the same period, so that the temperature rise of the thin film transistor can be reduced.

  According to the thin film transistor circuit of the present invention, since the thin film transistors that are turned on in the same period can be dispersed, the temperature rise of the thin film transistors can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram of a double boosting power supply circuit 1 which is a thin film transistor circuit according to the first embodiment. In the double boosting power supply circuit 1, the charging period and the discharging period come alternately, and the current flow in each period is shown in FIGS. 1 (a) and 1 (b).

  The double boosting power supply circuit 1 includes a capacitive element C1 corresponding to the first capacitive element of the present invention and a capacitive element C2 corresponding to the second capacitive element of the present invention, and the negative pole of the capacitive element C1 is grounded. Connected to the circuit node G. The capacitive element is, for example, an electrolytic capacitor.

  The double boosting power supply circuit 1 includes a P-type thin film transistor Q1, an N-type thin film transistor Q2, and a P-type thin film transistor formed on an insulator (not shown) (for example, a substrate made of glass or the like; the same applies hereinafter). Q3 and Q4 are provided. The thin film transistors Q1 and Q2 correspond to the first thin film transistor of the present invention, and the thin film transistors Q3 and Q4 correspond to the second thin film transistor of the present invention.

  The thin film transistor Q1 is inserted between the circuit node A to which a positive voltage VCC is applied to the circuit node G and the positive electrode of the capacitive element C2 (so that a drain current flows, and so on). The thin film transistor thin film transistor Q2 is inserted between the negative pole of the capacitive element C2 and the circuit node G. The thin film transistor Q3 is inserted between the circuit node A and the negative pole of the capacitive element C2. The thin film transistor Q4 is inserted between the positive pole of the capacitive element C2 and the positive pole of the capacitive element C1.

  FIG. 2 is a diagram showing the arrangement and state transition of the thin film transistors in the double boosting power supply circuit 1.

  The thin film transistors are arranged in the order of the thin film transistors Q2, Q3, Q1, and Q4.

  In the charging period, the thin film transistors Q1 and Q2 are turned on, and the thin film transistors Q3 and Q4 are turned off. Thereby, the capacitive element C2 shown in FIG. 1 is charged, and the voltage between the electrodes becomes equal to the voltage VCC.

  In the discharge period, the thin film transistors Q3 and Q4 are turned on, and the thin film transistors Q1 and Q2 are turned off. As a result, the voltage VCC is applied to the negative pole of the capacitive element C2, and discharge from the capacitive element C2 to the capacitive element C1 is performed. Accordingly, the potential of the positive pole of the capacitive element C1 with respect to the circuit node G increases.

  By such alternating charging and discharging periods, the potential of the positive electrode of the capacitive element C1 eventually becomes a positive potential that is twice as large as the voltage VCC.

  In consideration of such operation, referring to FIG. 2, thin film transistors that are turned on in the charging period and thin film transistors that are turned on in the discharging period are alternately arranged.

  Although heat generation from the thin film transistor that occurs in the process of the above operation increases during the period in which the thin film transistor is turned on, such thin film transistors are not adjacent to each other by adopting the arrangement of FIG. That is, heat sources (thin-film transistors that are turned on) in the same period (charging period or discharging period) can be dispersed, so that an increase in temperature of each thin film transistor can be reduced. Thus, off-state current and power consumption can also be reduced. In addition, the temperature rise can be further reduced in conjunction with the reduction in power consumption.

  In view of this effect, the positions of the thin film transistors Q1 and Q2 may be reversed. Similarly, the positions of the thin film transistors Q3 and Q4 may be reversed.

  In view of such effects, as shown in FIG. 3, the thin film transistors Q1 and Q2 that are turned on during the charging period and the thin film transistors Q3 and Q4 that are turned on during the discharging period may be arranged in a staggered pattern.

  Also, as shown in FIG. 4, the outer shapes are formed in, for example, a U-shape so that the thin film transistor Q1 that is turned on in the charging period and the thin film transistor Q4 that is turned on in the discharging period are fitted to each other. By arranging so as to be fitted and the same applies to the thin film transistors Q2 and Q3, the contact area between the heat source (thin film transistor to be turned on) and the other part can be increased in the same period (charging period or discharging period). Thereby, the rising temperature of each thin film transistor can be further reduced, and as a result, the off current and the power consumption can be further reduced.

[Second Embodiment]
FIG. 5 is a circuit diagram of the double negative voltage power supply circuit 2 which is a thin film transistor circuit according to the second embodiment. In the double negative voltage power supply circuit 2, the charging period and the discharging period come alternately, and the current flow in each period is shown in FIGS. 5 (a) and 5 (b).

  The double negative voltage power supply circuit 2 includes a capacitive element C11 corresponding to the first capacitive element of the present invention and a capacitive element C12 corresponding to the second capacitive element of the present invention, and the positive electrode of the capacitive element C11 is connected to the ground. Connected to the connected circuit node G.

  The double negative voltage power supply circuit 2 includes a P-type thin film transistor Q11 and N-type thin film transistors Q12 to Q14 formed on an insulator. The thin film transistors Q11 and Q12 correspond to the first thin film transistor of the present invention, and the thin film transistors Q13 and Q14 correspond to the second thin film transistor of the present invention.

  The thin film transistor Q11 is inserted between the circuit node A to which a positive voltage VCC is applied to the circuit node G and the positive electrode of the capacitive element C12. The thin film transistor Q12 is inserted between the negative pole of the capacitive element C12 and the circuit node G. The thin film transistor Q13 is inserted between the negative pole of the capacitive element C11 and the negative pole of the capacitive element C12. The thin film transistor Q14 is inserted between the positive electrode of the capacitive element C12 and the circuit node G.

  FIG. 6 is a diagram showing the arrangement and state transition of the thin film transistors in the double negative voltage power supply circuit 2.

  The thin film transistors are arranged in the order of thin film transistors Q11, Q14, Q12, and Q13.

  In the charging period, the thin film transistors Q11 and Q12 are turned on, and the thin film transistors Q13 and Q14 are turned off. Thereby, the capacitive element C12 shown in FIG. 5 is charged, and the voltage between the electrodes becomes equal to the voltage VCC.

  In the discharge period, the thin film transistors Q13 and Q14 are turned on, and the thin film transistors Q11 and Q12 are turned off. As a result, the positive pole of the capacitive element C12 is connected to the circuit node G, and further, the capacitive element C12 is discharged to the capacitive element C11. Accordingly, the potential of the negative pole of the capacitive element C11 with respect to the circuit node G drops. Negative potential.

  By such alternating charging and discharging periods, the negative electrode potential of the capacitive element C11 eventually becomes a negative potential having a magnitude equal to the voltage VCC.

  In consideration of such operation, referring to FIG. 6, thin film transistors that are turned on in the charging period and thin film transistors that are turned on in the discharging period are alternately arranged.

  Therefore, the temperature rise of each thin film transistor can be reduced by the same operation as that of the first embodiment. In addition, off-state current and power consumption can be reduced.

  In view of this effect, the positions of the thin film transistors Q11 and Q12 may be reversed. Similarly, the positions of the thin film transistors Q13 and Q14 may be reversed.

  In view of such effects, as shown in FIG. 7, the thin film transistors Q11 and Q12 that are turned on during the charging period and the thin film transistors Q13 and Q14 that are turned on during the discharging period may be arranged in a staggered pattern.

  Further, as shown in FIG. 8, the outer shape is formed in, for example, a U-shape so that the thin film transistor Q12 that is turned on in the charging period and the thin film transistor Q13 that is turned on in the discharging period are fitted to each other. By arranging so that the thin film transistors are fitted and the same applies to the thin film transistors Q11 and Q14, similarly to FIG. 4, the rising temperature of each thin film transistor can be further reduced, and as a result, the off current and the power consumption can be further reduced. it can.

[Third Embodiment]
FIG. 9 is a circuit diagram of the double boosting power supply circuit 11 which is a thin film transistor circuit according to the third embodiment.

  The double boosting power supply circuit 11 includes a capacitive element C21 corresponding to the first capacitive element of the present invention and a capacitive element C22 corresponding to the second capacitive element of the present invention, and the negative pole of the capacitive element C21 is grounded. Connected to the circuit node G.

  The double boosting power supply circuit 11 includes P-type thin film transistors Q1-1 to Q-3, N-type thin film transistors Q2-1 to Q3, P-type thin film transistors Q3-1 to Q-3, and Q4-1 formed on an insulator. ~ 3. The thin film transistors Q1-1 to Q3 and Q2-1 to Q3 correspond to the first thin film transistor of the present invention, and the thin film transistors Q3-1 to Q3 and Q4-1 to Q3 correspond to the second thin film transistor of the present invention.

  The thin film transistors Q1-1 to Q3-3 are connected in parallel and are inserted between the circuit node A to which a positive voltage VCC is applied to the circuit node G and the positive electrode of the capacitive element C22. The thin film transistors Q2-1 to Q2-3 are connected in parallel and are inserted between the negative pole of the capacitive element C22 and the circuit node G. The thin film transistors Q3-1 to Q3-1 are connected in parallel, and are inserted between the circuit node A and the negative pole of the capacitive element C22. The thin film transistors Q4-1 to Q3-3 are connected in parallel and are inserted between the positive pole of the capacitive element C22 and the positive pole of the capacitive element C21.

  FIG. 10 is a diagram showing the arrangement and state transition of the thin film transistors in the double boosting power supply circuit 11.

  Each thin film transistor is a thin film transistor Q1-1, Q4-1, Q2-1, Q3-1, Q1-2, Q4-2, Q2-2, Q3-2, Q1-3, Q4-3, Q2-3, Q3. Are arranged in the order of -3. In the figure, thin film transistors connected in parallel are connected to each other.

  In the double boosting power supply circuit 11, the charging period and the discharging period come alternately.

  In the charging period, the thin film transistors Q1-1 to Q3 and Q2-1 to 3 are turned on, and the thin film transistors Q3-1 to Q3 and Q2-1 to 34 are turned off. That is, the thin film transistors Q1-1 to 3 operate as one switch, the thin film transistors Q2-1 to Q3 operate as one switch, the thin film transistors Q3-1 to Q3 operate as one switch, and the thin film transistors Q4-1 to Q3. Operates as one switch. Thereby, the capacitive element C22 shown in FIG. 9 is charged, and the voltage between the electrodes becomes equal to the voltage VCC.

  Returning to FIG. 10, in the discharge period, the thin film transistors Q3-1 to Q3 and Q4-1 to Q3 are turned on, and the thin film transistors Q1-1 to Q3 and Q2-1 to Q3 are turned off. As a result, the voltage VCC is applied to the negative pole of the capacitive element C22 shown in FIG. 9, and the discharge from the capacitive element C22 to the capacitive element C21 is performed. Therefore, the potential of the positive pole of the capacitive element C21 with respect to the circuit node G Rises.

  By such alternating charging and discharging periods, the potential of the positive electrode of the capacitive element C21 eventually becomes a positive potential that is twice as large as the voltage VCC.

  In consideration of such operation, referring to FIG. 10, thin film transistors that are turned on in the charging period and thin film transistors that are turned on in the discharging period are alternately arranged.

  Therefore, the temperature rise of each thin film transistor can be reduced by the same operation as in the first embodiment. In addition, off-state current and power consumption can be reduced.

  In view of such operational effects, the positions of the thin film transistors Q1-1 to Q3 and Q2-1 to Q3 may be changed. Similarly, the positions of the thin film transistors Q3-1 to Q3-1 and Q3-1 to Q3-1 may be changed.

  Similarly to FIG. 3 and the like, thin film transistors that are turned on in the charging period and thin film transistors that are turned on in the discharging period may be arranged in a staggered pattern.

  Similarly to FIG. 4 and the like, the thin film transistor that is turned on in the charging period and the thin film transistor that is turned on in the discharging period may be formed and arranged so as to be fitted to each other.

  Further, the number of thin film transistors constituting the same switch may be two or four or more.

[Fourth Embodiment]
FIG. 11 is a circuit diagram of the double negative voltage power supply circuit 12 which is a thin film transistor circuit according to the fourth embodiment.

  The double negative voltage power supply circuit 12 includes a capacitive element C31 corresponding to the first capacitive element of the present invention and a capacitive element C32 corresponding to the second capacitive element of the present invention, and the positive electrode of the capacitive element C31 is connected to the ground. Connected to the connected circuit node G.

  The double negative voltage power supply circuit 12 includes P-type thin film transistors Q11-1 to Q11-3, N-type thin film transistors Q12-1 to Q3, Q13-1 to Q3, and Q14-1 to Q14-3 that are formed on an insulator. I have. The thin film transistors Q11-1 to Q3 and Q12-1 to 3 correspond to the first thin film transistor of the present invention, and the thin film transistors Q13-1 to Q13 to Q14-1 to 3 correspond to the second thin film transistor of the present invention.

  The thin film transistors Q11-1 to Q11-3 are connected in parallel, and are inserted between the circuit node A to which a positive voltage VCC is applied to the circuit node G and the positive electrode of the capacitive element C32. The thin film transistors Q12-1 to Q12-3 are connected in parallel and are inserted between the negative pole of the capacitive element C32 and the circuit node G. The thin film transistors Q13-1 to Q13-3 are connected in parallel and are inserted between the negative pole of the capacitive element C31 and the negative pole of the capacitive element C32. The thin film transistors Q14-1 to Q3-3 are connected in parallel and are inserted between the positive electrode of the capacitive element C32 and the circuit node G.

  FIG. 12 is a diagram showing the arrangement and state transition of the thin film transistors in the double negative voltage power supply circuit 12.

  Each thin film transistor is a thin film transistor Q12-1, Q13-1, Q11-1, Q14-1, Q12-2, Q13-2, Q11-2, Q14-2, Q12-3, Q13-3, Q11-3, Q14. Are arranged in the order of -3. In the figure, thin film transistors connected in parallel are connected to each other.

  In the double negative voltage power supply circuit 12, the charging period and the discharging period come alternately.

  In the charging period, the thin film transistors Q11-1 to Q3 and Q12-1 to Q3 are turned on, and the thin film transistors Q13-1 to Q3 and Q14-1 to Q3 are turned off. That is, the thin film transistor Q11-1 to 3 operates as one switch, the thin film transistor Q12-1 to 3 operates as one switch, the thin film transistor Q13-1 to 3 operates as one switch, and the thin film transistors Q14-1 to Q3-3. Operates as one switch. Thereby, the capacitive element C31 shown in FIG. 11 is charged, and the voltage between the electrodes becomes equal to the voltage VCC.

  Returning to FIG. 12, in the discharge period, the thin film transistors Q13-1 to Q3 and Q14-1 to Q3 are turned on, and the thin film transistors Q11-1 to Q3 and Q12-1 to Q3 are turned off. As a result, the positive pole of the capacitive element C31 shown in FIG. 11 is connected to the circuit node G, and the capacitive element C32 is discharged from the capacitive element C31. Therefore, the negative pole of the capacitive element C31 is connected to the circuit node G. The potential drops to a negative potential.

  By such alternating charging and discharging periods, the potential of the negative pole of the capacitive element C31 eventually becomes a negative potential having a magnitude equal to the voltage VCC.

  In consideration of such operation, referring to FIG. 12, thin film transistors that are turned on in the charging period and thin film transistors that are turned on in the discharging period are alternately arranged.

  Therefore, the temperature rise of each thin film transistor can be reduced by the same operation as in the first embodiment. In addition, off-state current and power consumption can be reduced.

  In view of such effects, the positions of the thin film transistors Q11-1 to Q3-3 and Q12-1 to Q12-1 may be changed. Similarly, the positions of the thin film transistors Q13-1 to Q13-3 and Q13-1 to Q13-3 may be changed.

  Similarly to FIG. 7 and the like, thin film transistors that are turned on in the charging period and thin film transistors that are turned on in the discharging period may be arranged in a staggered pattern.

  Similarly to FIG. 8 and the like, a thin film transistor that is turned on in a charging period and a thin film transistor that is turned on in a discharging period may be formed and arranged so as to be fitted to each other.

  Further, the number of thin film transistors constituting the same switch may be two or four or more.

1 is a circuit diagram of a double boost power supply circuit 1 which is a thin film transistor circuit according to a first embodiment. FIG. It is a figure which shows arrangement | positioning and state transition of a thin-film transistor in the double boosting power supply circuit. It is a figure which shows other arrangement | positioning and state transition of the thin-film transistor in the double boosting power supply circuit. It is a figure which shows other shapes and arrangement | positioning and state transition of a thin-film transistor in the double boosting power supply circuit. It is a circuit diagram of the double negative voltage power supply circuit 2 that is a thin film transistor circuit according to a second embodiment. It is a figure which shows arrangement | positioning and state transition of a thin-film transistor in the double negative voltage power supply circuit. It is a figure which shows other arrangement | positioning and state transition of the thin-film transistor in the double negative voltage power supply circuit. It is a figure which shows the other shape and arrangement | positioning and state transition of a thin-film transistor in the double negative voltage power supply circuit 2. FIG. FIG. 6 is a circuit diagram of a double boost power supply circuit 11 which is a thin film transistor circuit according to a third embodiment. FIG. 3 is a diagram showing the arrangement and state transition of thin film transistors in the double boosting power supply circuit 11. It is a circuit diagram of the double negative voltage power supply circuit 12, which is a thin film transistor circuit according to a fourth embodiment. It is a figure which shows arrangement | positioning and state transition of a thin-film transistor in the double negative voltage power supply circuit. FIG. 6 is a diagram showing an off-current in the double boost power supply circuit 1. FIG. 6 is a diagram showing an off-current in the double negative voltage power supply circuit 2; It is a characteristic view of an N-type thin film transistor.

Explanation of symbols

1, 11 Double boosting power supply circuit 2, 12 Equal negative voltage power supply circuit Q1-4, Q11-14, Q1-1-4, Q2-1-4, Q3-1-4, Q4-1-4, Q11 -1 to 4, Q12-1 to 4, Q13-1 to 4, Q14-1 to 4 Thin film transistors C1, C2, C11, C12, C21, C22, C31, C32 capacitive elements

Claims (4)

On the first thin film transistor to turn off, and off period in which the first thin film transistor is turned on, and a second thin film transistor in which the first thin film transistor is turned on during a period of off, on the insulating thin film transistor circuit arranged alternately Because
A first thin film transistor inserted between a circuit node to which a positive voltage is applied to the negative pole of the first capacitive element and the positive pole of the second capacitive element;
A first thin film transistor inserted between a negative pole of the second capacitive element and a negative pole of the first capacitive element;
A second thin film transistor inserted between the circuit node and the negative pole of the second capacitive element;
Thin film transistor circuits you anda second thin film transistor which is inserted between the positive electrode and the positive electrode of the first capacitive element of the second capacitive element. On the first thin film transistor to turn off, and off period in which the first thin film transistor is turned on, and a second thin film transistor in which the first thin film transistor is turned on during a period of off, on the insulating thin Maku transistor circuit arranged alternately Because
A first thin film transistor inserted between a circuit node to which a positive voltage is applied to the positive electrode of the first capacitive element and the positive electrode of the second capacitive element;
A first thin film transistor inserted between a negative pole of the second capacitive element and a positive pole of the first capacitive element;
A second thin film transistor inserted between the negative pole of the first capacitive element and the negative pole of the second capacitive element;
A second thin film transistor inserted between a positive pole of the second capacitive element and a positive pole of the first capacitive element;
Thin Maku transistor circuit you comprising: a. On the first thin film transistor to turn off, and off period in which the first thin film transistor is turned on, and a second thin film transistor in which the first thin film transistor is turned on during a period of off, on the insulating thin film transistor circuit arranged alternately Because
A first switch inserted between a circuit node to which a positive voltage is applied to the negative pole of the first capacitive element and the positive pole of the second capacitive element;
A second switch inserted between the negative pole of the second capacitive element and the negative pole of the first capacitive element;
A third switch inserted between the circuit node and the negative pole of the second capacitive element;
A fourth switch inserted between the positive pole of the second capacitive element and the positive pole of the first capacitive element;
The first switch and the second switch include a plurality of first thin film transistors connected in parallel,
The third switch and the fourth switch, the thin film transistor circuit you characterized by comprising a parallel-connected plurality of second thin film transistor. On the first thin film transistor to turn off, and off period in which the first thin film transistor is turned on, and a second thin film transistor in which the first thin film transistor is turned on during a period of off, on the insulating thin film transistor circuit arranged alternately Because
A first switch inserted between a circuit node to which a positive voltage is applied to the positive pole of the first capacitive element and the positive pole of the second capacitive element;
A second switch inserted between the negative pole of the second capacitive element and the positive pole of the first capacitive element;
A third switch inserted between the negative pole of the first capacitive element and the negative pole of the second capacitive element;
A fourth switch inserted between the positive pole of the second capacitive element and the positive pole of the first capacitive element;
The first switch and the second switch include a plurality of first thin film transistors connected in parallel,
The third switch and the fourth switch, the thin film transistor circuit you characterized by comprising a parallel-connected plurality of second thin film transistor.

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